[llvm] e5a0c30 - AMDGPU: Work around machine verifier failure with convergence tokens
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 4 05:59:30 PDT 2024
Author: Matt Arsenault
Date: 2024-10-04T16:59:23+04:00
New Revision: e5a0c30e4ad6b22b17b72cc40b609905d2f97703
URL: https://github.com/llvm/llvm-project/commit/e5a0c30e4ad6b22b17b72cc40b609905d2f97703
DIFF: https://github.com/llvm/llvm-project/commit/e5a0c30e4ad6b22b17b72cc40b609905d2f97703.diff
LOG: AMDGPU: Work around machine verifier failure with convergence tokens
Apparently any function with convergence tokens will fail the
machine verifier after register allocation. The existing codegen tests
for tokens use stop-before, and do not run to the end. Work around this
by splitting out tests with convergence tokens. Fixes EXPENSIVE_CHECKS
bot failures after c08d7b3de7409aecadd7f9edfe0f3a1ce28a6374 and
428ae0f12e29eff1ddcaf59bdcce904ec056963e
Added:
llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.convergencetokens.ll
llvm/test/CodeGen/AMDGPU/tail-call-uniform-target-in-vgprs-issue110930.convergencetokens.ll
Modified:
llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.ll
llvm/test/CodeGen/AMDGPU/tail-call-uniform-target-in-vgprs-issue110930.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.convergencetokens.ll b/llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.convergencetokens.ll
new file mode 100644
index 00000000000000..42a1f746be3fad
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.convergencetokens.ll
@@ -0,0 +1,56 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -stop-after=si-fix-sgpr-copies < %s | FileCheck %s
+
+; FIXME: Merge with tail-call-inreg-arguments.ll
+
+; Currently all functions with convergence tokens will fail the
+; machine verifier after register allocation.
+declare void @void_func_i64_inreg(i64 inreg)
+
+define void @tail_call_i64_inreg_uniform_in_vgpr_convergence_tokens() #0 {
+ ; CHECK-LABEL: name: tail_call_i64_inreg_uniform_in_vgpr_convergence_tokens
+ ; CHECK: bb.0 (%ir-block.0):
+ ; CHECK-NEXT: liveins: $sgpr4_sgpr5, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr6_sgpr7, $vgpr31
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr31
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr15
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr13
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr12
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9
+ ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
+ ; CHECK-NEXT: [[CONVERGENCECTRL_ENTRY:%[0-9]+]]:sreg_64 = CONVERGENCECTRL_ENTRY
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[DS_READ_B64_gfx9_:%[0-9]+]]:vreg_64 = DS_READ_B64_gfx9 killed [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (load (s64) from `ptr addrspace(3) null`, addrspace 3)
+ ; CHECK-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[DS_READ_B64_gfx9_]].sub1
+ ; CHECK-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[DS_READ_B64_gfx9_]].sub0
+ ; CHECK-NEXT: CONVERGENCECTRL_GLUE [[CONVERGENCECTRL_ENTRY]]
+ ; CHECK-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY10]]
+ ; CHECK-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 killed [[COPY11]], implicit $exec, implicit [[CONVERGENCECTRL_ENTRY]]
+ ; CHECK-NEXT: CONVERGENCECTRL_GLUE [[CONVERGENCECTRL_ENTRY]]
+ ; CHECK-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY9]]
+ ; CHECK-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 killed [[COPY12]], implicit $exec, implicit [[CONVERGENCECTRL_ENTRY]]
+ ; CHECK-NEXT: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @void_func_i64_inreg, target-flags(amdgpu-gotprel32-hi) @void_func_i64_inreg, implicit-def dead $scc
+ ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:ccr_sgpr_64 = S_LOAD_DWORDX2_IMM killed [[SI_PC_ADD_REL_OFFSET]], 0, 0 :: (dereferenceable invariant load (s64) from got, addrspace 4)
+ ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY8]]
+ ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY1]]
+ ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[COPY7]]
+ ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY6]]
+ ; CHECK-NEXT: $sgpr12 = COPY [[COPY5]]
+ ; CHECK-NEXT: $sgpr13 = COPY [[COPY4]]
+ ; CHECK-NEXT: $sgpr14 = COPY [[COPY3]]
+ ; CHECK-NEXT: $sgpr15 = COPY [[COPY2]]
+ ; CHECK-NEXT: $vgpr31 = COPY [[COPY]]
+ ; CHECK-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
+ ; CHECK-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
+ ; CHECK-NEXT: CONVERGENCECTRL_GLUE [[CONVERGENCECTRL_ENTRY]]
+ ; CHECK-NEXT: SI_TCRETURN killed [[S_LOAD_DWORDX2_IMM]], @void_func_i64_inreg, 0, csr_amdgpu, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit $sgpr0, implicit $sgpr1, implicit [[CONVERGENCECTRL_ENTRY]]
+ %t = call token @llvm.experimental.convergence.entry()
+ %uniform.vgpr = load i64, ptr addrspace(3) null, align 8
+ tail call void @void_func_i64_inreg(i64 inreg %uniform.vgpr) #0 [ "convergencectrl"(token %t) ]
+ ret void
+}
+
+attributes #0 = { convergent }
diff --git a/llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.ll b/llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.ll
index 2db62111745f23..9b992c40c28eeb 100644
--- a/llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.ll
+++ b/llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s
declare hidden void @void_func_i32_inreg(i32 inreg)
@@ -72,26 +72,3 @@ define void @tail_call_i64_inreg_uniform_in_vgpr() {
tail call void @void_func_i64_inreg(i64 inreg %uniform.vgpr)
ret void
}
-
-define void @tail_call_i64_inreg_uniform_in_vgpr_convergence_tokens() #0 {
-; CHECK-LABEL: tail_call_i64_inreg_uniform_in_vgpr_convergence_tokens:
-; CHECK: ; %bb.0:
-; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT: v_mov_b32_e32 v0, 0
-; CHECK-NEXT: ds_read_b64 v[0:1], v0
-; CHECK-NEXT: s_getpc_b64 s[18:19]
-; CHECK-NEXT: s_add_u32 s18, s18, void_func_i64_inreg at gotpcrel32@lo+4
-; CHECK-NEXT: s_addc_u32 s19, s19, void_func_i64_inreg at gotpcrel32@hi+12
-; CHECK-NEXT: s_load_dwordx2 s[18:19], s[18:19], 0x0
-; CHECK-NEXT: ; meta instruction
-; CHECK-NEXT: s_waitcnt lgkmcnt(0)
-; CHECK-NEXT: v_readfirstlane_b32 s0, v0
-; CHECK-NEXT: v_readfirstlane_b32 s1, v1
-; CHECK-NEXT: s_setpc_b64 s[18:19]
- %t = call token @llvm.experimental.convergence.entry()
- %uniform.vgpr = load i64, ptr addrspace(3) null, align 8
- tail call void @void_func_i64_inreg(i64 inreg %uniform.vgpr) #0 [ "convergencectrl"(token %t) ]
- ret void
-}
-
-attributes #0 = { convergent }
diff --git a/llvm/test/CodeGen/AMDGPU/tail-call-uniform-target-in-vgprs-issue110930.convergencetokens.ll b/llvm/test/CodeGen/AMDGPU/tail-call-uniform-target-in-vgprs-issue110930.convergencetokens.ll
new file mode 100644
index 00000000000000..3ca2adec90be59
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/tail-call-uniform-target-in-vgprs-issue110930.convergencetokens.ll
@@ -0,0 +1,54 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -stop-after=si-fix-sgpr-copies < %s | FileCheck %s
+
+; FIXME: This should merge with
+; tail-call-uniform-target-in-vgprs-issue110930.ll. This is split
+; because all functions involving convergence tokens will fail the
+; machine verifier after register allocation.
+
+target triple = "amdgcn-amd-amdhsa"
+
+define void @tail_call_uniform_vgpr_value_convergence_tokens() #0 {
+ ; CHECK-LABEL: name: tail_call_uniform_vgpr_value_convergence_tokens
+ ; CHECK: bb.0 (%ir-block.0):
+ ; CHECK-NEXT: liveins: $sgpr4_sgpr5, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr6_sgpr7, $vgpr31
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr31
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr15
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr13
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr12
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9
+ ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
+ ; CHECK-NEXT: [[CONVERGENCECTRL_ENTRY:%[0-9]+]]:sreg_64 = CONVERGENCECTRL_ENTRY
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[DS_READ_B64_gfx9_:%[0-9]+]]:vreg_64 = DS_READ_B64_gfx9 killed [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (load (s64) from `ptr addrspace(3) null`, addrspace 3)
+ ; CHECK-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[DS_READ_B64_gfx9_]].sub1
+ ; CHECK-NEXT: CONVERGENCECTRL_GLUE [[CONVERGENCECTRL_ENTRY]]
+ ; CHECK-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY9]]
+ ; CHECK-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 killed [[COPY10]], implicit $exec, implicit [[CONVERGENCECTRL_ENTRY]]
+ ; CHECK-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[DS_READ_B64_gfx9_]].sub0
+ ; CHECK-NEXT: CONVERGENCECTRL_GLUE [[CONVERGENCECTRL_ENTRY]]
+ ; CHECK-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY11]]
+ ; CHECK-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 killed [[COPY12]], implicit $exec, implicit [[CONVERGENCECTRL_ENTRY]]
+ ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:ccr_sgpr_64 = REG_SEQUENCE killed [[V_READFIRSTLANE_B32_1]], %subreg.sub0, killed [[V_READFIRSTLANE_B32_]], %subreg.sub1
+ ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY8]]
+ ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY1]]
+ ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[COPY7]]
+ ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY6]]
+ ; CHECK-NEXT: $sgpr12 = COPY [[COPY5]]
+ ; CHECK-NEXT: $sgpr13 = COPY [[COPY4]]
+ ; CHECK-NEXT: $sgpr14 = COPY [[COPY3]]
+ ; CHECK-NEXT: $sgpr15 = COPY [[COPY2]]
+ ; CHECK-NEXT: $vgpr31 = COPY [[COPY]]
+ ; CHECK-NEXT: CONVERGENCECTRL_GLUE [[CONVERGENCECTRL_ENTRY]]
+ ; CHECK-NEXT: SI_TCRETURN killed [[REG_SEQUENCE]], 0, 0, csr_amdgpu, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit [[CONVERGENCECTRL_ENTRY]]
+ %t = call token @llvm.experimental.convergence.entry()
+ %fptr = load ptr, ptr addrspace(3) null, align 8
+ tail call void %fptr() #0 [ "convergencectrl"(token %t) ]
+ ret void
+}
+
+attributes #0 = { convergent }
diff --git a/llvm/test/CodeGen/AMDGPU/tail-call-uniform-target-in-vgprs-issue110930.ll b/llvm/test/CodeGen/AMDGPU/tail-call-uniform-target-in-vgprs-issue110930.ll
index 60fe7c47e0df79..b5a68720dc19f5 100644
--- a/llvm/test/CodeGen/AMDGPU/tail-call-uniform-target-in-vgprs-issue110930.ll
+++ b/llvm/test/CodeGen/AMDGPU/tail-call-uniform-target-in-vgprs-issue110930.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s
target triple = "amdgcn-amd-amdhsa"
@@ -37,22 +37,3 @@ define void @tail_call_uniform_sgpr_value() {
tail call void %fptr()
ret void
}
-
-define void @tail_call_uniform_vgpr_value_convergence_tokens() #0 {
-; CHECK-LABEL: tail_call_uniform_vgpr_value_convergence_tokens:
-; CHECK: ; %bb.0:
-; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT: v_mov_b32_e32 v0, 0
-; CHECK-NEXT: ds_read_b64 v[0:1], v0
-; CHECK-NEXT: ; meta instruction
-; CHECK-NEXT: s_waitcnt lgkmcnt(0)
-; CHECK-NEXT: v_readfirstlane_b32 s19, v1
-; CHECK-NEXT: v_readfirstlane_b32 s18, v0
-; CHECK-NEXT: s_setpc_b64 s[18:19]
- %t = call token @llvm.experimental.convergence.entry()
- %fptr = load ptr, ptr addrspace(3) null, align 8
- tail call void %fptr() #0 [ "convergencectrl"(token %t) ]
- ret void
-}
-
-attributes #0 = { convergent }
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