[llvm] [MCP] Skip invalidating constant regs during forward propagation (PR #111129)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-aarch64

Author: Vladimir Radosavljevic (vladimirradosavljevic)

<details>
<summary>Changes</summary>

Before this patch, redundant COPY couldn't be removed for the following case:
```
  %reg1 = COPY %const-reg
  ... // No use of %reg1 but there is a def/use of %const-reg
  %reg2 = COPY killed %reg1
```
where this can be optimized to:
```
  ... // No use of %reg1 but there is a def/use of %const-reg
  %reg2 = COPY %const-reg
```
This patch enables this by skipping invalidating constant regs, which should be safe even for defs since architectures like AArch64 and RISCV for some instructions are replacing a dead definition of a GPR with zero constant register.

---
Full diff: https://github.com/llvm/llvm-project/pull/111129.diff


2 Files Affected:

- (modified) llvm/lib/CodeGen/MachineCopyPropagation.cpp (+4) 
- (added) llvm/test/CodeGen/AArch64/machine-cp-constant-reg.mir (+19) 


``````````diff
diff --git a/llvm/lib/CodeGen/MachineCopyPropagation.cpp b/llvm/lib/CodeGen/MachineCopyPropagation.cpp
index 8bcc437cbfb865..d1f8b0b9729ce7 100644
--- a/llvm/lib/CodeGen/MachineCopyPropagation.cpp
+++ b/llvm/lib/CodeGen/MachineCopyPropagation.cpp
@@ -885,6 +885,10 @@ void MachineCopyPropagation::ForwardCopyPropagateBlock(MachineBasicBlock &MBB) {
       assert(!Reg.isVirtual() &&
              "MachineCopyPropagation should be run after register allocation!");
 
+      // Skip invalidating constant registers.
+      if (MRI->isReserved(Reg) && MRI->isConstantPhysReg(Reg))
+        continue;
+
       if (MO.isDef() && !MO.isEarlyClobber()) {
         Defs.push_back(Reg.asMCReg());
         continue;
diff --git a/llvm/test/CodeGen/AArch64/machine-cp-constant-reg.mir b/llvm/test/CodeGen/AArch64/machine-cp-constant-reg.mir
new file mode 100644
index 00000000000000..da4309a3d4772a
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/machine-cp-constant-reg.mir
@@ -0,0 +1,19 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass machine-cp -verify-machineinstrs -o - %s | FileCheck %s
+
+---
+name: test
+body: |
+  bb.0:
+    liveins: $w2
+    ; CHECK-LABEL: name: test
+    ; CHECK: liveins: $w2
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: dead $wzr = SUBSWri killed renamable $w2, 0, 0, implicit-def $nzcv
+    ; CHECK-NEXT: renamable $w0 = COPY $wzr
+    ; CHECK-NEXT: RET_ReallyLR implicit killed $w0
+    renamable $w1 = COPY $wzr
+    dead $wzr = SUBSWri killed renamable $w2, 0, 0, implicit-def $nzcv
+    renamable $w0 = COPY killed renamable $w1
+    RET_ReallyLR implicit killed $w0
+...

``````````

</details>


https://github.com/llvm/llvm-project/pull/111129