[llvm] [MCP] Skip invalidating constant regs during forward propagation (PR #111129)

[Vladimir Radosavljevic via llvm-commits]

https://github.com/vladimirradosavljevic created https://github.com/llvm/llvm-project/pull/111129

Before this patch, redundant COPY couldn't be removed for the following case:
```
  %reg1 = COPY %const-reg
  ... // No use of %reg1 but there is a def/use of %const-reg
  %reg2 = COPY killed %reg1
```
where this can be optimized to:
```
  ... // No use of %reg1 but there is a def/use of %const-reg
  %reg2 = COPY %const-reg
```
This patch enables this by skipping invalidating constant regs, which should be safe even for defs since architectures like AArch64 and RISCV for some instructions are replacing a dead definition of a GPR with zero constant register.

>From bd7e93f152c0ae6faaa1fe15d47543a8cb12b109 Mon Sep 17 00:00:00 2001
From: Vladimir Radosavljevic <vr at matterlabs.dev>
Date: Thu, 3 Oct 2024 13:55:18 +0200
Subject: [PATCH 1/2] [MCP] NFC: Add pre-commit test

---
 .../AArch64/machine-cp-constant-reg.mir       | 20 +++++++++++++++++++
 1 file changed, 20 insertions(+)
 create mode 100644 llvm/test/CodeGen/AArch64/machine-cp-constant-reg.mir

diff --git a/llvm/test/CodeGen/AArch64/machine-cp-constant-reg.mir b/llvm/test/CodeGen/AArch64/machine-cp-constant-reg.mir
new file mode 100644
index 00000000000000..cb00743d22ceb8
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/machine-cp-constant-reg.mir
@@ -0,0 +1,20 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass machine-cp -verify-machineinstrs -o - %s | FileCheck %s
+
+---
+name: test
+body: |
+  bb.0:
+    liveins: $w2
+    ; CHECK-LABEL: name: test
+    ; CHECK: liveins: $w2
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: renamable $w1 = COPY $wzr
+    ; CHECK-NEXT: dead $wzr = SUBSWri killed renamable $w2, 0, 0, implicit-def $nzcv
+    ; CHECK-NEXT: renamable $w0 = COPY killed renamable $w1
+    ; CHECK-NEXT: RET_ReallyLR implicit killed $w0
+    renamable $w1 = COPY $wzr
+    dead $wzr = SUBSWri killed renamable $w2, 0, 0, implicit-def $nzcv
+    renamable $w0 = COPY killed renamable $w1
+    RET_ReallyLR implicit killed $w0
+...

>From b19c4a47f95e5cf12ecea0f35f076bb47214981c Mon Sep 17 00:00:00 2001
From: Vladimir Radosavljevic <vr at matterlabs.dev>
Date: Thu, 3 Oct 2024 14:19:05 +0200
Subject: [PATCH 2/2] [MCP] Skip invalidating constant regs during forward
 propagation

Before this patch, redundant COPY couldn't be removed
for the following case:
  %reg1 = COPY %const-reg
  ... // No use of %reg1 but there is a def/use of %const-reg
  %reg2 = COPY killed %reg1

where this can be optimized to:
  ... // No use of %reg1 but there is a def/use of %const-reg
  %reg2 = COPY %const-reg

This patch enables this by skipping invalidating constant
regs, which should be safe even for defs since architectures
like AArch64 and RISCV for some instructions are replacing
a dead definition of a GPR with zero constant register.
---
 llvm/lib/CodeGen/MachineCopyPropagation.cpp           | 4 ++++
 llvm/test/CodeGen/AArch64/machine-cp-constant-reg.mir | 3 +--
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/CodeGen/MachineCopyPropagation.cpp b/llvm/lib/CodeGen/MachineCopyPropagation.cpp
index 8bcc437cbfb865..d1f8b0b9729ce7 100644
--- a/llvm/lib/CodeGen/MachineCopyPropagation.cpp
+++ b/llvm/lib/CodeGen/MachineCopyPropagation.cpp
@@ -885,6 +885,10 @@ void MachineCopyPropagation::ForwardCopyPropagateBlock(MachineBasicBlock &MBB) {
       assert(!Reg.isVirtual() &&
              "MachineCopyPropagation should be run after register allocation!");
 
+      // Skip invalidating constant registers.
+      if (MRI->isReserved(Reg) && MRI->isConstantPhysReg(Reg))
+        continue;
+
       if (MO.isDef() && !MO.isEarlyClobber()) {
         Defs.push_back(Reg.asMCReg());
         continue;
diff --git a/llvm/test/CodeGen/AArch64/machine-cp-constant-reg.mir b/llvm/test/CodeGen/AArch64/machine-cp-constant-reg.mir
index cb00743d22ceb8..da4309a3d4772a 100644
--- a/llvm/test/CodeGen/AArch64/machine-cp-constant-reg.mir
+++ b/llvm/test/CodeGen/AArch64/machine-cp-constant-reg.mir
@@ -9,9 +9,8 @@ body: |
     ; CHECK-LABEL: name: test
     ; CHECK: liveins: $w2
     ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: renamable $w1 = COPY $wzr
     ; CHECK-NEXT: dead $wzr = SUBSWri killed renamable $w2, 0, 0, implicit-def $nzcv
-    ; CHECK-NEXT: renamable $w0 = COPY killed renamable $w1
+    ; CHECK-NEXT: renamable $w0 = COPY $wzr
     ; CHECK-NEXT: RET_ReallyLR implicit killed $w0
     renamable $w1 = COPY $wzr
     dead $wzr = SUBSWri killed renamable $w2, 0, 0, implicit-def $nzcv