[llvm] [RISCV][ISel] Allow emitting `addiw` with u32simm12 rhs (PR #111116)

[Yingwei Zheng via llvm-commits]

https://github.com/dtcxzyw created https://github.com/llvm/llvm-project/pull/111116

In InstCombine, we shrink the constant by setting unused bits to zero (e.g. `((X + -2) & 4294967295) -> ((X + 4294967294) & 4294967295)`). However, this canonicalization blocks emitting `addiw` and creates redundant li for simm32 rhs:
```
; bin/llc -mtriple=riscv64 -mattr=+zba test.ll -o -
define i64 @add_u32simm32_zextw(i64 %x) nounwind {
entry:
  %add = add i64 %x, 4294967294
  %and = and i64 %add, 4294967295
  ret i64 %and
}
```
```
add_u32simm32_zextw:                    # @add_u32simm32_zextw
# %bb.0:                                # %entry
        li      a1, -2
        add     a0, a0, a1
        zext.w  a0, a0
        ret
```

This patch addresses the issue by matching u32simm12 rhs.


>From 826b1cb6018e79d3c078139070529fa2e53708e3 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: Fri, 4 Oct 2024 15:32:42 +0800
Subject: [PATCH 1/2] [RISCV][ISel] Add pre-commit tests. NFC.

---
 llvm/test/CodeGen/RISCV/rv64zba.ll | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/llvm/test/CodeGen/RISCV/rv64zba.ll b/llvm/test/CodeGen/RISCV/rv64zba.ll
index a381ee67354b32..f87bf84408d066 100644
--- a/llvm/test/CodeGen/RISCV/rv64zba.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zba.ll
@@ -3217,3 +3217,26 @@ entry:
   %z = and i64 %y, -8192
   ret i64 %z
 }
+
+define i64 @add_u32simm32_zextw(i64 %x) nounwind {
+; RV64I-LABEL: add_u32simm32_zextw:
+; RV64I:       # %bb.0: # %entry
+; RV64I-NEXT:    li a1, 1
+; RV64I-NEXT:    slli a1, a1, 32
+; RV64I-NEXT:    addi a1, a1, -2
+; RV64I-NEXT:    add a0, a0, a1
+; RV64I-NEXT:    addi a1, a1, 1
+; RV64I-NEXT:    and a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64ZBA-LABEL: add_u32simm32_zextw:
+; RV64ZBA:       # %bb.0: # %entry
+; RV64ZBA-NEXT:    li a1, -2
+; RV64ZBA-NEXT:    add a0, a0, a1
+; RV64ZBA-NEXT:    zext.w a0, a0
+; RV64ZBA-NEXT:    ret
+entry:
+  %add = add i64 %x, 4294967294
+  %and = and i64 %add, 4294967295
+  ret i64 %and
+}

>From 949744e940b73c13f8a7725e965b596172112a5c Mon Sep 17 00:00:00 2001
From: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: Fri, 4 Oct 2024 15:55:20 +0800
Subject: [PATCH 2/2] [RISCV][ISel] Allow emit addiw with u32simm12 rhs

---
 llvm/lib/Target/RISCV/RISCVInstrInfo.td | 1 +
 llvm/test/CodeGen/RISCV/rv64zba.ll      | 3 +--
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index a2f1e3ded18fe0..c22d83a71872aa 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1896,6 +1896,7 @@ def : PatGprGpr<shiftopw<riscv_sraw>, SRAW>;
 // Select W instructions if only the lower 32 bits of the result are used.
 def : PatGprGpr<binop_allwusers<add>, ADDW>;
 def : PatGprSimm12<binop_allwusers<add>, ADDIW>;
+def : PatGprImm<binop_allwusers<add>, ADDIW, u32simm12>;
 def : PatGprGpr<binop_allwusers<sub>, SUBW>;
 def : PatGprImm<binop_allwusers<shl>, SLLIW, uimm5>;
 
diff --git a/llvm/test/CodeGen/RISCV/rv64zba.ll b/llvm/test/CodeGen/RISCV/rv64zba.ll
index f87bf84408d066..05b411bb12a241 100644
--- a/llvm/test/CodeGen/RISCV/rv64zba.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zba.ll
@@ -3231,8 +3231,7 @@ define i64 @add_u32simm32_zextw(i64 %x) nounwind {
 ;
 ; RV64ZBA-LABEL: add_u32simm32_zextw:
 ; RV64ZBA:       # %bb.0: # %entry
-; RV64ZBA-NEXT:    li a1, -2
-; RV64ZBA-NEXT:    add a0, a0, a1
+; RV64ZBA-NEXT:    addi a0, a0, -2
 ; RV64ZBA-NEXT:    zext.w a0, a0
 ; RV64ZBA-NEXT:    ret
 entry: