[llvm] [AMDGPU][GlobalISel] Align `selectVOP3PMadMixModsImpl` with the `SelectionDAG` counterpart (PR #110168)

[Matt Arsenault via llvm-commits]

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@@ -0,0 +1,23 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx908 -denormal-fp-math=preserve-sign -verify-machineinstrs %s -o - | FileCheck %s
+
+define amdgpu_ps float @foo(i32 inreg %val.0, i32 inreg %val.1) {
+; CHECK-LABEL: foo:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_lshr_b32 s1, s1, 16
+; CHECK-NEXT:    s_lshr_b32 s0, s0, 16
+; CHECK-NEXT:    v_mov_b32_e32 v0, s1
+; CHECK-NEXT:    v_fma_mix_f32 v0, s0, -s0, v0 op_sel_hi:[1,1,1]
+; CHECK-NEXT:    ; return to shader part epilog
+  %lshr.0 = lshr i32 %val.0, 16
+  %lshr.1 = lshr i32 %val.1, 16
+  %trunc.0 = trunc i32 %lshr.0 to i16
+  %trunc.1 = trunc i32 %lshr.1 to i16
+  %cast.0 = bitcast i16 %trunc.0 to half
+  %cast.1 = bitcast i16 %trunc.1 to half
+  %fpext.0 = fpext half %cast.0 to float
+  %fpext.1 = fpext half %cast.1 to float
+  %fneg = fneg float %fpext.0
+  %fma = call float @llvm.fma.f32(float %fpext.0, float %fneg, float %fpext.1)
+  ret float %fma
+}
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arsenm wrote:

Test all the combinations of SGPR in each position. We probably already have a comprehensive test for selectiondag, maybe should just add a run line there 

https://github.com/llvm/llvm-project/pull/110168