[llvm] [AMDGPU][MC] Disallow op_sel in v_dot4 and v_dot8 with 4- or 8-bit packed data (PR #100485)

[Joe Nash via llvm-commits]

Sisyph wrote:

Sp3 does not support op_sel for dot4* or dot8* instructions on any of gfxip 908,90a,940,1030,11, or 12. 
None of those ISA manuals say the instructions should support op_sel.
I don't see any docs on what the semantics of opsel on those instructions would be.
The only mention of opsel on these instructions in the programming guide is in GFX11 and GFX12. It says if you use inline constants they 'use 32bit inline src0/1 (ignore OPSEL)'. We use i32 fields for those operands in tablegen, so that looks fine as is.
We don't use op_sel in codegen on those instructions. So this will not be a functional change to codegen, only the asm/disasm (please correct me if I'm wrong on this).

However, @DadSchoorse  reports some semantics on how op_sel might work on these instructions. Is that claim from experimentation on hardware, or something else?

It might be best to leave the assembler/disassembler as is, and make sure we continue to not use op_sel in codegen. If we do want to change these, please change them across all targets. 

https://github.com/llvm/llvm-project/pull/100485