[llvm] [RISCV] Allow hoisting VXRM writes out of loops speculatively (PR #110044)

[Craig Topper via llvm-commits]

topperc wrote:

> Hello,
> 
> I added a TuneVXRMPipelineFlush subfeature and conditioned the changes to VXRM on this. I added this subtarget feature to P470 and P670 and changed the tests accordingly.
> 
> I didn't find the SpacemiT K1 processor definition for the BPI. And probably other CPUs could benefit from this as well. Let me know if I should add that to any other processors.

`def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60"` is the BPI

https://github.com/llvm/llvm-project/pull/110044