[llvm] 144dc4c - [RISCV][GISel] Remove some unneeded isel patterns.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 3 09:47:04 PDT 2024
Author: Craig Topper
Date: 2024-10-03T09:46:20-07:00
New Revision: 144dc4c3b152ccc7da340c0493da0308a577e5ad
URL: https://github.com/llvm/llvm-project/commit/144dc4c3b152ccc7da340c0493da0308a577e5ad
DIFF: https://github.com/llvm/llvm-project/commit/144dc4c3b152ccc7da340c0493da0308a577e5ad.diff
LOG: [RISCV][GISel] Remove some unneeded isel patterns.
These use riscv_ SDNodes that don't have GISel equivalents yet or
for extensions that we haven't added tests for yet.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVGISel.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVGISel.td b/llvm/lib/Target/RISCV/RISCVGISel.td
index 2f1fa1d548f5f9..a65577b9cacdae 100644
--- a/llvm/lib/Target/RISCV/RISCVGISel.td
+++ b/llvm/lib/Target/RISCV/RISCVGISel.td
@@ -244,79 +244,10 @@ def : PatGprGpr<srem, REMW, i32, i32>;
def : PatGprGpr<urem, REMUW, i32, i32>;
}
-//===----------------------------------------------------------------------===//
-// Atomic RV64 i32 patterns not used by SelectionDAG
-//===----------------------------------------------------------------------===//
-
-class PatGprGprA<SDPatternOperator OpNode, RVInst Inst, ValueType vt>
- : Pat<(vt (OpNode (XLenVT GPR:$rs1), (vt GPR:$rs2))), (Inst GPR:$rs1, GPR:$rs2)>;
-
-multiclass AMOPat2<string AtomicOp, string BaseInst, ValueType vt = XLenVT,
- list<Predicate> ExtraPreds = []> {
-let Predicates = !listconcat([HasStdExtA, NotHasStdExtZtso], ExtraPreds) in {
- def : PatGprGprA<!cast<PatFrag>(AtomicOp#"_monotonic"),
- !cast<RVInst>(BaseInst), vt>;
- def : PatGprGprA<!cast<PatFrag>(AtomicOp#"_acquire"),
- !cast<RVInst>(BaseInst#"_AQ"), vt>;
- def : PatGprGprA<!cast<PatFrag>(AtomicOp#"_release"),
- !cast<RVInst>(BaseInst#"_RL"), vt>;
- def : PatGprGprA<!cast<PatFrag>(AtomicOp#"_acq_rel"),
- !cast<RVInst>(BaseInst#"_AQ_RL"), vt>;
- def : PatGprGprA<!cast<PatFrag>(AtomicOp#"_seq_cst"),
- !cast<RVInst>(BaseInst#"_AQ_RL"), vt>;
-}
-let Predicates = !listconcat([HasStdExtA, HasStdExtZtso], ExtraPreds) in {
- def : PatGprGprA<!cast<PatFrag>(AtomicOp#"_monotonic"),
- !cast<RVInst>(BaseInst), vt>;
- def : PatGprGprA<!cast<PatFrag>(AtomicOp#"_acquire"),
- !cast<RVInst>(BaseInst), vt>;
- def : PatGprGprA<!cast<PatFrag>(AtomicOp#"_release"),
- !cast<RVInst>(BaseInst), vt>;
- def : PatGprGprA<!cast<PatFrag>(AtomicOp#"_acq_rel"),
- !cast<RVInst>(BaseInst), vt>;
- def : PatGprGprA<!cast<PatFrag>(AtomicOp#"_seq_cst"),
- !cast<RVInst>(BaseInst), vt>;
-}
-}
-
-defm : AMOPat2<"atomic_swap_i32", "AMOSWAP_W", i32>;
-defm : AMOPat2<"atomic_load_add_i32", "AMOADD_W", i32>;
-defm : AMOPat2<"atomic_load_and_i32", "AMOAND_W", i32>;
-defm : AMOPat2<"atomic_load_or_i32", "AMOOR_W", i32>;
-defm : AMOPat2<"atomic_load_xor_i32", "AMOXOR_W", i32>;
-defm : AMOPat2<"atomic_load_max_i32", "AMOMAX_W", i32>;
-defm : AMOPat2<"atomic_load_min_i32", "AMOMIN_W", i32>;
-defm : AMOPat2<"atomic_load_umax_i32", "AMOMAXU_W", i32>;
-defm : AMOPat2<"atomic_load_umin_i32", "AMOMINU_W", i32>;
-
-let Predicates = [HasStdExtA, IsRV64] in
-defm : PseudoCmpXchgPat<"atomic_cmp_swap_i32", PseudoCmpXchg32, i32>;
-
-let Predicates = [HasAtomicLdSt] in {
- def : LdPat<atomic_load_8, LB, i32>;
- def : LdPat<atomic_load_16, LH, i32>;
- def : LdPat<atomic_load_32, LW, i32>;
-
- def : StPat<atomic_store_8, SB, GPR, i32>;
- def : StPat<atomic_store_16, SH, GPR, i32>;
- def : StPat<atomic_store_32, SW, GPR, i32>;
-}
-
-
//===----------------------------------------------------------------------===//
// Zb* RV64 i32 patterns not used by SelectionDAG.
//===----------------------------------------------------------------------===//
-def zexti16i32 : ComplexPattern<i32, 1, "selectZExtBits<16>">;
-def zexti8i32 : ComplexPattern<i32, 1, "selectZExtBits<8>">;
-
-def BCLRMaski32 : ImmLeaf<i32, [{
- return !isInt<12>(Imm) && isPowerOf2_32(~Imm);
-}]>;
-def SingleBitSetMaski32 : ImmLeaf<i32, [{
- return !isInt<12>(Imm) && isPowerOf2_32(Imm);
-}]>;
-
let Predicates = [HasStdExtZbb, IsRV64] in {
def : PatGpr<ctlz, CLZW, i32>;
def : PatGpr<cttz, CTZW, i32>;
@@ -328,10 +259,6 @@ def : Pat<(i32 (sext_inreg GPR:$rs1, i16)), (SEXT_H GPR:$rs1)>;
def : Pat<(i32 (and GPR:$rs, 0xFFFF)), (ZEXT_H_RV64 GPR:$rs)>;
} // Predicates = [HasStdExtZbb, IsRV64]
-let Predicates = [HasStdExtZbkb, NoStdExtZbb, IsRV64] in {
-def : Pat<(i32 (and GPR:$rs, 0xFFFF)), (PACKW GPR:$rs, (XLenVT X0))>;
-}
-
let Predicates = [HasStdExtZbbOrZbkb, IsRV64] in {
def : Pat<(i32 (and GPR:$rs1, (not GPR:$rs2))), (ANDN GPR:$rs1, GPR:$rs2)>;
def : Pat<(i32 (or GPR:$rs1, (not GPR:$rs2))), (ORN GPR:$rs1, GPR:$rs2)>;
@@ -346,21 +273,6 @@ def : Pat<(i32 (rotl GPR:$rs1, uimm5i32:$rs2)),
(RORIW GPR:$rs1, (ImmSubFrom32 uimm5i32:$rs2))>;
} // Predicates = [HasStdExtZbbOrZbkb, IsRV64]
-let Predicates = [HasStdExtZbkb, IsRV64] in {
-def : Pat<(or (and (shl GPR:$rs2, (i64 8)), 0xFFFF),
- (zexti8i32 (i32 GPR:$rs1))),
- (PACKH GPR:$rs1, GPR:$rs2)>;
-def : Pat<(or (shl (zexti8i32 (i32 GPR:$rs2)), (i64 8)),
- (zexti8i32 (i32 GPR:$rs1))),
- (PACKH GPR:$rs1, GPR:$rs2)>;
-def : Pat<(and (anyext (or (shl GPR:$rs2, (XLenVT 8)),
- (zexti8i32 (i32 GPR:$rs1)))), 0xFFFF),
- (PACKH GPR:$rs1, GPR:$rs2)>;
-
-def : Pat<(i32 (or (shl GPR:$rs2, (i64 16)), (zexti16i32 (i32 GPR:$rs1)))),
- (PACKW GPR:$rs1, GPR:$rs2)>;
-} // Predicates = [HasStdExtZbkb, IsRV64]
-
let Predicates = [HasStdExtZba, IsRV64] in {
def : Pat<(shl (i64 (zext i32:$rs1)), uimm5:$shamt),
(SLLI_UW GPR:$rs1, uimm5:$shamt)>;
@@ -373,96 +285,5 @@ foreach i = {1,2,3} in {
defvar shxadd = !cast<Instruction>("SH"#i#"ADD");
def : Pat<(i32 (add_like_non_imm12 (shl GPR:$rs1, (i32 i)), GPR:$rs2)),
(shxadd GPR:$rs1, GPR:$rs2)>;
- def : Pat<(i32 (riscv_shl_add GPR:$rs1, (i32 i), GPR:$rs2)),
- (shxadd GPR:$rs1, GPR:$rs2)>;
-}
-}
-
-let Predicates = [HasStdExtZbs, IsRV64] in {
-def : Pat<(i32 (and (not (shiftop<shl> 1, (i64 GPR:$rs2))), GPR:$rs1)),
- (BCLR GPR:$rs1, GPR:$rs2)>;
-def : Pat<(i32 (and (rotl -2, (i64 GPR:$rs2)), GPR:$rs1)),
- (BCLR GPR:$rs1, GPR:$rs2)>;
-def : Pat<(i32 (or (shiftop<shl> 1, (i64 GPR:$rs2)), GPR:$rs1)),
- (BSET GPR:$rs1, GPR:$rs2)>;
-def : Pat<(i32 (xor (shiftop<shl> 1, (i64 GPR:$rs2)), GPR:$rs1)),
- (BINV GPR:$rs1, GPR:$rs2)>;
-def : Pat<(i32 (and (shiftop<srl> GPR:$rs1, (i64 GPR:$rs2)), 1)),
- (BEXT GPR:$rs1, GPR:$rs2)>;
-def : Pat<(i64 (and (anyext (i32 (shiftop<srl> GPR:$rs1, (i64 GPR:$rs2)))), 1)),
- (BEXT GPR:$rs1, GPR:$rs2)>;
-
-def : Pat<(i32 (shiftop<shl> 1, (i64 GPR:$rs2))),
- (BSET (XLenVT X0), GPR:$rs2)>;
-def : Pat<(i32 (not (shiftop<shl> -1, (i64 GPR:$rs2)))),
- (ADDI (i32 (BSET (XLenVT X0), GPR:$rs2)), -1)>;
-
-def : Pat<(i32 (and (srl GPR:$rs1, uimm5:$shamt), (i32 1))),
- (BEXTI GPR:$rs1, uimm5:$shamt)>;
-
-def : Pat<(i32 (and GPR:$rs1, BCLRMaski32:$mask)),
- (BCLRI GPR:$rs1, (i64 (BCLRXForm $mask)))>;
-def : Pat<(i32 (or GPR:$rs1, SingleBitSetMaski32:$mask)),
- (BSETI GPR:$rs1, (i64 (SingleBitSetMaskToIndex $mask)))>;
-def : Pat<(i32 (xor GPR:$rs1, SingleBitSetMaski32:$mask)),
- (BINVI GPR:$rs1, (i64 (SingleBitSetMaskToIndex $mask)))>;
-} // Predicates = [HasStdExtZbs, IsRV64]
-
-//===----------------------------------------------------------------------===//
-// XTHead RV64 i32 patterns not used by SelectionDAG.
-//===----------------------------------------------------------------------===//
-
-def sexti16i32 : ComplexPattern<i32, 1, "selectSExtBits<16>">;
-
-let Predicates = [HasVendorXTHeadMemIdx, IsRV64] in {
-defm : StoreUpdatePat<post_truncsti8, TH_SBIA, i32>;
-defm : StoreUpdatePat<pre_truncsti8, TH_SBIB, i32>;
-defm : StoreUpdatePat<post_truncsti16, TH_SHIA, i32>;
-defm : StoreUpdatePat<pre_truncsti16, TH_SHIB, i32>;
-
-defm : StIdxPat<truncstorei8, TH_SRB, GPR, i32>;
-defm : StIdxPat<truncstorei16, TH_SRH, GPR, i32>;
-
-defm : StZextIdxPat<truncstorei8, TH_SURB, GPR, i32>;
-defm : StZextIdxPat<truncstorei16, TH_SURH, GPR, i32>;
-defm : StZextIdxPat<store, TH_SURW, GPR, i32>;
}
-
-let Predicates = [HasVendorXTHeadCondMov, IsRV64] in {
-def : Pat<(select (XLenVT GPR:$cond), (i32 GPR:$a), (i32 GPR:$b)),
- (TH_MVEQZ GPR:$a, GPR:$b, GPR:$cond)>;
-def : Pat<(select (XLenVT GPR:$cond), (i32 GPR:$a), (i32 0)),
- (TH_MVEQZ GPR:$a, (XLenVT X0), GPR:$cond)>;
-def : Pat<(select (XLenVT GPR:$cond), (i32 0), (i32 GPR:$b)),
- (TH_MVNEZ GPR:$b, (XLenVT X0), GPR:$cond)>;
-
-def : Pat<(select (riscv_seteq (XLenVT GPR:$cond)), (i32 GPR:$a), (i32 GPR:$b)),
- (TH_MVNEZ GPR:$a, GPR:$b, GPR:$cond)>;
-def : Pat<(select (riscv_setne (XLenVT GPR:$cond)), (i32 GPR:$a), (i32 GPR:$b)),
- (TH_MVEQZ GPR:$a, GPR:$b, GPR:$cond)>;
-def : Pat<(select (riscv_seteq (XLenVT GPR:$cond)), (i32 GPR:$a), (i32 0)),
- (TH_MVNEZ GPR:$a, (XLenVT X0), GPR:$cond)>;
-def : Pat<(select (riscv_setne (XLenVT GPR:$cond)), (i32 GPR:$a), (i32 0)),
- (TH_MVEQZ GPR:$a, (XLenVT X0), GPR:$cond)>;
-def : Pat<(select (riscv_seteq (XLenVT GPR:$cond)), (i32 0), (i32 GPR:$b)),
- (TH_MVEQZ GPR:$b, (XLenVT X0), GPR:$cond)>;
-def : Pat<(select (riscv_setne (XLenVT GPR:$cond)), (i32 0), (i32 GPR:$b)),
- (TH_MVNEZ GPR:$b, (XLenVT X0), GPR:$cond)>;
-} // Predicates = [HasVendorXTHeadCondMov]
-
-let Predicates = [HasVendorXTHeadMac, IsRV64] in {
-// mulaw, mulsw are available only in RV64.
-def : Pat<(i32 (add GPR:$rd, (mul GPR:$rs1, GPR:$rs2))),
- (TH_MULAW GPR:$rd, GPR:$rs1, GPR:$rs2)>;
-def : Pat<(i32 (sub GPR:$rd, (mul GPR:$rs1, GPR:$rs2))),
- (TH_MULSW GPR:$rd, GPR:$rs1, GPR:$rs2)>;
-// mulah, mulsh produce a sign-extended result.
-def : Pat<(i32 (add GPR:$rd,
- (mul (sexti16i32 (i32 GPR:$rs1)),
- (sexti16i32 (i32 GPR:$rs2))))),
- (TH_MULAH GPR:$rd, GPR:$rs1, GPR:$rs2)>;
-def : Pat<(i32 (sub GPR:$rd,
- (mul (sexti16i32 (i32 GPR:$rs1)),
- (sexti16i32 (i32 GPR:$rs2))))),
- (TH_MULSH GPR:$rd, GPR:$rs1, GPR:$rs2)>;
}
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