[llvm] 487686b - [SDAG][RISCV] Don't promote VP_REDUCE_{FADD, FMUL} (#111000)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 3 09:17:48 PDT 2024
Author: Luke Lau
Date: 2024-10-04T00:17:45+08:00
New Revision: 487686b82e9a20bd090704e04c8cbf7207dd6527
URL: https://github.com/llvm/llvm-project/commit/487686b82e9a20bd090704e04c8cbf7207dd6527
DIFF: https://github.com/llvm/llvm-project/commit/487686b82e9a20bd090704e04c8cbf7207dd6527.diff
LOG: [SDAG][RISCV] Don't promote VP_REDUCE_{FADD,FMUL} (#111000)
In https://reviews.llvm.org/D153848, promotion was added for a variety
of f16 ops with zvfhmin, including VP reductions.
However I don't believe it's correct to promote f16 fadd or fmul
reductions to f32 since we need to round the intermediate results.
Today if we lower @llvm.vp.reduce.fadd.nxv1f16 on RISC-V, we'll get two
different results depending on whether we compiled with +zvfh or
+zvfhmin, for example with a 3 element reduction:
; v9 = [0.1563, 5.97e-8, 0.00006104]
; zvfh
vsetivli x0, 3, e16, m1, ta, ma
vmv.v.i v8, 0
vfredosum.vs v8, v9, v8
vfmv.f.s fa0, v8
; fa0 = 0.1563
; zvfhmin
vsetivli x0, 3, e16, m1, ta, ma
vfwcvt.f.f.v v10, v9
vsetivli x0, 3, e32, m1, ta, ma
vmv.v.i v8, 0
vfredosum.vs v8, v10, v8
vfmv.f.s fa0, v8
fcvt.h.s fa0, fa0
; fa0 = 0.1564
This same thing happens with reassociative reductions e.g. vfredusum.vs,
and this also applies for bf16.
I couldn't find anything in the LangRef for reductions that suggest the
excess precision is allowed. There may be something we can do in Clang
with -fexcess-precision=fast, but I haven't looked into this yet.
I presume the same precision issue occurs with fmul, but not with
fmin/fmax/fminimum/fmaximum.
I can't think of another way of lowering these other than scalarizing,
and we can't scalarize scalable vectors, so this just removes the
promotion and adjusts the cost model to return an invalid cost. (It
looks like we also don't currently cost fmul reductions, so presumably
they also have an invalid cost?)
I think this should be enough to stop the loop vectorizer or SLP from
emitting these intrinsics.
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
llvm/test/Analysis/CostModel/RISCV/reduce-fadd.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 04eb891f719d28..42d031310d5e02 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -5851,13 +5851,10 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
DAG.getIntPtrConstant(0, dl, /*isTarget=*/true)));
break;
}
- case ISD::VP_REDUCE_FADD:
- case ISD::VP_REDUCE_FMUL:
case ISD::VP_REDUCE_FMAX:
case ISD::VP_REDUCE_FMIN:
case ISD::VP_REDUCE_FMAXIMUM:
case ISD::VP_REDUCE_FMINIMUM:
- case ISD::VP_REDUCE_SEQ_FADD:
Results.push_back(PromoteReduction(Node));
break;
}
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index a0f885695c2051..3e06960092cf32 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -957,8 +957,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
ISD::VP_FMUL,
ISD::VP_FDIV,
ISD::VP_FMA,
- ISD::VP_REDUCE_FADD,
- ISD::VP_REDUCE_SEQ_FADD,
ISD::VP_REDUCE_FMIN,
ISD::VP_REDUCE_FMAX,
ISD::VP_SQRT,
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index c042782389f188..a61461681f79ed 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -1531,6 +1531,11 @@ RISCVTTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *Ty,
Opcodes = {RISCV::VMV_S_X, RISCV::VREDAND_VS, RISCV::VMV_X_S};
break;
case ISD::FADD:
+ // We can't promote f16/bf16 fadd reductions.
+ if ((LT.second.getVectorElementType() == MVT::f16 &&
+ !ST->hasVInstructionsF16()) ||
+ LT.second.getVectorElementType() == MVT::bf16)
+ return InstructionCost::getInvalid();
SplitOp = RISCV::VFADD_VV;
Opcodes = {RISCV::VFMV_S_F, RISCV::VFREDUSUM_VS, RISCV::VFMV_F_S};
break;
diff --git a/llvm/test/Analysis/CostModel/RISCV/reduce-fadd.ll b/llvm/test/Analysis/CostModel/RISCV/reduce-fadd.ll
index 71f614d7003fad..afb2b644645218 100644
--- a/llvm/test/Analysis/CostModel/RISCV/reduce-fadd.ll
+++ b/llvm/test/Analysis/CostModel/RISCV/reduce-fadd.ll
@@ -1,18 +1,30 @@
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
-; RUN: opt < %s -mtriple=riscv64 -mattr=+v,+zfh,+zvfh -passes="print<cost-model>" -cost-kind=throughput 2>&1 -disable-output | FileCheck %s --check-prefix=FP-REDUCE
+; RUN: opt < %s -mtriple=riscv64 -mattr=+v,+zfh,+zvfh -passes="print<cost-model>" -cost-kind=throughput 2>&1 -disable-output | FileCheck %s --check-prefixes=FP-REDUCE,FP-REDUCE-ZVFH
+; RUN: opt < %s -mtriple=riscv64 -mattr=+v,+zfh,+zvfhmin -passes="print<cost-model>" -cost-kind=throughput 2>&1 -disable-output | FileCheck %s --check-prefixes=FP-REDUCE,FP-REDUCE-ZVFHMIN
; RUN: opt < %s -mtriple=riscv64 -mattr=+v,+zfh,+zvfh -passes="print<cost-model>" -cost-kind=code-size 2>&1 -disable-output | FileCheck %s --check-prefix=SIZE
define void @reduce_fadd_half() {
-; FP-REDUCE-LABEL: 'reduce_fadd_half'
-; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1 = call fast half @llvm.vector.reduce.fadd.v1f16(half 0xH0000, <1 x half> undef)
-; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call fast half @llvm.vector.reduce.fadd.v2f16(half 0xH0000, <2 x half> undef)
-; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4 = call fast half @llvm.vector.reduce.fadd.v4f16(half 0xH0000, <4 x half> undef)
-; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V8 = call fast half @llvm.vector.reduce.fadd.v8f16(half 0xH0000, <8 x half> undef)
-; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call fast half @llvm.vector.reduce.fadd.v16f16(half 0xH0000, <16 x half> undef)
-; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %v32 = call fast half @llvm.vector.reduce.fadd.v32f16(half 0xH0000, <32 x half> undef)
-; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V64 = call fast half @llvm.vector.reduce.fadd.v64f16(half 0xH0000, <64 x half> undef)
-; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V128 = call fast half @llvm.vector.reduce.fadd.v128f16(half 0xH0000, <128 x half> undef)
-; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
+; FP-REDUCE-ZVFH-LABEL: 'reduce_fadd_half'
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1 = call fast half @llvm.vector.reduce.fadd.v1f16(half 0xH0000, <1 x half> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call fast half @llvm.vector.reduce.fadd.v2f16(half 0xH0000, <2 x half> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4 = call fast half @llvm.vector.reduce.fadd.v4f16(half 0xH0000, <4 x half> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V8 = call fast half @llvm.vector.reduce.fadd.v8f16(half 0xH0000, <8 x half> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call fast half @llvm.vector.reduce.fadd.v16f16(half 0xH0000, <16 x half> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %v32 = call fast half @llvm.vector.reduce.fadd.v32f16(half 0xH0000, <32 x half> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V64 = call fast half @llvm.vector.reduce.fadd.v64f16(half 0xH0000, <64 x half> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V128 = call fast half @llvm.vector.reduce.fadd.v128f16(half 0xH0000, <128 x half> undef)
+; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+; FP-REDUCE-ZVFHMIN-LABEL: 'reduce_fadd_half'
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %V1 = call fast half @llvm.vector.reduce.fadd.v1f16(half 0xH0000, <1 x half> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %V2 = call fast half @llvm.vector.reduce.fadd.v2f16(half 0xH0000, <2 x half> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %V4 = call fast half @llvm.vector.reduce.fadd.v4f16(half 0xH0000, <4 x half> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %V8 = call fast half @llvm.vector.reduce.fadd.v8f16(half 0xH0000, <8 x half> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %V16 = call fast half @llvm.vector.reduce.fadd.v16f16(half 0xH0000, <16 x half> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %v32 = call fast half @llvm.vector.reduce.fadd.v32f16(half 0xH0000, <32 x half> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %V64 = call fast half @llvm.vector.reduce.fadd.v64f16(half 0xH0000, <64 x half> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %V128 = call fast half @llvm.vector.reduce.fadd.v128f16(half 0xH0000, <128 x half> undef)
+; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; SIZE-LABEL: 'reduce_fadd_half'
; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1 = call fast half @llvm.vector.reduce.fadd.v1f16(half 0xH0000, <1 x half> undef)
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
index 793e8eb5aee6a7..6d5be7f14bf70b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
@@ -1,63 +1,33 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \
-; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
+; RUN: -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \
-; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
-; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v -target-abi=ilp32d \
-; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
-; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v -target-abi=lp64d \
-; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
+; RUN: -verify-machineinstrs < %s | FileCheck %s
declare half @llvm.vp.reduce.fadd.v2f16(half, <2 x half>, <2 x i1>, i32)
define half @vpreduce_fadd_v2f16(half %s, <2 x half> %v, <2 x i1> %m, i32 zeroext %evl) {
-; ZVFH-LABEL: vpreduce_fadd_v2f16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; ZVFH-NEXT: vfmv.s.f v9, fa0
-; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFH-NEXT: vfredusum.vs v9, v8, v9, v0.t
-; ZVFH-NEXT: vfmv.f.s fa0, v9
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vpreduce_fadd_v2f16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
-; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVFHMIN-NEXT: vfmv.s.f v8, fa5
-; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; ZVFHMIN-NEXT: vfredusum.vs v8, v9, v8, v0.t
-; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
-; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
-; ZVFHMIN-NEXT: ret
+; CHECK-LABEL: vpreduce_fadd_v2f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; CHECK-NEXT: vfmv.s.f v9, fa0
+; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; CHECK-NEXT: vfredusum.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vfmv.f.s fa0, v9
+; CHECK-NEXT: ret
%r = call reassoc half @llvm.vp.reduce.fadd.v2f16(half %s, <2 x half> %v, <2 x i1> %m, i32 %evl)
ret half %r
}
define half @vpreduce_ord_fadd_v2f16(half %s, <2 x half> %v, <2 x i1> %m, i32 zeroext %evl) {
-; ZVFH-LABEL: vpreduce_ord_fadd_v2f16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; ZVFH-NEXT: vfmv.s.f v9, fa0
-; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFH-NEXT: vfredosum.vs v9, v8, v9, v0.t
-; ZVFH-NEXT: vfmv.f.s fa0, v9
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vpreduce_ord_fadd_v2f16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
-; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVFHMIN-NEXT: vfmv.s.f v8, fa5
-; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; ZVFHMIN-NEXT: vfredosum.vs v8, v9, v8, v0.t
-; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
-; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
-; ZVFHMIN-NEXT: ret
+; CHECK-LABEL: vpreduce_ord_fadd_v2f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; CHECK-NEXT: vfmv.s.f v9, fa0
+; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; CHECK-NEXT: vfredosum.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vfmv.f.s fa0, v9
+; CHECK-NEXT: ret
%r = call half @llvm.vp.reduce.fadd.v2f16(half %s, <2 x half> %v, <2 x i1> %m, i32 %evl)
ret half %r
}
@@ -65,53 +35,27 @@ define half @vpreduce_ord_fadd_v2f16(half %s, <2 x half> %v, <2 x i1> %m, i32 ze
declare half @llvm.vp.reduce.fadd.v4f16(half, <4 x half>, <4 x i1>, i32)
define half @vpreduce_fadd_v4f16(half %s, <4 x half> %v, <4 x i1> %m, i32 zeroext %evl) {
-; ZVFH-LABEL: vpreduce_fadd_v4f16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; ZVFH-NEXT: vfmv.s.f v9, fa0
-; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFH-NEXT: vfredusum.vs v9, v8, v9, v0.t
-; ZVFH-NEXT: vfmv.f.s fa0, v9
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vpreduce_fadd_v4f16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
-; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFHMIN-NEXT: vfmv.s.f v8, fa5
-; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; ZVFHMIN-NEXT: vfredusum.vs v8, v9, v8, v0.t
-; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
-; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
-; ZVFHMIN-NEXT: ret
+; CHECK-LABEL: vpreduce_fadd_v4f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; CHECK-NEXT: vfmv.s.f v9, fa0
+; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; CHECK-NEXT: vfredusum.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vfmv.f.s fa0, v9
+; CHECK-NEXT: ret
%r = call reassoc half @llvm.vp.reduce.fadd.v4f16(half %s, <4 x half> %v, <4 x i1> %m, i32 %evl)
ret half %r
}
define half @vpreduce_ord_fadd_v4f16(half %s, <4 x half> %v, <4 x i1> %m, i32 zeroext %evl) {
-; ZVFH-LABEL: vpreduce_ord_fadd_v4f16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; ZVFH-NEXT: vfmv.s.f v9, fa0
-; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFH-NEXT: vfredosum.vs v9, v8, v9, v0.t
-; ZVFH-NEXT: vfmv.f.s fa0, v9
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vpreduce_ord_fadd_v4f16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
-; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFHMIN-NEXT: vfmv.s.f v8, fa5
-; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; ZVFHMIN-NEXT: vfredosum.vs v8, v9, v8, v0.t
-; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
-; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
-; ZVFHMIN-NEXT: ret
+; CHECK-LABEL: vpreduce_ord_fadd_v4f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; CHECK-NEXT: vfmv.s.f v9, fa0
+; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; CHECK-NEXT: vfredosum.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vfmv.f.s fa0, v9
+; CHECK-NEXT: ret
%r = call half @llvm.vp.reduce.fadd.v4f16(half %s, <4 x half> %v, <4 x i1> %m, i32 %evl)
ret half %r
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
index 0f8e74942d58d0..f3ccf74019bb58 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
@@ -1,339 +1,33 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \
-; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \
-; RUN: --check-prefixes=CHECK,ZVFH
-; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \
-; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \
-; RUN: --check-prefixes=CHECK,ZVFH
-; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \
-; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \
-; RUN: --check-prefixes=CHECK,ZVFHMIN
-; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \
-; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \
-; RUN: --check-prefixes=CHECK,ZVFHMIN
-
-declare bfloat @llvm.vp.reduce.fadd.nxv1bf16(bfloat, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i32)
-
-define bfloat @vpreduce_fadd_nxv1bf16(bfloat %s, <vscale x 1 x bfloat> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_fadd_nxv1bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
-; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
-; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; CHECK-NEXT: vfmv.s.f v8, fa5
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vfredusum.vs v8, v9, v8, v0.t
-; CHECK-NEXT: vfmv.f.s fa5, v8
-; CHECK-NEXT: fcvt.bf16.s fa0, fa5
-; CHECK-NEXT: ret
- %r = call reassoc bfloat @llvm.vp.reduce.fadd.nxv1bf16(bfloat %s, <vscale x 1 x bfloat> %v, <vscale x 1 x i1> %m, i32 %evl)
- ret bfloat %r
-}
-
-define bfloat @vpreduce_ord_fadd_nxv1bf16(bfloat %s, <vscale x 1 x bfloat> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_ord_fadd_nxv1bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
-; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
-; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; CHECK-NEXT: vfmv.s.f v8, fa5
-; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vfredosum.vs v8, v9, v8, v0.t
-; CHECK-NEXT: vfmv.f.s fa5, v8
-; CHECK-NEXT: fcvt.bf16.s fa0, fa5
-; CHECK-NEXT: ret
- %r = call bfloat @llvm.vp.reduce.fadd.nxv1bf16(bfloat %s, <vscale x 1 x bfloat> %v, <vscale x 1 x i1> %m, i32 %evl)
- ret bfloat %r
-}
-
-declare bfloat @llvm.vp.reduce.fadd.nxv2bf16(bfloat, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i32)
-
-define bfloat @vpreduce_fadd_nxv2bf16(bfloat %s, <vscale x 2 x bfloat> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_fadd_nxv2bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
-; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
-; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; CHECK-NEXT: vfmv.s.f v8, fa5
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vfredusum.vs v8, v9, v8, v0.t
-; CHECK-NEXT: vfmv.f.s fa5, v8
-; CHECK-NEXT: fcvt.bf16.s fa0, fa5
-; CHECK-NEXT: ret
- %r = call reassoc bfloat @llvm.vp.reduce.fadd.nxv2bf16(bfloat %s, <vscale x 2 x bfloat> %v, <vscale x 2 x i1> %m, i32 %evl)
- ret bfloat %r
-}
-
-define bfloat @vpreduce_ord_fadd_nxv2bf16(bfloat %s, <vscale x 2 x bfloat> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_ord_fadd_nxv2bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
-; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
-; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; CHECK-NEXT: vfmv.s.f v8, fa5
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vfredosum.vs v8, v9, v8, v0.t
-; CHECK-NEXT: vfmv.f.s fa5, v8
-; CHECK-NEXT: fcvt.bf16.s fa0, fa5
-; CHECK-NEXT: ret
- %r = call bfloat @llvm.vp.reduce.fadd.nxv2bf16(bfloat %s, <vscale x 2 x bfloat> %v, <vscale x 2 x i1> %m, i32 %evl)
- ret bfloat %r
-}
-
-declare bfloat @llvm.vp.reduce.fadd.nxv4bf16(bfloat, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i32)
-
-define bfloat @vpreduce_fadd_nxv4bf16(bfloat %s, <vscale x 4 x bfloat> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_fadd_nxv4bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
-; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
-; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, ma
-; CHECK-NEXT: vfmv.s.f v8, fa5
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vfredusum.vs v8, v10, v8, v0.t
-; CHECK-NEXT: vfmv.f.s fa5, v8
-; CHECK-NEXT: fcvt.bf16.s fa0, fa5
-; CHECK-NEXT: ret
- %r = call reassoc bfloat @llvm.vp.reduce.fadd.nxv4bf16(bfloat %s, <vscale x 4 x bfloat> %v, <vscale x 4 x i1> %m, i32 %evl)
- ret bfloat %r
-}
-
-define bfloat @vpreduce_ord_fadd_nxv4bf16(bfloat %s, <vscale x 4 x bfloat> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_ord_fadd_nxv4bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
-; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
-; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, ma
-; CHECK-NEXT: vfmv.s.f v8, fa5
-; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vfredosum.vs v8, v10, v8, v0.t
-; CHECK-NEXT: vfmv.f.s fa5, v8
-; CHECK-NEXT: fcvt.bf16.s fa0, fa5
-; CHECK-NEXT: ret
- %r = call bfloat @llvm.vp.reduce.fadd.nxv4bf16(bfloat %s, <vscale x 4 x bfloat> %v, <vscale x 4 x i1> %m, i32 %evl)
- ret bfloat %r
-}
-
-declare bfloat @llvm.vp.reduce.fadd.nxv64bf16(bfloat, <vscale x 64 x bfloat>, <vscale x 64 x i1>, i32)
-
-define bfloat @vpreduce_fadd_nxv64bf16(bfloat %s, <vscale x 64 x bfloat> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_fadd_nxv64bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: srli a1, a3, 1
-; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v7, v0, a1
-; CHECK-NEXT: slli a5, a3, 2
-; CHECK-NEXT: sub a1, a0, a5
-; CHECK-NEXT: sltu a2, a0, a1
-; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: and a1, a2, a1
-; CHECK-NEXT: slli a4, a3, 1
-; CHECK-NEXT: sub a2, a1, a4
-; CHECK-NEXT: sltu a6, a1, a2
-; CHECK-NEXT: bltu a1, a4, .LBB6_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a1, a4
-; CHECK-NEXT: .LBB6_2:
-; CHECK-NEXT: addi a6, a6, -1
-; CHECK-NEXT: bltu a0, a5, .LBB6_4
-; CHECK-NEXT: # %bb.3:
-; CHECK-NEXT: mv a0, a5
-; CHECK-NEXT: .LBB6_4:
-; CHECK-NEXT: and a2, a6, a2
-; CHECK-NEXT: sub a5, a0, a4
-; CHECK-NEXT: sltu a6, a0, a5
-; CHECK-NEXT: addi a6, a6, -1
-; CHECK-NEXT: and a5, a6, a5
-; CHECK-NEXT: srli a3, a3, 2
-; CHECK-NEXT: vsetvli a6, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v6, v0, a3
-; CHECK-NEXT: bltu a0, a4, .LBB6_6
-; CHECK-NEXT: # %bb.5:
-; CHECK-NEXT: mv a0, a4
-; CHECK-NEXT: .LBB6_6:
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v8
-; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
-; CHECK-NEXT: vsetivli zero, 1, e32, m8, ta, ma
-; CHECK-NEXT: vfmv.s.f v8, fa5
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vfredusum.vs v8, v24, v8, v0.t
-; CHECK-NEXT: vfmv.f.s fa5, v8
-; CHECK-NEXT: fcvt.bf16.s fa5, fa5
-; CHECK-NEXT: fcvt.s.bf16 fa5, fa5
-; CHECK-NEXT: vsetivli zero, 1, e32, m8, ta, ma
-; CHECK-NEXT: vfmv.s.f v8, fa5
-; CHECK-NEXT: vsetvli zero, a5, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12
-; CHECK-NEXT: vmv1r.v v0, v6
-; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfredusum.vs v8, v24, v8, v0.t
-; CHECK-NEXT: vfmv.f.s fa5, v8
-; CHECK-NEXT: fcvt.bf16.s fa5, fa5
-; CHECK-NEXT: fcvt.s.bf16 fa5, fa5
-; CHECK-NEXT: vsetivli zero, 1, e32, m8, ta, ma
-; CHECK-NEXT: vfmv.s.f v8, fa5
-; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v16
-; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfredusum.vs v8, v24, v8, v0.t
-; CHECK-NEXT: vfmv.f.s fa5, v8
-; CHECK-NEXT: fcvt.bf16.s fa5, fa5
-; CHECK-NEXT: fcvt.s.bf16 fa5, fa5
-; CHECK-NEXT: vsetivli zero, 1, e32, m8, ta, ma
-; CHECK-NEXT: vfmv.s.f v8, fa5
-; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v7, a3
-; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v20
-; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfredusum.vs v8, v24, v8, v0.t
-; CHECK-NEXT: vfmv.f.s fa5, v8
-; CHECK-NEXT: fcvt.bf16.s fa0, fa5
-; CHECK-NEXT: ret
- %r = call reassoc bfloat @llvm.vp.reduce.fadd.nxv64bf16(bfloat %s, <vscale x 64 x bfloat> %v, <vscale x 64 x i1> %m, i32 %evl)
- ret bfloat %r
-}
-
-define bfloat @vpreduce_ord_fadd_nxv64bf16(bfloat %s, <vscale x 64 x bfloat> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: vpreduce_ord_fadd_nxv64bf16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: srli a1, a3, 1
-; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v7, v0, a1
-; CHECK-NEXT: slli a5, a3, 2
-; CHECK-NEXT: sub a1, a0, a5
-; CHECK-NEXT: sltu a2, a0, a1
-; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: and a1, a2, a1
-; CHECK-NEXT: slli a4, a3, 1
-; CHECK-NEXT: sub a2, a1, a4
-; CHECK-NEXT: sltu a6, a1, a2
-; CHECK-NEXT: bltu a1, a4, .LBB7_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a1, a4
-; CHECK-NEXT: .LBB7_2:
-; CHECK-NEXT: addi a6, a6, -1
-; CHECK-NEXT: bltu a0, a5, .LBB7_4
-; CHECK-NEXT: # %bb.3:
-; CHECK-NEXT: mv a0, a5
-; CHECK-NEXT: .LBB7_4:
-; CHECK-NEXT: and a2, a6, a2
-; CHECK-NEXT: sub a5, a0, a4
-; CHECK-NEXT: sltu a6, a0, a5
-; CHECK-NEXT: addi a6, a6, -1
-; CHECK-NEXT: and a5, a6, a5
-; CHECK-NEXT: srli a3, a3, 2
-; CHECK-NEXT: vsetvli a6, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v6, v0, a3
-; CHECK-NEXT: bltu a0, a4, .LBB7_6
-; CHECK-NEXT: # %bb.5:
-; CHECK-NEXT: mv a0, a4
-; CHECK-NEXT: .LBB7_6:
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v8
-; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
-; CHECK-NEXT: vsetivli zero, 1, e32, m8, ta, ma
-; CHECK-NEXT: vfmv.s.f v8, fa5
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vfredosum.vs v8, v24, v8, v0.t
-; CHECK-NEXT: vfmv.f.s fa5, v8
-; CHECK-NEXT: fcvt.bf16.s fa5, fa5
-; CHECK-NEXT: fcvt.s.bf16 fa5, fa5
-; CHECK-NEXT: vsetivli zero, 1, e32, m8, ta, ma
-; CHECK-NEXT: vfmv.s.f v8, fa5
-; CHECK-NEXT: vsetvli zero, a5, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12
-; CHECK-NEXT: vmv1r.v v0, v6
-; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfredosum.vs v8, v24, v8, v0.t
-; CHECK-NEXT: vfmv.f.s fa5, v8
-; CHECK-NEXT: fcvt.bf16.s fa5, fa5
-; CHECK-NEXT: fcvt.s.bf16 fa5, fa5
-; CHECK-NEXT: vsetivli zero, 1, e32, m8, ta, ma
-; CHECK-NEXT: vfmv.s.f v8, fa5
-; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v16
-; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfredosum.vs v8, v24, v8, v0.t
-; CHECK-NEXT: vfmv.f.s fa5, v8
-; CHECK-NEXT: fcvt.bf16.s fa5, fa5
-; CHECK-NEXT: fcvt.s.bf16 fa5, fa5
-; CHECK-NEXT: vsetivli zero, 1, e32, m8, ta, ma
-; CHECK-NEXT: vfmv.s.f v8, fa5
-; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v7, a3
-; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v20
-; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfredosum.vs v8, v24, v8, v0.t
-; CHECK-NEXT: vfmv.f.s fa5, v8
-; CHECK-NEXT: fcvt.bf16.s fa0, fa5
-; CHECK-NEXT: ret
- %r = call bfloat @llvm.vp.reduce.fadd.nxv64bf16(bfloat %s, <vscale x 64 x bfloat> %v, <vscale x 64 x i1> %m, i32 %evl)
- ret bfloat %r
-}
+; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \
+; RUN: -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \
+; RUN: -verify-machineinstrs < %s | FileCheck %s
declare half @llvm.vp.reduce.fadd.nxv1f16(half, <vscale x 1 x half>, <vscale x 1 x i1>, i32)
define half @vpreduce_fadd_nxv1f16(half %s, <vscale x 1 x half> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; ZVFH-LABEL: vpreduce_fadd_nxv1f16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; ZVFH-NEXT: vfmv.s.f v9, fa0
-; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFH-NEXT: vfredusum.vs v9, v8, v9, v0.t
-; ZVFH-NEXT: vfmv.f.s fa0, v9
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vpreduce_fadd_nxv1f16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
-; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
-; ZVFHMIN-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; ZVFHMIN-NEXT: vfmv.s.f v8, fa5
-; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; ZVFHMIN-NEXT: vfredusum.vs v8, v9, v8, v0.t
-; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
-; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
-; ZVFHMIN-NEXT: ret
+; CHECK-LABEL: vpreduce_fadd_nxv1f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; CHECK-NEXT: vfmv.s.f v9, fa0
+; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; CHECK-NEXT: vfredusum.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vfmv.f.s fa0, v9
+; CHECK-NEXT: ret
%r = call reassoc half @llvm.vp.reduce.fadd.nxv1f16(half %s, <vscale x 1 x half> %v, <vscale x 1 x i1> %m, i32 %evl)
ret half %r
}
define half @vpreduce_ord_fadd_nxv1f16(half %s, <vscale x 1 x half> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; ZVFH-LABEL: vpreduce_ord_fadd_nxv1f16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; ZVFH-NEXT: vfmv.s.f v9, fa0
-; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFH-NEXT: vfredosum.vs v9, v8, v9, v0.t
-; ZVFH-NEXT: vfmv.f.s fa0, v9
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vpreduce_ord_fadd_nxv1f16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
-; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
-; ZVFHMIN-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
-; ZVFHMIN-NEXT: vfmv.s.f v8, fa5
-; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; ZVFHMIN-NEXT: vfredosum.vs v8, v9, v8, v0.t
-; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
-; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
-; ZVFHMIN-NEXT: ret
+; CHECK-LABEL: vpreduce_ord_fadd_nxv1f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; CHECK-NEXT: vfmv.s.f v9, fa0
+; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; CHECK-NEXT: vfredosum.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vfmv.f.s fa0, v9
+; CHECK-NEXT: ret
%r = call half @llvm.vp.reduce.fadd.nxv1f16(half %s, <vscale x 1 x half> %v, <vscale x 1 x i1> %m, i32 %evl)
ret half %r
}
@@ -341,53 +35,27 @@ define half @vpreduce_ord_fadd_nxv1f16(half %s, <vscale x 1 x half> %v, <vscale
declare half @llvm.vp.reduce.fadd.nxv2f16(half, <vscale x 2 x half>, <vscale x 2 x i1>, i32)
define half @vpreduce_fadd_nxv2f16(half %s, <vscale x 2 x half> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {
-; ZVFH-LABEL: vpreduce_fadd_nxv2f16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; ZVFH-NEXT: vfmv.s.f v9, fa0
-; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFH-NEXT: vfredusum.vs v9, v8, v9, v0.t
-; ZVFH-NEXT: vfmv.f.s fa0, v9
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vpreduce_fadd_nxv2f16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
-; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
-; ZVFHMIN-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; ZVFHMIN-NEXT: vfmv.s.f v8, fa5
-; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; ZVFHMIN-NEXT: vfredusum.vs v8, v9, v8, v0.t
-; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
-; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
-; ZVFHMIN-NEXT: ret
+; CHECK-LABEL: vpreduce_fadd_nxv2f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; CHECK-NEXT: vfmv.s.f v9, fa0
+; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; CHECK-NEXT: vfredusum.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vfmv.f.s fa0, v9
+; CHECK-NEXT: ret
%r = call reassoc half @llvm.vp.reduce.fadd.nxv2f16(half %s, <vscale x 2 x half> %v, <vscale x 2 x i1> %m, i32 %evl)
ret half %r
}
define half @vpreduce_ord_fadd_nxv2f16(half %s, <vscale x 2 x half> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {
-; ZVFH-LABEL: vpreduce_ord_fadd_nxv2f16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; ZVFH-NEXT: vfmv.s.f v9, fa0
-; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFH-NEXT: vfredosum.vs v9, v8, v9, v0.t
-; ZVFH-NEXT: vfmv.f.s fa0, v9
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vpreduce_ord_fadd_nxv2f16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
-; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
-; ZVFHMIN-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; ZVFHMIN-NEXT: vfmv.s.f v8, fa5
-; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; ZVFHMIN-NEXT: vfredosum.vs v8, v9, v8, v0.t
-; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
-; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
-; ZVFHMIN-NEXT: ret
+; CHECK-LABEL: vpreduce_ord_fadd_nxv2f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; CHECK-NEXT: vfmv.s.f v9, fa0
+; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
+; CHECK-NEXT: vfredosum.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vfmv.f.s fa0, v9
+; CHECK-NEXT: ret
%r = call half @llvm.vp.reduce.fadd.nxv2f16(half %s, <vscale x 2 x half> %v, <vscale x 2 x i1> %m, i32 %evl)
ret half %r
}
@@ -395,53 +63,27 @@ define half @vpreduce_ord_fadd_nxv2f16(half %s, <vscale x 2 x half> %v, <vscale
declare half @llvm.vp.reduce.fadd.nxv4f16(half, <vscale x 4 x half>, <vscale x 4 x i1>, i32)
define half @vpreduce_fadd_nxv4f16(half %s, <vscale x 4 x half> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
-; ZVFH-LABEL: vpreduce_fadd_nxv4f16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; ZVFH-NEXT: vfmv.s.f v9, fa0
-; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; ZVFH-NEXT: vfredusum.vs v9, v8, v9, v0.t
-; ZVFH-NEXT: vfmv.f.s fa0, v9
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vpreduce_fadd_nxv4f16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
-; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
-; ZVFHMIN-NEXT: vsetivli zero, 1, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfmv.s.f v8, fa5
-; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfredusum.vs v8, v10, v8, v0.t
-; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
-; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
-; ZVFHMIN-NEXT: ret
+; CHECK-LABEL: vpreduce_fadd_nxv4f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; CHECK-NEXT: vfmv.s.f v9, fa0
+; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; CHECK-NEXT: vfredusum.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vfmv.f.s fa0, v9
+; CHECK-NEXT: ret
%r = call reassoc half @llvm.vp.reduce.fadd.nxv4f16(half %s, <vscale x 4 x half> %v, <vscale x 4 x i1> %m, i32 %evl)
ret half %r
}
define half @vpreduce_ord_fadd_nxv4f16(half %s, <vscale x 4 x half> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {
-; ZVFH-LABEL: vpreduce_ord_fadd_nxv4f16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; ZVFH-NEXT: vfmv.s.f v9, fa0
-; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; ZVFH-NEXT: vfredosum.vs v9, v8, v9, v0.t
-; ZVFH-NEXT: vfmv.f.s fa0, v9
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vpreduce_ord_fadd_nxv4f16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
-; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
-; ZVFHMIN-NEXT: vsetivli zero, 1, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfmv.s.f v8, fa5
-; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfredosum.vs v8, v10, v8, v0.t
-; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
-; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
-; ZVFHMIN-NEXT: ret
+; CHECK-LABEL: vpreduce_ord_fadd_nxv4f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
+; CHECK-NEXT: vfmv.s.f v9, fa0
+; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; CHECK-NEXT: vfredosum.vs v9, v8, v9, v0.t
+; CHECK-NEXT: vfmv.f.s fa0, v9
+; CHECK-NEXT: ret
%r = call half @llvm.vp.reduce.fadd.nxv4f16(half %s, <vscale x 4 x half> %v, <vscale x 4 x i1> %m, i32 %evl)
ret half %r
}
@@ -449,213 +91,59 @@ define half @vpreduce_ord_fadd_nxv4f16(half %s, <vscale x 4 x half> %v, <vscale
declare half @llvm.vp.reduce.fadd.nxv64f16(half, <vscale x 64 x half>, <vscale x 64 x i1>, i32)
define half @vpreduce_fadd_nxv64f16(half %s, <vscale x 64 x half> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {
-; ZVFH-LABEL: vpreduce_fadd_nxv64f16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: csrr a2, vlenb
-; ZVFH-NEXT: srli a1, a2, 1
-; ZVFH-NEXT: vsetvli a3, zero, e8, m1, ta, ma
-; ZVFH-NEXT: vslidedown.vx v24, v0, a1
-; ZVFH-NEXT: slli a2, a2, 2
-; ZVFH-NEXT: sub a1, a0, a2
-; ZVFH-NEXT: sltu a3, a0, a1
-; ZVFH-NEXT: addi a3, a3, -1
-; ZVFH-NEXT: and a1, a3, a1
-; ZVFH-NEXT: bltu a0, a2, .LBB14_2
-; ZVFH-NEXT: # %bb.1:
-; ZVFH-NEXT: mv a0, a2
-; ZVFH-NEXT: .LBB14_2:
-; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; ZVFH-NEXT: vfmv.s.f v25, fa0
-; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFH-NEXT: vfredusum.vs v25, v8, v25, v0.t
-; ZVFH-NEXT: vmv1r.v v0, v24
-; ZVFH-NEXT: vsetvli zero, a1, e16, m8, ta, ma
-; ZVFH-NEXT: vfredusum.vs v25, v16, v25, v0.t
-; ZVFH-NEXT: vfmv.f.s fa0, v25
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vpreduce_fadd_nxv64f16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: srli a1, a3, 1
-; ZVFHMIN-NEXT: vsetvli a2, zero, e8, m1, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v7, v0, a1
-; ZVFHMIN-NEXT: slli a5, a3, 2
-; ZVFHMIN-NEXT: sub a1, a0, a5
-; ZVFHMIN-NEXT: sltu a2, a0, a1
-; ZVFHMIN-NEXT: addi a2, a2, -1
-; ZVFHMIN-NEXT: and a1, a2, a1
-; ZVFHMIN-NEXT: slli a4, a3, 1
-; ZVFHMIN-NEXT: sub a2, a1, a4
-; ZVFHMIN-NEXT: sltu a6, a1, a2
-; ZVFHMIN-NEXT: bltu a1, a4, .LBB14_2
-; ZVFHMIN-NEXT: # %bb.1:
-; ZVFHMIN-NEXT: mv a1, a4
-; ZVFHMIN-NEXT: .LBB14_2:
-; ZVFHMIN-NEXT: addi a6, a6, -1
-; ZVFHMIN-NEXT: bltu a0, a5, .LBB14_4
-; ZVFHMIN-NEXT: # %bb.3:
-; ZVFHMIN-NEXT: mv a0, a5
-; ZVFHMIN-NEXT: .LBB14_4:
-; ZVFHMIN-NEXT: and a2, a6, a2
-; ZVFHMIN-NEXT: sub a5, a0, a4
-; ZVFHMIN-NEXT: sltu a6, a0, a5
-; ZVFHMIN-NEXT: addi a6, a6, -1
-; ZVFHMIN-NEXT: and a5, a6, a5
-; ZVFHMIN-NEXT: srli a3, a3, 2
-; ZVFHMIN-NEXT: vsetvli a6, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v6, v0, a3
-; ZVFHMIN-NEXT: bltu a0, a4, .LBB14_6
-; ZVFHMIN-NEXT: # %bb.5:
-; ZVFHMIN-NEXT: mv a0, a4
-; ZVFHMIN-NEXT: .LBB14_6:
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8
-; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
-; ZVFHMIN-NEXT: vsetivli zero, 1, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmv.s.f v8, fa5
-; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfredusum.vs v8, v24, v8, v0.t
-; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
-; ZVFHMIN-NEXT: fcvt.h.s fa5, fa5
-; ZVFHMIN-NEXT: fcvt.s.h fa5, fa5
-; ZVFHMIN-NEXT: vsetivli zero, 1, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmv.s.f v8, fa5
-; ZVFHMIN-NEXT: vsetvli zero, a5, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12
-; ZVFHMIN-NEXT: vmv1r.v v0, v6
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfredusum.vs v8, v24, v8, v0.t
-; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
-; ZVFHMIN-NEXT: fcvt.h.s fa5, fa5
-; ZVFHMIN-NEXT: fcvt.s.h fa5, fa5
-; ZVFHMIN-NEXT: vsetivli zero, 1, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmv.s.f v8, fa5
-; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfredusum.vs v8, v24, v8, v0.t
-; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
-; ZVFHMIN-NEXT: fcvt.h.s fa5, fa5
-; ZVFHMIN-NEXT: fcvt.s.h fa5, fa5
-; ZVFHMIN-NEXT: vsetivli zero, 1, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmv.s.f v8, fa5
-; ZVFHMIN-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v7, a3
-; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfredusum.vs v8, v24, v8, v0.t
-; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
-; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
-; ZVFHMIN-NEXT: ret
+; CHECK-LABEL: vpreduce_fadd_nxv64f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: srli a1, a2, 1
+; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v24, v0, a1
+; CHECK-NEXT: slli a2, a2, 2
+; CHECK-NEXT: sub a1, a0, a2
+; CHECK-NEXT: sltu a3, a0, a1
+; CHECK-NEXT: addi a3, a3, -1
+; CHECK-NEXT: and a1, a3, a1
+; CHECK-NEXT: bltu a0, a2, .LBB6_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: mv a0, a2
+; CHECK-NEXT: .LBB6_2:
+; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vfmv.s.f v25, fa0
+; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t
+; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
+; CHECK-NEXT: vfredusum.vs v25, v16, v25, v0.t
+; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: ret
%r = call reassoc half @llvm.vp.reduce.fadd.nxv64f16(half %s, <vscale x 64 x half> %v, <vscale x 64 x i1> %m, i32 %evl)
ret half %r
}
define half @vpreduce_ord_fadd_nxv64f16(half %s, <vscale x 64 x half> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {
-; ZVFH-LABEL: vpreduce_ord_fadd_nxv64f16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: csrr a2, vlenb
-; ZVFH-NEXT: srli a1, a2, 1
-; ZVFH-NEXT: vsetvli a3, zero, e8, m1, ta, ma
-; ZVFH-NEXT: vslidedown.vx v24, v0, a1
-; ZVFH-NEXT: slli a2, a2, 2
-; ZVFH-NEXT: sub a1, a0, a2
-; ZVFH-NEXT: sltu a3, a0, a1
-; ZVFH-NEXT: addi a3, a3, -1
-; ZVFH-NEXT: and a1, a3, a1
-; ZVFH-NEXT: bltu a0, a2, .LBB15_2
-; ZVFH-NEXT: # %bb.1:
-; ZVFH-NEXT: mv a0, a2
-; ZVFH-NEXT: .LBB15_2:
-; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; ZVFH-NEXT: vfmv.s.f v25, fa0
-; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFH-NEXT: vfredosum.vs v25, v8, v25, v0.t
-; ZVFH-NEXT: vmv1r.v v0, v24
-; ZVFH-NEXT: vsetvli zero, a1, e16, m8, ta, ma
-; ZVFH-NEXT: vfredosum.vs v25, v16, v25, v0.t
-; ZVFH-NEXT: vfmv.f.s fa0, v25
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vpreduce_ord_fadd_nxv64f16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: srli a1, a3, 1
-; ZVFHMIN-NEXT: vsetvli a2, zero, e8, m1, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v7, v0, a1
-; ZVFHMIN-NEXT: slli a5, a3, 2
-; ZVFHMIN-NEXT: sub a1, a0, a5
-; ZVFHMIN-NEXT: sltu a2, a0, a1
-; ZVFHMIN-NEXT: addi a2, a2, -1
-; ZVFHMIN-NEXT: and a1, a2, a1
-; ZVFHMIN-NEXT: slli a4, a3, 1
-; ZVFHMIN-NEXT: sub a2, a1, a4
-; ZVFHMIN-NEXT: sltu a6, a1, a2
-; ZVFHMIN-NEXT: bltu a1, a4, .LBB15_2
-; ZVFHMIN-NEXT: # %bb.1:
-; ZVFHMIN-NEXT: mv a1, a4
-; ZVFHMIN-NEXT: .LBB15_2:
-; ZVFHMIN-NEXT: addi a6, a6, -1
-; ZVFHMIN-NEXT: bltu a0, a5, .LBB15_4
-; ZVFHMIN-NEXT: # %bb.3:
-; ZVFHMIN-NEXT: mv a0, a5
-; ZVFHMIN-NEXT: .LBB15_4:
-; ZVFHMIN-NEXT: and a2, a6, a2
-; ZVFHMIN-NEXT: sub a5, a0, a4
-; ZVFHMIN-NEXT: sltu a6, a0, a5
-; ZVFHMIN-NEXT: addi a6, a6, -1
-; ZVFHMIN-NEXT: and a5, a6, a5
-; ZVFHMIN-NEXT: srli a3, a3, 2
-; ZVFHMIN-NEXT: vsetvli a6, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v6, v0, a3
-; ZVFHMIN-NEXT: bltu a0, a4, .LBB15_6
-; ZVFHMIN-NEXT: # %bb.5:
-; ZVFHMIN-NEXT: mv a0, a4
-; ZVFHMIN-NEXT: .LBB15_6:
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8
-; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
-; ZVFHMIN-NEXT: vsetivli zero, 1, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmv.s.f v8, fa5
-; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfredosum.vs v8, v24, v8, v0.t
-; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
-; ZVFHMIN-NEXT: fcvt.h.s fa5, fa5
-; ZVFHMIN-NEXT: fcvt.s.h fa5, fa5
-; ZVFHMIN-NEXT: vsetivli zero, 1, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmv.s.f v8, fa5
-; ZVFHMIN-NEXT: vsetvli zero, a5, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12
-; ZVFHMIN-NEXT: vmv1r.v v0, v6
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfredosum.vs v8, v24, v8, v0.t
-; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
-; ZVFHMIN-NEXT: fcvt.h.s fa5, fa5
-; ZVFHMIN-NEXT: fcvt.s.h fa5, fa5
-; ZVFHMIN-NEXT: vsetivli zero, 1, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmv.s.f v8, fa5
-; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfredosum.vs v8, v24, v8, v0.t
-; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
-; ZVFHMIN-NEXT: fcvt.h.s fa5, fa5
-; ZVFHMIN-NEXT: fcvt.s.h fa5, fa5
-; ZVFHMIN-NEXT: vsetivli zero, 1, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmv.s.f v8, fa5
-; ZVFHMIN-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v7, a3
-; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfredosum.vs v8, v24, v8, v0.t
-; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
-; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
-; ZVFHMIN-NEXT: ret
+; CHECK-LABEL: vpreduce_ord_fadd_nxv64f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: srli a1, a2, 1
+; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v24, v0, a1
+; CHECK-NEXT: slli a2, a2, 2
+; CHECK-NEXT: sub a1, a0, a2
+; CHECK-NEXT: sltu a3, a0, a1
+; CHECK-NEXT: addi a3, a3, -1
+; CHECK-NEXT: and a1, a3, a1
+; CHECK-NEXT: bltu a0, a2, .LBB7_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: mv a0, a2
+; CHECK-NEXT: .LBB7_2:
+; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vfmv.s.f v25, fa0
+; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; CHECK-NEXT: vfredosum.vs v25, v8, v25, v0.t
+; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
+; CHECK-NEXT: vfredosum.vs v25, v16, v25, v0.t
+; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: ret
%r = call half @llvm.vp.reduce.fadd.nxv64f16(half %s, <vscale x 64 x half> %v, <vscale x 64 x i1> %m, i32 %evl)
ret half %r
}
@@ -868,12 +356,12 @@ define float @vreduce_fminimum_nxv4f32(float %start, <vscale x 4 x float> %val,
; CHECK-NEXT: feq.s a1, fa0, fa0
; CHECK-NEXT: xori a1, a1, 1
; CHECK-NEXT: or a0, a0, a1
-; CHECK-NEXT: beqz a0, .LBB30_2
+; CHECK-NEXT: beqz a0, .LBB22_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: lui a0, 523264
; CHECK-NEXT: fmv.w.x fa0, a0
; CHECK-NEXT: ret
-; CHECK-NEXT: .LBB30_2:
+; CHECK-NEXT: .LBB22_2:
; CHECK-NEXT: vfmv.f.s fa0, v10
; CHECK-NEXT: ret
%s = call float @llvm.vp.reduce.fminimum.nxv4f32(float %start, <vscale x 4 x float> %val, <vscale x 4 x i1> %m, i32 %evl)
@@ -892,12 +380,12 @@ define float @vreduce_fmaximum_nxv4f32(float %start, <vscale x 4 x float> %val,
; CHECK-NEXT: feq.s a1, fa0, fa0
; CHECK-NEXT: xori a1, a1, 1
; CHECK-NEXT: or a0, a0, a1
-; CHECK-NEXT: beqz a0, .LBB31_2
+; CHECK-NEXT: beqz a0, .LBB23_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: lui a0, 523264
; CHECK-NEXT: fmv.w.x fa0, a0
; CHECK-NEXT: ret
-; CHECK-NEXT: .LBB31_2:
+; CHECK-NEXT: .LBB23_2:
; CHECK-NEXT: vfmv.f.s fa0, v10
; CHECK-NEXT: ret
%s = call float @llvm.vp.reduce.fmaximum.nxv4f32(float %start, <vscale x 4 x float> %val, <vscale x 4 x i1> %m, i32 %evl)
@@ -942,12 +430,12 @@ define float @vreduce_fminimum_v4f32(float %start, <4 x float> %val, <4 x i1> %m
; CHECK-NEXT: feq.s a1, fa0, fa0
; CHECK-NEXT: xori a1, a1, 1
; CHECK-NEXT: or a0, a0, a1
-; CHECK-NEXT: beqz a0, .LBB34_2
+; CHECK-NEXT: beqz a0, .LBB26_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: lui a0, 523264
; CHECK-NEXT: fmv.w.x fa0, a0
; CHECK-NEXT: ret
-; CHECK-NEXT: .LBB34_2:
+; CHECK-NEXT: .LBB26_2:
; CHECK-NEXT: vfmv.f.s fa0, v9
; CHECK-NEXT: ret
%s = call float @llvm.vp.reduce.fminimum.v4f32(float %start, <4 x float> %val, <4 x i1> %m, i32 %evl)
@@ -966,12 +454,12 @@ define float @vreduce_fmaximum_v4f32(float %start, <4 x float> %val, <4 x i1> %m
; CHECK-NEXT: feq.s a1, fa0, fa0
; CHECK-NEXT: xori a1, a1, 1
; CHECK-NEXT: or a0, a0, a1
-; CHECK-NEXT: beqz a0, .LBB35_2
+; CHECK-NEXT: beqz a0, .LBB27_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: lui a0, 523264
; CHECK-NEXT: fmv.w.x fa0, a0
; CHECK-NEXT: ret
-; CHECK-NEXT: .LBB35_2:
+; CHECK-NEXT: .LBB27_2:
; CHECK-NEXT: vfmv.f.s fa0, v9
; CHECK-NEXT: ret
%s = call float @llvm.vp.reduce.fmaximum.v4f32(float %start, <4 x float> %val, <4 x i1> %m, i32 %evl)
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