[llvm] [LLVM][CodeGen] Add lowering for scalable vector bfloat operations. (PR #109803)

[Graham Hunter via llvm-commits]

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@@ -663,6 +663,13 @@ let Predicates = [HasSVEorSME] in {
   defm FABS_ZPmZ : sve_int_un_pred_arit_1_fp<0b100, "fabs", AArch64fabs_mt>;
   defm FNEG_ZPmZ : sve_int_un_pred_arit_1_fp<0b101, "fneg", AArch64fneg_mt>;
 
+  foreach VT = [nxv2bf16, nxv4bf16, nxv8bf16] in {
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huntergr-arm wrote:

nit: May be worth a comment clarifying that you're zeroing or inverting the sign bit.

https://github.com/llvm/llvm-project/pull/109803