[llvm] b9bb77f - [AMDGPU] Update branch-condition-and.ll to auto-generated checks (#110860)

[via llvm-commits]

Author: Juan Manuel Martinez Caamaño
Date: 2024-10-03T17:12:31+02:00
New Revision: b9bb77f0c76be88d824e87c713ae8457046b1ac6

URL: https://github.com/llvm/llvm-project/commit/b9bb77f0c76be88d824e87c713ae8457046b1ac6
DIFF: https://github.com/llvm/llvm-project/commit/b9bb77f0c76be88d824e87c713ae8457046b1ac6.diff

LOG: [AMDGPU] Update branch-condition-and.ll to auto-generated checks (#110860)

Added: 
    

Modified: 
    llvm/test/CodeGen/AMDGPU/branch-condition-and.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/AMDGPU/branch-condition-and.ll b/llvm/test/CodeGen/AMDGPU/branch-condition-and.ll
index cc05129b1b2af6..6efc9f2ae77b82 100644
--- a/llvm/test/CodeGen/AMDGPU/branch-condition-and.ll
+++ b/llvm/test/CodeGen/AMDGPU/branch-condition-and.ll
@@ -1,5 +1,6 @@
-; RUN: llc -mtriple=amdgcn -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=GCN %s
-; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=GCN %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn -mcpu=tahiti -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -mtriple=amdgcn -mcpu=tonga -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=GCN %s
 
 ; This used to crash because during intermediate control flow lowering, there
 ; was a sequence
@@ -9,20 +10,21 @@
 ;       s_mov_b64_term exec, s[2:3]
 ; that was not treated correctly.
 ;
-; GCN-LABEL: {{^}}ham:
-; GCN-DAG: v_cmp_lt_f32_e64 [[OTHERCC:s\[[0-9]+:[0-9]+\]]],
-; GCN-DAG: v_cmp_lt_f32_e32 vcc,
-; GCN: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], vcc, [[OTHERCC]]
-; GCN: s_and_saveexec_b64 [[SAVED:s\[[0-9]+:[0-9]+\]]], [[AND]]
-; GCN-NEXT: s_cbranch_execz .LBB0_{{[0-9]+}}
-
-; GCN-NEXT: ; %bb.{{[0-9]+}}: ; %bb4
-; GCN: ds_write_b32
-
-; GCN: .LBB0_{{[0-9]+}}: ; %UnifiedReturnBlock
-; GCN-NEXT: s_endpgm
-; GCN-NEXT: .Lfunc_end
 define amdgpu_ps void @ham(float %arg, float %arg1) #0 {
+; GCN-LABEL: ham:
+; GCN:       ; %bb.0: ; %bb
+; GCN-NEXT:    v_cmp_lt_f32_e32 vcc, 0, v0
+; GCN-NEXT:    v_cmp_lt_f32_e64 s[0:1], 0, v1
+; GCN-NEXT:    s_and_b64 s[0:1], vcc, s[0:1]
+; GCN-NEXT:    s_and_saveexec_b64 s[2:3], s[0:1]
+; GCN-NEXT:    s_cbranch_execz .LBB0_2
+; GCN-NEXT:  ; %bb.1: ; %bb4
+; GCN-NEXT:    v_mov_b32_e32 v0, 4
+; GCN-NEXT:    s_mov_b32 m0, -1
+; GCN-NEXT:    ds_write_b32 v0, v0
+; GCN-NEXT:    ; divergent unreachable
+; GCN-NEXT:  .LBB0_2: ; %UnifiedReturnBlock
+; GCN-NEXT:    s_endpgm
 bb:
   %tmp = fcmp ogt float %arg, 0.000000e+00
   %tmp2 = fcmp ogt float %arg1, 0.000000e+00