[llvm] a2994de - [RISCV] Fix RISCVBitPositions typo (#110953)

[via llvm-commits]

Author: Piyou Chen
Date: 2024-10-03T14:34:44+08:00
New Revision: a2994ded60c7476e30107a851d61647ccf02d5de

URL: https://github.com/llvm/llvm-project/commit/a2994ded60c7476e30107a851d61647ccf02d5de
DIFF: https://github.com/llvm/llvm-project/commit/a2994ded60c7476e30107a851d61647ccf02d5de.diff

LOG: [RISCV] Fix RISCVBitPositions typo (#110953)

This patch updates  `{"zve64x", 0, 63},` into `{"zve64f", 0, 63},`.

Base on
https://github.com/riscv-non-isa/riscv-c-api-doc/blob/main/src/c-api.adoc#extension-bitmask-definitions

Added: 
    

Modified: 
    llvm/lib/TargetParser/RISCVISAInfo.cpp

Removed: 
    


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diff  --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp b/llvm/lib/TargetParser/RISCVISAInfo.cpp
index 7fa3d8edec84d5..caa5a97747ee57 100644
--- a/llvm/lib/TargetParser/RISCVISAInfo.cpp
+++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp
@@ -1049,7 +1049,7 @@ constexpr static RISCVExtBit RISCVBitPositions[] = {
     {"zvksed", 0, 57},    {"zvksh", 0, 58},
     {"zvkt", 0, 59},      {"zve32x", 0, 60},
     {"zve32f", 0, 61},    {"zve64x", 0, 62},
-    {"zve64x", 0, 63},    {"zve64d", 1, 0},
+    {"zve64f", 0, 63},    {"zve64d", 1, 0},
     {"zimop", 1, 1},      {"zca", 1, 2},
     {"zcb", 1, 3},        {"zcd", 1, 4},
     {"zcf", 1, 5},        {"zcmop", 1, 6},