[llvm] [RISCV] Fix RISCVBitPositions typo (PR #110953)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Piyou Chen (BeMg)

<details>
<summary>Changes</summary>

This patch updates  `{"zve64x", 0, 63},` into `{"zve64f", 0, 63},`.

Base on https://github.com/riscv-non-isa/riscv-c-api-doc/blob/main/src/c-api.adoc#extension-bitmask-definitions

---
Full diff: https://github.com/llvm/llvm-project/pull/110953.diff


1 Files Affected:

- (modified) llvm/lib/TargetParser/RISCVISAInfo.cpp (+1-1) 


``````````diff
diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp b/llvm/lib/TargetParser/RISCVISAInfo.cpp
index 7fa3d8edec84d5..caa5a97747ee57 100644
--- a/llvm/lib/TargetParser/RISCVISAInfo.cpp
+++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp
@@ -1049,7 +1049,7 @@ constexpr static RISCVExtBit RISCVBitPositions[] = {
     {"zvksed", 0, 57},    {"zvksh", 0, 58},
     {"zvkt", 0, 59},      {"zve32x", 0, 60},
     {"zve32f", 0, 61},    {"zve64x", 0, 62},
-    {"zve64x", 0, 63},    {"zve64d", 1, 0},
+    {"zve64f", 0, 63},    {"zve64d", 1, 0},
     {"zimop", 1, 1},      {"zca", 1, 2},
     {"zcb", 1, 3},        {"zcd", 1, 4},
     {"zcf", 1, 5},        {"zcmop", 1, 6},

``````````

</details>


https://github.com/llvm/llvm-project/pull/110953