[llvm] [SPIRV] Add radians intrinsic (PR #110800)
Adam Yang via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 2 16:41:24 PDT 2024
https://github.com/adam-yang updated https://github.com/llvm/llvm-project/pull/110800
>From 010cf3742626d8a5f6daa534304525769a91aebe Mon Sep 17 00:00:00 2001
From: Adam Yang <hanbyang at microsoft.com>
Date: Wed, 2 Oct 2024 00:11:14 -0700
Subject: [PATCH 1/3] Added radians selection for spirv
---
llvm/include/llvm/IR/IntrinsicsSPIRV.td | 1 +
.../Target/SPIRV/SPIRVInstructionSelector.cpp | 48 +++++++++++++++++++
.../CodeGen/SPIRV/hlsl-intrinsics/radians.ll | 48 +++++++++++++++++++
3 files changed, 97 insertions(+)
create mode 100644 llvm/test/CodeGen/SPIRV/hlsl-intrinsics/radians.ll
diff --git a/llvm/include/llvm/IR/IntrinsicsSPIRV.td b/llvm/include/llvm/IR/IntrinsicsSPIRV.td
index efe19f5a8370e5..fadc3727c099a1 100644
--- a/llvm/include/llvm/IR/IntrinsicsSPIRV.td
+++ b/llvm/include/llvm/IR/IntrinsicsSPIRV.td
@@ -83,4 +83,5 @@ let TargetPrefix = "spv" in {
[IntrNoMem, Commutative] >;
def int_spv_wave_is_first_lane : DefaultAttrsIntrinsic<[llvm_i1_ty], [], [IntrConvergent]>;
def int_spv_sign : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i32_ty>], [llvm_any_ty], [IntrNoMem]>;
+ def int_spv_radians : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [llvm_anyfloat_ty]>;
}
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index c1a0cd9837d146..30ff29da66e3d2 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -229,6 +229,9 @@ class SPIRVInstructionSelector : public InstructionSelector {
bool selectSpvThreadId(Register ResVReg, const SPIRVType *ResType,
MachineInstr &I) const;
+ bool selectRadians(Register ResVReg, const SPIRVType *ResType,
+ MachineInstr &I) const;
+
bool selectUnmergeValues(MachineInstr &I) const;
// Utilities
@@ -1751,6 +1754,45 @@ bool SPIRVInstructionSelector::selectSign(Register ResVReg,
return Result;
}
+<<<<<<< HEAD
+=======
+bool SPIRVInstructionSelector::selectStep(Register ResVReg,
+ const SPIRVType *ResType,
+ MachineInstr &I) const {
+
+ assert(I.getNumOperands() == 4);
+ assert(I.getOperand(2).isReg());
+ assert(I.getOperand(3).isReg());
+ MachineBasicBlock &BB = *I.getParent();
+
+ return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst))
+ .addDef(ResVReg)
+ .addUse(GR.getSPIRVTypeID(ResType))
+ .addImm(static_cast<uint32_t>(SPIRV::InstructionSet::GLSL_std_450))
+ .addImm(GL::Step)
+ .addUse(I.getOperand(2).getReg())
+ .addUse(I.getOperand(3).getReg())
+ .constrainAllUses(TII, TRI, RBI);
+}
+
+bool SPIRVInstructionSelector::selectRadians(Register ResVReg,
+ const SPIRVType *ResType,
+ MachineInstr &I) const {
+
+ assert(I.getNumOperands() == 3);
+ assert(I.getOperand(2).isReg());
+ MachineBasicBlock &BB = *I.getParent();
+
+ return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst))
+ .addDef(ResVReg)
+ .addUse(GR.getSPIRVTypeID(ResType))
+ .addImm(static_cast<uint32_t>(SPIRV::InstructionSet::GLSL_std_450))
+ .addImm(GL::Radians)
+ .addUse(I.getOperand(2).getReg())
+ .constrainAllUses(TII, TRI, RBI);
+}
+
+>>>>>>> c520937ac3f9 (Added radians selection for spirv)
bool SPIRVInstructionSelector::selectBitreverse(Register ResVReg,
const SPIRVType *ResType,
MachineInstr &I) const {
@@ -2533,6 +2575,7 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
.addUse(GR.getOrCreateConstInt(3, I, IntTy, TII));
}
case Intrinsic::spv_step:
+<<<<<<< HEAD
return selectExtInst(ResVReg, ResType, I, CL::step, GL::Step);
// Discard intrinsics which we do not expect to actually represent code after
// lowering or intrinsics which are not implemented but should not crash when
@@ -2542,6 +2585,11 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
case Intrinsic::instrprof_value_profile:
break;
// Discard internal intrinsics.
+=======
+ return selectStep(ResVReg, ResType, I);
+ case Intrinsic::spv_radians:
+ return selectRadians(ResVReg, ResType, I);
+>>>>>>> c520937ac3f9 (Added radians selection for spirv)
case Intrinsic::spv_value_md:
break;
default: {
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/radians.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/radians.ll
new file mode 100644
index 00000000000000..1fe8ab30ed9538
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/radians.ll
@@ -0,0 +1,48 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+
+; CHECK-DAG: %[[#op_ext_glsl:]] = OpExtInstImport "GLSL.std.450"
+
+; CHECK-DAG: %[[#float_32:]] = OpTypeFloat 32
+; CHECK-DAG: %[[#float_16:]] = OpTypeFloat 16
+
+; CHECK-DAG: %[[#vec4_float_32:]] = OpTypeVector %[[#float_32]] 4
+; CHECK-DAG: %[[#vec4_float_16:]] = OpTypeVector %[[#float_16]] 4
+
+declare half @llvm.spv.radians.f16(half)
+declare float @llvm.spv.radians.f32(float)
+
+declare <4 x float> @llvm.spv.radians.v4f32(<4 x float>)
+declare <4 x half> @llvm.spv.radians.v4f16(<4 x half>)
+
+define noundef float @radians_float(float noundef %a) {
+entry:
+; CHECK: %[[#float_32_arg:]] = OpFunctionParameter %[[#float_32]]
+; CHECK: %[[#]] = OpExtInst %[[#float_32]] %[[#op_ext_glsl]] Radians %[[#float_32_arg]]
+ %elt.radians = call float @llvm.spv.radians.f32(float %a)
+ ret float %elt.radians
+}
+
+define noundef half @radians_half(half noundef %a) {
+entry:
+; CHECK: %[[#float_16_arg:]] = OpFunctionParameter %[[#float_16]]
+; CHECK: %[[#]] = OpExtInst %[[#float_16]] %[[#op_ext_glsl]] Radians %[[#float_16_arg]]
+ %elt.radians = call half @llvm.spv.radians.f16(half %a)
+ ret half %elt.radians
+}
+
+define noundef <4 x float> @radians_float_vector(<4 x float> noundef %a) {
+entry:
+; CHECK: %[[#vec4_float_32_arg:]] = OpFunctionParameter %[[#vec4_float_32]]
+; CHECK: %[[#]] = OpExtInst %[[#vec4_float_32]] %[[#op_ext_glsl]] Radians %[[#vec4_float_32_arg]]
+ %elt.radians = call <4 x float> @llvm.spv.radians.v4f32(<4 x float> %a)
+ ret <4 x float> %elt.radians
+}
+
+define noundef <4 x half> @radians_half_vector(<4 x half> noundef %a) {
+entry:
+; CHECK: %[[#vec4_float_16_arg:]] = OpFunctionParameter %[[#vec4_float_16]]
+; CHECK: %[[#]] = OpExtInst %[[#vec4_float_16]] %[[#op_ext_glsl]] Radians %[[#vec4_float_16_arg]]
+ %elt.radians = call <4 x half> @llvm.spv.radians.v4f16(<4 x half> %a)
+ ret <4 x half> %elt.radians
+}
>From ea6331e9f25bccfcb63c56aa135502f38c655ea7 Mon Sep 17 00:00:00 2001
From: Adam Yang <hanbyang at microsoft.com>
Date: Wed, 2 Oct 2024 01:22:27 -0700
Subject: [PATCH 2/3] Added nomem attribute
---
llvm/include/llvm/IR/IntrinsicsSPIRV.td | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/include/llvm/IR/IntrinsicsSPIRV.td b/llvm/include/llvm/IR/IntrinsicsSPIRV.td
index fadc3727c099a1..d1d74e8ccba6b1 100644
--- a/llvm/include/llvm/IR/IntrinsicsSPIRV.td
+++ b/llvm/include/llvm/IR/IntrinsicsSPIRV.td
@@ -83,5 +83,5 @@ let TargetPrefix = "spv" in {
[IntrNoMem, Commutative] >;
def int_spv_wave_is_first_lane : DefaultAttrsIntrinsic<[llvm_i1_ty], [], [IntrConvergent]>;
def int_spv_sign : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i32_ty>], [llvm_any_ty], [IntrNoMem]>;
- def int_spv_radians : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [llvm_anyfloat_ty]>;
+ def int_spv_radians : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [llvm_anyfloat_ty], [IntrNoMem]>;
}
>From 735e8be18119af94cc9d3b307883c1edbdcf3737 Mon Sep 17 00:00:00 2001
From: Adam Yang <hanbyang at microsoft.com>
Date: Wed, 2 Oct 2024 16:41:12 -0700
Subject: [PATCH 3/3] Fixed bad rebase. Removed selectRadians and using
selectExtInst instead
---
.../Target/SPIRV/SPIRVInstructionSelector.cpp | 50 +------------------
1 file changed, 2 insertions(+), 48 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index 30ff29da66e3d2..8f1ce93942b71e 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -229,9 +229,6 @@ class SPIRVInstructionSelector : public InstructionSelector {
bool selectSpvThreadId(Register ResVReg, const SPIRVType *ResType,
MachineInstr &I) const;
- bool selectRadians(Register ResVReg, const SPIRVType *ResType,
- MachineInstr &I) const;
-
bool selectUnmergeValues(MachineInstr &I) const;
// Utilities
@@ -1754,45 +1751,6 @@ bool SPIRVInstructionSelector::selectSign(Register ResVReg,
return Result;
}
-<<<<<<< HEAD
-=======
-bool SPIRVInstructionSelector::selectStep(Register ResVReg,
- const SPIRVType *ResType,
- MachineInstr &I) const {
-
- assert(I.getNumOperands() == 4);
- assert(I.getOperand(2).isReg());
- assert(I.getOperand(3).isReg());
- MachineBasicBlock &BB = *I.getParent();
-
- return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst))
- .addDef(ResVReg)
- .addUse(GR.getSPIRVTypeID(ResType))
- .addImm(static_cast<uint32_t>(SPIRV::InstructionSet::GLSL_std_450))
- .addImm(GL::Step)
- .addUse(I.getOperand(2).getReg())
- .addUse(I.getOperand(3).getReg())
- .constrainAllUses(TII, TRI, RBI);
-}
-
-bool SPIRVInstructionSelector::selectRadians(Register ResVReg,
- const SPIRVType *ResType,
- MachineInstr &I) const {
-
- assert(I.getNumOperands() == 3);
- assert(I.getOperand(2).isReg());
- MachineBasicBlock &BB = *I.getParent();
-
- return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst))
- .addDef(ResVReg)
- .addUse(GR.getSPIRVTypeID(ResType))
- .addImm(static_cast<uint32_t>(SPIRV::InstructionSet::GLSL_std_450))
- .addImm(GL::Radians)
- .addUse(I.getOperand(2).getReg())
- .constrainAllUses(TII, TRI, RBI);
-}
-
->>>>>>> c520937ac3f9 (Added radians selection for spirv)
bool SPIRVInstructionSelector::selectBitreverse(Register ResVReg,
const SPIRVType *ResType,
MachineInstr &I) const {
@@ -2575,8 +2533,9 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
.addUse(GR.getOrCreateConstInt(3, I, IntTy, TII));
}
case Intrinsic::spv_step:
-<<<<<<< HEAD
return selectExtInst(ResVReg, ResType, I, CL::step, GL::Step);
+ case Intrinsic::spv_radians:
+ return selectExtInst(ResVReg, ResType, I, CL::radians, GL::Radians);
// Discard intrinsics which we do not expect to actually represent code after
// lowering or intrinsics which are not implemented but should not crash when
// found in a customer's LLVM IR input.
@@ -2585,11 +2544,6 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
case Intrinsic::instrprof_value_profile:
break;
// Discard internal intrinsics.
-=======
- return selectStep(ResVReg, ResType, I);
- case Intrinsic::spv_radians:
- return selectRadians(ResVReg, ResType, I);
->>>>>>> c520937ac3f9 (Added radians selection for spirv)
case Intrinsic::spv_value_md:
break;
default: {
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