[llvm] [llvm] Mark win x64 SEH pseudo instruction as meta instructions (PR #110889)
Daniel Paoliello via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 2 10:06:22 PDT 2024
https://github.com/dpaoliello created https://github.com/llvm/llvm-project/pull/110889
When adding new SEH pseudo instructions in #110024 I noticed that some of the tests were changing their output since these new instructions were counting towards thresholds for branching versus folding decisions.
These instructions do not result in real machine instructions being emitted, so they should be marked as meta instructions.
>From 5f278f658062cc2e210e96fc940a55b042964872 Mon Sep 17 00:00:00 2001
From: Daniel Paoliello <danpao at microsoft.com>
Date: Wed, 2 Oct 2024 10:03:27 -0700
Subject: [PATCH] [llvm] Mark win x64 SEH psuedoinstruction as meta
instructions
---
llvm/lib/Target/X86/X86InstrCompiler.td | 2 +-
.../CodeGen/X86/x86-win64-shrink-wrapping.ll | 24 +++++++++----------
2 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/llvm/lib/Target/X86/X86InstrCompiler.td b/llvm/lib/Target/X86/X86InstrCompiler.td
index 5a8177e2b3607b..0d9ce696bad467 100644
--- a/llvm/lib/Target/X86/X86InstrCompiler.td
+++ b/llvm/lib/Target/X86/X86InstrCompiler.td
@@ -235,7 +235,7 @@ let isBranch = 1, isTerminator = 1, isCodeGenOnly = 1 in {
//===----------------------------------------------------------------------===//
// Pseudo instructions used by unwind info.
//
-let isPseudo = 1, SchedRW = [WriteSystem] in {
+let isPseudo = 1, isMeta = 1, SchedRW = [WriteSystem] in {
def SEH_PushReg : I<0, Pseudo, (outs), (ins i32imm:$reg),
"#SEH_PushReg $reg", []>;
def SEH_SaveReg : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst),
diff --git a/llvm/test/CodeGen/X86/x86-win64-shrink-wrapping.ll b/llvm/test/CodeGen/X86/x86-win64-shrink-wrapping.ll
index 6ed23b0d770cd4..3c06bd29b88739 100644
--- a/llvm/test/CodeGen/X86/x86-win64-shrink-wrapping.ll
+++ b/llvm/test/CodeGen/X86/x86-win64-shrink-wrapping.ll
@@ -17,7 +17,7 @@ define i32 @loopInfoSaveOutsideLoop(i32 %cond, i32 %N) #0 {
; ENABLE-NEXT: .seh_pushreg %rbx
; ENABLE-NEXT: .seh_endprologue
; ENABLE-NEXT: testl %ecx, %ecx
-; ENABLE-NEXT: je .LBB0_4
+; ENABLE-NEXT: je .LBB0_5
; ENABLE-NEXT: # %bb.1: # %for.preheader
; ENABLE-NEXT: #APP
; ENABLE-NEXT: nop
@@ -38,11 +38,11 @@ define i32 @loopInfoSaveOutsideLoop(i32 %cond, i32 %N) #0 {
; ENABLE-NEXT: nop
; ENABLE-NEXT: #NO_APP
; ENABLE-NEXT: shll $3, %eax
-; ENABLE-NEXT: jmp .LBB0_5
-; ENABLE-NEXT: .LBB0_4: # %if.else
+; ENABLE-NEXT: popq %rbx
+; ENABLE-NEXT: retq
+; ENABLE-NEXT: .LBB0_5: # %if.else
; ENABLE-NEXT: movl %edx, %eax
; ENABLE-NEXT: addl %edx, %eax
-; ENABLE-NEXT: .LBB0_5: # %if.end
; ENABLE-NEXT: popq %rbx
; ENABLE-NEXT: retq
; ENABLE-NEXT: .seh_endproc
@@ -53,7 +53,7 @@ define i32 @loopInfoSaveOutsideLoop(i32 %cond, i32 %N) #0 {
; DISABLE-NEXT: .seh_pushreg %rbx
; DISABLE-NEXT: .seh_endprologue
; DISABLE-NEXT: testl %ecx, %ecx
-; DISABLE-NEXT: je .LBB0_4
+; DISABLE-NEXT: je .LBB0_5
; DISABLE-NEXT: # %bb.1: # %for.preheader
; DISABLE-NEXT: #APP
; DISABLE-NEXT: nop
@@ -74,11 +74,11 @@ define i32 @loopInfoSaveOutsideLoop(i32 %cond, i32 %N) #0 {
; DISABLE-NEXT: nop
; DISABLE-NEXT: #NO_APP
; DISABLE-NEXT: shll $3, %eax
-; DISABLE-NEXT: jmp .LBB0_5
-; DISABLE-NEXT: .LBB0_4: # %if.else
+; DISABLE-NEXT: popq %rbx
+; DISABLE-NEXT: retq
+; DISABLE-NEXT: .LBB0_5: # %if.else
; DISABLE-NEXT: movl %edx, %eax
; DISABLE-NEXT: addl %edx, %eax
-; DISABLE-NEXT: .LBB0_5: # %if.end
; DISABLE-NEXT: popq %rbx
; DISABLE-NEXT: retq
; DISABLE-NEXT: .seh_endproc
@@ -157,7 +157,7 @@ define i32 @loopInfoSaveOutsideLoop2(i32 %cond, i32 %N) #0 {
; DISABLE-NEXT: .seh_pushreg %rbx
; DISABLE-NEXT: .seh_endprologue
; DISABLE-NEXT: testl %ecx, %ecx
-; DISABLE-NEXT: je .LBB1_4
+; DISABLE-NEXT: je .LBB1_5
; DISABLE-NEXT: # %bb.1: # %for.preheader
; DISABLE-NEXT: #APP
; DISABLE-NEXT: nop
@@ -178,11 +178,11 @@ define i32 @loopInfoSaveOutsideLoop2(i32 %cond, i32 %N) #0 {
; DISABLE-NEXT: nop
; DISABLE-NEXT: #NO_APP
; DISABLE-NEXT: shll $3, %eax
-; DISABLE-NEXT: jmp .LBB1_5
-; DISABLE-NEXT: .LBB1_4: # %if.else
+; DISABLE-NEXT: popq %rbx
+; DISABLE-NEXT: retq
+; DISABLE-NEXT: .LBB1_5: # %if.else
; DISABLE-NEXT: addl %edx, %edx
; DISABLE-NEXT: movl %edx, %eax
-; DISABLE-NEXT: .LBB1_5: # %if.end
; DISABLE-NEXT: popq %rbx
; DISABLE-NEXT: retq
; DISABLE-NEXT: .seh_endproc
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