[llvm] [AMDGPU] Use the SchedModel available in SIInstrInfo (PR #110859)

[Juan Manuel Martinez Caamaño via llvm-commits]

https://github.com/jmmartinez created https://github.com/llvm/llvm-project/pull/110859

Instead of allocating an initializing a new instance in `GCNHazardRecognizer` and `AMDGPUInsertDelayAlu`.

>From 722952751ebc11028e204ecbc1c46d352ff1a56f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Juan=20Manuel=20Martinez=20Caama=C3=B1o?= <juamarti at amd.com>
Date: Wed, 2 Oct 2024 16:50:50 +0200
Subject: [PATCH] [AMDGPU] Use the SchedModel available in SIInstrInfo

Instead of allocating an initializing a new instance in
GCNHazardRecognizer and AMDGPUInsertDelayAlu.
---
 llvm/lib/Target/AMDGPU/AMDGPUInsertDelayAlu.cpp | 7 +++----
 llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp  | 4 ++--
 llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h    | 2 +-
 3 files changed, 6 insertions(+), 7 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInsertDelayAlu.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInsertDelayAlu.cpp
index 7619a39bac9c14..3f2bb5df8836bb 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInsertDelayAlu.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInsertDelayAlu.cpp
@@ -30,7 +30,7 @@ class AMDGPUInsertDelayAlu : public MachineFunctionPass {
   const SIInstrInfo *SII;
   const TargetRegisterInfo *TRI;
 
-  TargetSchedModel SchedModel;
+  const TargetSchedModel *SchedModel;
 
   AMDGPUInsertDelayAlu() : MachineFunctionPass(ID) {}
 
@@ -387,7 +387,7 @@ class AMDGPUInsertDelayAlu : public MachineFunctionPass {
       if (Type != OTHER) {
         // TODO: Scan implicit defs too?
         for (const auto &Op : MI.defs()) {
-          unsigned Latency = SchedModel.computeOperandLatency(
+          unsigned Latency = SchedModel->computeOperandLatency(
               &MI, Op.getOperandNo(), nullptr, 0);
           for (MCRegUnit Unit : TRI->regunits(Op.getReg()))
             State[Unit] = DelayInfo(Type, Latency);
@@ -429,8 +429,7 @@ class AMDGPUInsertDelayAlu : public MachineFunctionPass {
 
     SII = ST.getInstrInfo();
     TRI = ST.getRegisterInfo();
-
-    SchedModel.init(&ST);
+    SchedModel = &SII->getSchedModel();
 
     // Calculate the delay state for each basic block, iterating until we reach
     // a fixed point.
diff --git a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
index cc39fd1740683f..44afccb0690d0d 100644
--- a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
@@ -59,10 +59,10 @@ static bool shouldRunLdsBranchVmemWARHazardFixup(const MachineFunction &MF,
 GCNHazardRecognizer::GCNHazardRecognizer(const MachineFunction &MF)
     : IsHazardRecognizerMode(false), CurrCycleInstr(nullptr), MF(MF),
       ST(MF.getSubtarget<GCNSubtarget>()), TII(*ST.getInstrInfo()),
-      TRI(TII.getRegisterInfo()), UseVALUReadHazardExhaustiveSearch(false),
+      TRI(TII.getRegisterInfo()), TSchedModel(TII.getSchedModel()),
+      UseVALUReadHazardExhaustiveSearch(false),
       ClauseUses(TRI.getNumRegUnits()), ClauseDefs(TRI.getNumRegUnits()) {
   MaxLookAhead = MF.getRegInfo().isPhysRegUsed(AMDGPU::AGPR0) ? 19 : 5;
-  TSchedModel.init(&ST);
   RunLdsBranchVmemWARHazardFixup = shouldRunLdsBranchVmemWARHazardFixup(MF, ST);
 }
 
diff --git a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
index e840e2445188fb..adb2278c48eebe 100644
--- a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
+++ b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
@@ -46,7 +46,7 @@ class GCNHazardRecognizer final : public ScheduleHazardRecognizer {
   const GCNSubtarget &ST;
   const SIInstrInfo &TII;
   const SIRegisterInfo &TRI;
-  TargetSchedModel TSchedModel;
+  const TargetSchedModel &TSchedModel;
   bool RunLdsBranchVmemWARHazardFixup;
   BitVector VALUReadHazardSGPRs;
   bool UseVALUReadHazardExhaustiveSearch;