[llvm] 6d6eea9 - [LV] Use SCEV to simplify wide binop operand to constant.
Florian Hahn via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 2 05:47:02 PDT 2024
Author: Florian Hahn
Date: 2024-10-02T13:45:49+01:00
New Revision: 6d6eea92e36c301e34a7ec11b2a40e3080f79f53
URL: https://github.com/llvm/llvm-project/commit/6d6eea92e36c301e34a7ec11b2a40e3080f79f53
DIFF: https://github.com/llvm/llvm-project/commit/6d6eea92e36c301e34a7ec11b2a40e3080f79f53.diff
LOG: [LV] Use SCEV to simplify wide binop operand to constant.
The legacy cost model uses SCEV to determine if the second operand of a
binary op is a constant. Update the VPlan construction logic to mirror
the current legacy behavior, to fix a difference in the cost models.
Fixes https://github.com/llvm/llvm-project/issues/109528.
Fixes https://github.com/llvm/llvm-project/issues/110440.
Added:
Modified:
llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
llvm/test/Transforms/LoopVectorize/X86/cost-constant-known-via-scev.ll
Removed:
################################################################################
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
index e1f9f29ac6d92f..de3b981a4fe390 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -8420,21 +8420,28 @@ VPWidenRecipe *VPRecipeBuilder::tryToWiden(Instruction *I,
case Instruction::Sub:
case Instruction::Xor:
case Instruction::Freeze:
- if (I->getOpcode() == Instruction::Mul) {
- // Simplify operands of multiplications using SCEV. This is needed at the
- // moment to match the behavior of the legacy cost-model.
- // TODO: Generalize to any opcode and move to VPlan transformation.
- SmallVector<VPValue *> NewOps(Operands);
+ SmallVector<VPValue *> NewOps(Operands);
+ if (Instruction::isBinaryOp(I->getOpcode())) {
+ // The legacy cost model uses SCEV to check if some of the operands are
+ // constants. To match the legacy cost model's behavior, use SCEV to try
+ // to replace operands with constants.
ScalarEvolution &SE = *PSE.getSE();
- for (unsigned I = 0; I < Operands.size(); ++I) {
- Value *V = NewOps[I]->getUnderlyingValue();
- if (!isa<Constant>(V) && SE.isSCEVable(V->getType()))
- if (auto *C = dyn_cast<SCEVConstant>(PSE.getSE()->getSCEV(V)))
- NewOps[I] = Plan.getOrAddLiveIn(C->getValue());
- }
- return new VPWidenRecipe(*I, make_range(NewOps.begin(), NewOps.end()));
+ auto GetConstantViaSCEV = [this, &SE](VPValue *Op) {
+ Value *V = Op->getUnderlyingValue();
+ if (isa<Constant>(V) || !SE.isSCEVable(V->getType()))
+ return Op;
+ auto *C = dyn_cast<SCEVConstant>(SE.getSCEV(V));
+ if (!C)
+ return Op;
+ return Plan.getOrAddLiveIn(C->getValue());
+ };
+ // For Mul, the legacy cost model checks both operands.
+ if (I->getOpcode() == Instruction::Mul)
+ NewOps[0] = GetConstantViaSCEV(NewOps[0]);
+ // For other binops, the legacy cost model only checks the second operand.
+ NewOps[1] = GetConstantViaSCEV(NewOps[1]);
}
- return new VPWidenRecipe(*I, make_range(Operands.begin(), Operands.end()));
+ return new VPWidenRecipe(*I, make_range(NewOps.begin(), NewOps.end()));
};
}
diff --git a/llvm/test/Transforms/LoopVectorize/X86/cost-constant-known-via-scev.ll b/llvm/test/Transforms/LoopVectorize/X86/cost-constant-known-via-scev.ll
index 4c10ac3cd519e9..6060a7318deb64 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/cost-constant-known-via-scev.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/cost-constant-known-via-scev.ll
@@ -58,9 +58,93 @@ exit:
%ret = phi i64 [ %mul, %loop ]
ret i64 %ret
}
+
+; Test case for https://github.com/llvm/llvm-project/issues/109528.
+define i64 @second_lshr_operand_zero_via_scev() {
+; CHECK-LABEL: define i64 @second_lshr_operand_zero_via_scev() {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: [[EXT_0:%.*]] = sext i8 0 to i32
+; CHECK-NEXT: br i1 true, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_IND:%.*]] = phi <2 x i64> [ <i64 0, i64 1>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <2 x i64> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP10:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <2 x i64> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP11:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_IND2:%.*]] = phi <2 x i32> [ <i32 0, i32 1>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT3:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[STEP_ADD:%.*]] = add <2 x i64> [[VEC_IND]], <i64 2, i64 2>
+; CHECK-NEXT: [[STEP_ADD4:%.*]] = add <2 x i32> [[VEC_IND2]], <i32 2, i32 2>
+; CHECK-NEXT: [[TMP0:%.*]] = icmp eq <2 x i64> [[VEC_IND]], zeroinitializer
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i64> [[STEP_ADD]], zeroinitializer
+; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i64> [[VEC_IND]], zeroinitializer
+; CHECK-NEXT: [[TMP3:%.*]] = and <2 x i64> [[STEP_ADD]], zeroinitializer
+; CHECK-NEXT: [[TMP4:%.*]] = lshr <2 x i32> [[VEC_IND2]], zeroinitializer
+; CHECK-NEXT: [[TMP5:%.*]] = lshr <2 x i32> [[STEP_ADD4]], zeroinitializer
+; CHECK-NEXT: [[TMP6:%.*]] = zext <2 x i32> [[TMP4]] to <2 x i64>
+; CHECK-NEXT: [[TMP7:%.*]] = zext <2 x i32> [[TMP5]] to <2 x i64>
+; CHECK-NEXT: [[TMP8:%.*]] = select <2 x i1> [[TMP0]], <2 x i64> [[TMP2]], <2 x i64> [[TMP6]]
+; CHECK-NEXT: [[TMP9:%.*]] = select <2 x i1> [[TMP1]], <2 x i64> [[TMP3]], <2 x i64> [[TMP7]]
+; CHECK-NEXT: [[TMP10]] = or <2 x i64> [[TMP8]], [[VEC_PHI]]
+; CHECK-NEXT: [[TMP11]] = or <2 x i64> [[TMP9]], [[VEC_PHI1]]
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
+; CHECK-NEXT: [[VEC_IND_NEXT]] = add <2 x i64> [[STEP_ADD]], <i64 2, i64 2>
+; CHECK-NEXT: [[VEC_IND_NEXT3]] = add <2 x i32> [[STEP_ADD4]], <i32 2, i32 2>
+; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], 0
+; CHECK-NEXT: br i1 [[TMP12]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: [[BIN_RDX:%.*]] = or <2 x i64> [[TMP11]], [[TMP10]]
+; CHECK-NEXT: [[TMP13:%.*]] = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> [[BIN_RDX]])
+; CHECK-NEXT: br i1 true, label %[[EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 0, %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[TMP13]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-NEXT: br label %[[LOOPS:.*]]
+; CHECK: [[LOOPS]]:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOPS]] ]
+; CHECK-NEXT: [[RED:%.*]] = phi i64 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[RED_NEXT:%.*]], %[[LOOPS]] ]
+; CHECK-NEXT: [[C:%.*]] = icmp eq i64 [[IV]], 0
+; CHECK-NEXT: [[AND:%.*]] = and i64 [[IV]], 0
+; CHECK-NEXT: [[TMP14:%.*]] = trunc i64 [[IV]] to i32
+; CHECK-NEXT: [[SHR:%.*]] = lshr i32 [[TMP14]], [[EXT_0]]
+; CHECK-NEXT: [[CONV_1:%.*]] = zext i32 [[SHR]] to i64
+; CHECK-NEXT: [[RED_NEXT_V:%.*]] = select i1 [[C]], i64 [[AND]], i64 [[CONV_1]]
+; CHECK-NEXT: [[RED_NEXT]] = or i64 [[RED_NEXT_V]], [[RED]]
+; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], 0
+; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOPS]], !llvm.loop [[LOOP5:![0-9]+]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: [[RES:%.*]] = phi i64 [ [[RED_NEXT]], %[[LOOPS]] ], [ [[TMP13]], %[[MIDDLE_BLOCK]] ]
+; CHECK-NEXT: ret i64 [[RES]]
+;
+entry:
+ %ext.0 = sext i8 0 to i32
+ br label %loops
+
+loops:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loops ]
+ %red = phi i64 [ 0, %entry ], [ %red.next, %loops ]
+ %c = icmp eq i64 %iv, 0
+ %and = and i64 %iv, 0
+ %0 = trunc i64 %iv to i32
+ %shr = lshr i32 %0, %ext.0
+ %conv.1 = zext i32 %shr to i64
+ %red.next.v = select i1 %c, i64 %and, i64 %conv.1
+ %red.next = or i64 %red.next.v, %red
+ %iv.next = add i64 %iv, 1
+ %ec = icmp eq i64 %iv.next, 0
+ br i1 %ec, label %exit, label %loops
+
+exit:
+ %res = phi i64 [ %red.next, %loops ]
+ ret i64 %res
+}
+
;.
; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}
+; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}
+; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]}
;.
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