[llvm] Hlsl radians spirv (PR #110800)
Adam Yang via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 2 01:29:20 PDT 2024
https://github.com/adam-yang created https://github.com/llvm/llvm-project/pull/110800
partially fixes https://github.com/llvm/llvm-project/issues/99151
### Changes
Added int_spv_radians intrinsic in IntrinsicsSPIRV.td
Added lowering for int_spv_radians in SPIRVInstructionSelector.cpp
Added DXIL backend test case
>From c520937ac3f917cdcddecc50bd21efc87b38ea72 Mon Sep 17 00:00:00 2001
From: Adam Yang <hanbyang at microsoft.com>
Date: Wed, 2 Oct 2024 00:11:14 -0700
Subject: [PATCH 1/2] Added radians selection for spirv
---
llvm/include/llvm/IR/IntrinsicsSPIRV.td | 1 +
.../Target/SPIRV/SPIRVInstructionSelector.cpp | 22 +++++++++
.../CodeGen/SPIRV/hlsl-intrinsics/radians.ll | 48 +++++++++++++++++++
3 files changed, 71 insertions(+)
create mode 100644 llvm/test/CodeGen/SPIRV/hlsl-intrinsics/radians.ll
diff --git a/llvm/include/llvm/IR/IntrinsicsSPIRV.td b/llvm/include/llvm/IR/IntrinsicsSPIRV.td
index 7ff3d58690ba75..7d1f10278e119c 100644
--- a/llvm/include/llvm/IR/IntrinsicsSPIRV.td
+++ b/llvm/include/llvm/IR/IntrinsicsSPIRV.td
@@ -83,4 +83,5 @@ let TargetPrefix = "spv" in {
[IntrNoMem, Commutative] >;
def int_spv_wave_is_first_lane : DefaultAttrsIntrinsic<[llvm_i1_ty], [], [IntrConvergent]>;
def int_spv_sign : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i32_ty>], [llvm_any_ty]>;
+ def int_spv_radians : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [llvm_anyfloat_ty]>;
}
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index 2f7efbdc81f845..3a786eb879b39f 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -247,6 +247,9 @@ class SPIRVInstructionSelector : public InstructionSelector {
bool selectStep(Register ResVReg, const SPIRVType *ResType,
MachineInstr &I) const;
+ bool selectRadians(Register ResVReg, const SPIRVType *ResType,
+ MachineInstr &I) const;
+
bool selectUnmergeValues(MachineInstr &I) const;
Register buildI32Constant(uint32_t Val, MachineInstr &I,
@@ -1783,6 +1786,23 @@ bool SPIRVInstructionSelector::selectStep(Register ResVReg,
.constrainAllUses(TII, TRI, RBI);
}
+bool SPIRVInstructionSelector::selectRadians(Register ResVReg,
+ const SPIRVType *ResType,
+ MachineInstr &I) const {
+
+ assert(I.getNumOperands() == 3);
+ assert(I.getOperand(2).isReg());
+ MachineBasicBlock &BB = *I.getParent();
+
+ return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst))
+ .addDef(ResVReg)
+ .addUse(GR.getSPIRVTypeID(ResType))
+ .addImm(static_cast<uint32_t>(SPIRV::InstructionSet::GLSL_std_450))
+ .addImm(GL::Radians)
+ .addUse(I.getOperand(2).getReg())
+ .constrainAllUses(TII, TRI, RBI);
+}
+
bool SPIRVInstructionSelector::selectBitreverse(Register ResVReg,
const SPIRVType *ResType,
MachineInstr &I) const {
@@ -2556,6 +2576,8 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
}
case Intrinsic::spv_step:
return selectStep(ResVReg, ResType, I);
+ case Intrinsic::spv_radians:
+ return selectRadians(ResVReg, ResType, I);
case Intrinsic::spv_value_md:
// ignore the intrinsic
break;
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/radians.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/radians.ll
new file mode 100644
index 00000000000000..1fe8ab30ed9538
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/radians.ll
@@ -0,0 +1,48 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+
+; CHECK-DAG: %[[#op_ext_glsl:]] = OpExtInstImport "GLSL.std.450"
+
+; CHECK-DAG: %[[#float_32:]] = OpTypeFloat 32
+; CHECK-DAG: %[[#float_16:]] = OpTypeFloat 16
+
+; CHECK-DAG: %[[#vec4_float_32:]] = OpTypeVector %[[#float_32]] 4
+; CHECK-DAG: %[[#vec4_float_16:]] = OpTypeVector %[[#float_16]] 4
+
+declare half @llvm.spv.radians.f16(half)
+declare float @llvm.spv.radians.f32(float)
+
+declare <4 x float> @llvm.spv.radians.v4f32(<4 x float>)
+declare <4 x half> @llvm.spv.radians.v4f16(<4 x half>)
+
+define noundef float @radians_float(float noundef %a) {
+entry:
+; CHECK: %[[#float_32_arg:]] = OpFunctionParameter %[[#float_32]]
+; CHECK: %[[#]] = OpExtInst %[[#float_32]] %[[#op_ext_glsl]] Radians %[[#float_32_arg]]
+ %elt.radians = call float @llvm.spv.radians.f32(float %a)
+ ret float %elt.radians
+}
+
+define noundef half @radians_half(half noundef %a) {
+entry:
+; CHECK: %[[#float_16_arg:]] = OpFunctionParameter %[[#float_16]]
+; CHECK: %[[#]] = OpExtInst %[[#float_16]] %[[#op_ext_glsl]] Radians %[[#float_16_arg]]
+ %elt.radians = call half @llvm.spv.radians.f16(half %a)
+ ret half %elt.radians
+}
+
+define noundef <4 x float> @radians_float_vector(<4 x float> noundef %a) {
+entry:
+; CHECK: %[[#vec4_float_32_arg:]] = OpFunctionParameter %[[#vec4_float_32]]
+; CHECK: %[[#]] = OpExtInst %[[#vec4_float_32]] %[[#op_ext_glsl]] Radians %[[#vec4_float_32_arg]]
+ %elt.radians = call <4 x float> @llvm.spv.radians.v4f32(<4 x float> %a)
+ ret <4 x float> %elt.radians
+}
+
+define noundef <4 x half> @radians_half_vector(<4 x half> noundef %a) {
+entry:
+; CHECK: %[[#vec4_float_16_arg:]] = OpFunctionParameter %[[#vec4_float_16]]
+; CHECK: %[[#]] = OpExtInst %[[#vec4_float_16]] %[[#op_ext_glsl]] Radians %[[#vec4_float_16_arg]]
+ %elt.radians = call <4 x half> @llvm.spv.radians.v4f16(<4 x half> %a)
+ ret <4 x half> %elt.radians
+}
>From 1c6b14b94fc2f5835c4d57034a542978a404126d Mon Sep 17 00:00:00 2001
From: Adam Yang <hanbyang at microsoft.com>
Date: Wed, 2 Oct 2024 01:22:27 -0700
Subject: [PATCH 2/2] Added nomem attribute
---
llvm/include/llvm/IR/IntrinsicsSPIRV.td | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/include/llvm/IR/IntrinsicsSPIRV.td b/llvm/include/llvm/IR/IntrinsicsSPIRV.td
index 7d1f10278e119c..c541f99942bd9c 100644
--- a/llvm/include/llvm/IR/IntrinsicsSPIRV.td
+++ b/llvm/include/llvm/IR/IntrinsicsSPIRV.td
@@ -83,5 +83,5 @@ let TargetPrefix = "spv" in {
[IntrNoMem, Commutative] >;
def int_spv_wave_is_first_lane : DefaultAttrsIntrinsic<[llvm_i1_ty], [], [IntrConvergent]>;
def int_spv_sign : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i32_ty>], [llvm_any_ty]>;
- def int_spv_radians : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [llvm_anyfloat_ty]>;
+ def int_spv_radians : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [llvm_anyfloat_ty], [IntrNoMem]>;
}
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