[clang] [llvm] [BPF] Add load-acquire and store-release instructions under -mcpu=v5 (PR #108636)

[via llvm-commits]

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@@ -522,6 +526,28 @@ let Predicates = [BPFNoALU32] in {
 }
 def STD : STOREi64<BPF_DW, "u64", store>;
 
+class relaxed_store<PatFrag base>
+  : PatFrag<(ops node:$val, node:$ptr), (base node:$val, node:$ptr)> {
+  let IsAtomic = 1;
+  let IsAtomicOrderingReleaseOrStronger = 0;
+}
+
+class releasing_store<PatFrag base>
+  : PatFrag<(ops node:$val, node:$ptr), (base node:$val, node:$ptr)> {
+  let IsAtomic = 1;
+  let IsAtomicOrderingRelease = 1;
+}
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yonghong-song wrote:

Okay, I see. It is interesting that arm64 generates the same insn with release and seq_cst. In my thinking, we should just support __ATOMIC_ACQUIRE and __ATOMIC_RELEASE since currently with __ATOMIC_RELAXED, e.g. __atomic_load_n(ptr, __ATOMIC_RELAXED), the actually generated code should be '*ptr'. Is my interpretation correct or  __atomic_load_n(ptr, __ATOMIC_RELAXED) could have semantics beyond '*ptr'?


https://github.com/llvm/llvm-project/pull/108636