[llvm] [RISCV][GISEL] instruction-select vmclr (PR #110782)

[Michael Maitland via llvm-commits]

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@@ -379,6 +381,26 @@ RISCVInstructionSelector::selectSHXADD_UWOp(MachineOperand &Root,
   return std::nullopt;
 }
 
+InstructionSelector::ComplexRendererFns
+RISCVInstructionSelector::selectVLOp(MachineOperand &Root) const {
+  MachineRegisterInfo &MRI =
+      Root.getParent()->getParent()->getParent()->getRegInfo();
+  assert(Root.isReg() && "Expected operand to be a Register");
+  MachineInstr *RootDef = MRI.getVRegDef(Root.getReg());
+
+  if (RootDef->getOpcode() == TargetOpcode::G_CONSTANT &&
+      RootDef->getOperand(1).getCImm()->getSExtValue() == RISCV::VLMaxSentinel)
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michaelmaitland wrote:

ah, I see the comment from the other patch. Will update both.

https://github.com/llvm/llvm-project/pull/110782