[llvm] [RISCV][GISEL] instruction-select vmclr (PR #110782)
Michael Maitland via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 1 20:49:19 PDT 2024
https://github.com/michaelmaitland updated https://github.com/llvm/llvm-project/pull/110782
>From 8de800a2fb129efefd90ee2c993a7933acb6b6ee Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Tue, 1 Oct 2024 19:14:34 -0700
Subject: [PATCH 1/3] [RISCV][GISEL] instruction-select vmclr
---
.../RISCV/GISel/RISCVInstructionSelector.cpp | 22 ++++
llvm/lib/Target/RISCV/RISCVGISel.td | 5 +
.../instruction-select/rvv/vmclr-rv32.mir | 124 ++++++++++++++++++
.../instruction-select/rvv/vmclr-rv64.mir | 124 ++++++++++++++++++
4 files changed, 275 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv32.mir
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv64.mir
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 92d00c26bd219c..cb28f40d64b176 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -100,6 +100,8 @@ class RISCVInstructionSelector : public InstructionSelector {
return selectSHXADD_UWOp(Root, ShAmt);
}
+ ComplexRendererFns selectVLOp(MachineOperand &Root) const;
+
// Custom renderers for tablegen
void renderNegImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
int OpIdx) const;
@@ -379,6 +381,26 @@ RISCVInstructionSelector::selectSHXADD_UWOp(MachineOperand &Root,
return std::nullopt;
}
+InstructionSelector::ComplexRendererFns
+RISCVInstructionSelector::selectVLOp(MachineOperand &Root) const {
+ MachineRegisterInfo &MRI =
+ Root.getParent()->getParent()->getParent()->getRegInfo();
+ assert(Root.isReg() && "Expected operand to be a Register");
+ MachineInstr *RootDef = MRI.getVRegDef(Root.getReg());
+
+ if (RootDef->getOpcode() == TargetOpcode::G_CONSTANT &&
+ RootDef->getOperand(1).getCImm()->getSExtValue() == RISCV::VLMaxSentinel)
+ // If the operand is a G_CONSTANT with value VLMaxSentinel, convert it
+ // to an immediate with value VLMaxSentinel. This is recognized specially by
+ // the vsetvli insertion pass.
+ return {
+ {[=](MachineInstrBuilder &MIB) { MIB.addImm(RISCV::VLMaxSentinel); }}};
+
+ // FIXME: Implement non-VLMAX case. ISEL will fail gracefully by returning
+ // like this for now.
+ return std::nullopt;
+}
+
InstructionSelector::ComplexRendererFns
RISCVInstructionSelector::selectAddrRegImm(MachineOperand &Root) const {
MachineFunction &MF = *Root.getParent()->getParent()->getParent();
diff --git a/llvm/lib/Target/RISCV/RISCVGISel.td b/llvm/lib/Target/RISCV/RISCVGISel.td
index 319611111cf470..a7d46e6edd39f1 100644
--- a/llvm/lib/Target/RISCV/RISCVGISel.td
+++ b/llvm/lib/Target/RISCV/RISCVGISel.td
@@ -50,6 +50,11 @@ def GIAddrRegImm :
GIComplexOperandMatcher<s32, "selectAddrRegImm">,
GIComplexPatternEquiv<AddrRegImm>;
+def GIVLOpS32 : GIComplexOperandMatcher<s32, "selectVLOp">,
+ GIComplexPatternEquiv<VLOp>;
+def GIVLOpS64 : GIComplexOperandMatcher<s64, "selectVLOp">,
+ GIComplexPatternEquiv<VLOp>;
+
// Convert from i32 immediate to i64 target immediate to make SelectionDAG type
// checking happy so we can use ADDIW which expects an XLen immediate.
def as_i64imm : SDNodeXForm<imm, [{
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv32.mir
new file mode 100644
index 00000000000000..1ef1312cc17c0e
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv32.mir
@@ -0,0 +1,124 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -mattr=+v,+m -run-pass=instruction-select \
+# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: splat_zero_nxv1i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv1i1
+ ; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s32) = G_CONSTANT i32 -1
+ %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
+ $v0 = COPY %1(<vscale x 1 x s1>)
+ PseudoRET implicit $v0
+
+...
+---
+name: splat_zero_nxv2i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv2i1
+ ; CHECK: [[PseudoVMCLR_M_B2_:%[0-9]+]]:vr = PseudoVMCLR_M_B2 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B2_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s32) = G_CONSTANT i32 -1
+ %1:vrb(<vscale x 2 x s1>) = G_VMCLR_VL %0(s32)
+ $v0 = COPY %1(<vscale x 2 x s1>)
+ PseudoRET implicit $v0
+
+...
+---
+name: splat_zero_nxv4i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv4i1
+ ; CHECK: [[PseudoVMCLR_M_B4_:%[0-9]+]]:vr = PseudoVMCLR_M_B4 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B4_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s32) = G_CONSTANT i32 -1
+ %1:vrb(<vscale x 4 x s1>) = G_VMCLR_VL %0(s32)
+ $v0 = COPY %1(<vscale x 4 x s1>)
+ PseudoRET implicit $v0
+
+...
+---
+name: splat_zero_nxv8i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv8i1
+ ; CHECK: [[PseudoVMCLR_M_B8_:%[0-9]+]]:vr = PseudoVMCLR_M_B8 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B8_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s32) = G_CONSTANT i32 -1
+ %1:vrb(<vscale x 8 x s1>) = G_VMCLR_VL %0(s32)
+ $v0 = COPY %1(<vscale x 8 x s1>)
+ PseudoRET implicit $v0
+
+...
+---
+name: splat_zero_nxv16i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv16i1
+ ; CHECK: [[PseudoVMCLR_M_B16_:%[0-9]+]]:vr = PseudoVMCLR_M_B16 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B16_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s32) = G_CONSTANT i32 -1
+ %1:vrb(<vscale x 16 x s1>) = G_VMCLR_VL %0(s32)
+ $v0 = COPY %1(<vscale x 16 x s1>)
+ PseudoRET implicit $v0
+
+...
+---
+name: splat_zero_nxv32i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv32i1
+ ; CHECK: [[PseudoVMCLR_M_B32_:%[0-9]+]]:vr = PseudoVMCLR_M_B32 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B32_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s32) = G_CONSTANT i32 -1
+ %1:vrb(<vscale x 32 x s1>) = G_VMCLR_VL %0(s32)
+ $v0 = COPY %1(<vscale x 32 x s1>)
+ PseudoRET implicit $v0
+
+...
+---
+name: splat_zero_nxv64i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv64i1
+ ; CHECK: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s32) = G_CONSTANT i32 -1
+ %1:vrb(<vscale x 64 x s1>) = G_VMCLR_VL %0(s32)
+ $v0 = COPY %1(<vscale x 64 x s1>)
+ PseudoRET implicit $v0
+
+...
+
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv64.mir
new file mode 100644
index 00000000000000..b7541cd4e96fb4
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv64.mir
@@ -0,0 +1,124 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -mattr=+v,+m -run-pass=instruction-select \
+# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: splat_zero_nxv1i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv1i1
+ ; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s64) = G_CONSTANT i64 -1
+ %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s64)
+ $v0 = COPY %1(<vscale x 1 x s1>)
+ PseudoRET implicit $v0
+
+...
+---
+name: splat_zero_nxv2i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv2i1
+ ; CHECK: [[PseudoVMCLR_M_B2_:%[0-9]+]]:vr = PseudoVMCLR_M_B2 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B2_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s64) = G_CONSTANT i64 -1
+ %1:vrb(<vscale x 2 x s1>) = G_VMCLR_VL %0(s64)
+ $v0 = COPY %1(<vscale x 2 x s1>)
+ PseudoRET implicit $v0
+
+...
+---
+name: splat_zero_nxv4i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv4i1
+ ; CHECK: [[PseudoVMCLR_M_B4_:%[0-9]+]]:vr = PseudoVMCLR_M_B4 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B4_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s64) = G_CONSTANT i64 -1
+ %1:vrb(<vscale x 4 x s1>) = G_VMCLR_VL %0(s64)
+ $v0 = COPY %1(<vscale x 4 x s1>)
+ PseudoRET implicit $v0
+
+...
+---
+name: splat_zero_nxv8i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv8i1
+ ; CHECK: [[PseudoVMCLR_M_B8_:%[0-9]+]]:vr = PseudoVMCLR_M_B8 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B8_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s64) = G_CONSTANT i64 -1
+ %1:vrb(<vscale x 8 x s1>) = G_VMCLR_VL %0(s64)
+ $v0 = COPY %1(<vscale x 8 x s1>)
+ PseudoRET implicit $v0
+
+...
+---
+name: splat_zero_nxv16i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv16i1
+ ; CHECK: [[PseudoVMCLR_M_B16_:%[0-9]+]]:vr = PseudoVMCLR_M_B16 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B16_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s64) = G_CONSTANT i64 -1
+ %1:vrb(<vscale x 16 x s1>) = G_VMCLR_VL %0(s64)
+ $v0 = COPY %1(<vscale x 16 x s1>)
+ PseudoRET implicit $v0
+
+...
+---
+name: splat_zero_nxv32i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv32i1
+ ; CHECK: [[PseudoVMCLR_M_B32_:%[0-9]+]]:vr = PseudoVMCLR_M_B32 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B32_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s64) = G_CONSTANT i64 -1
+ %1:vrb(<vscale x 32 x s1>) = G_VMCLR_VL %0(s64)
+ $v0 = COPY %1(<vscale x 32 x s1>)
+ PseudoRET implicit $v0
+
+...
+---
+name: splat_zero_nxv64i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv64i1
+ ; CHECK: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s64) = G_CONSTANT i64 -1
+ %1:vrb(<vscale x 64 x s1>) = G_VMCLR_VL %0(s64)
+ $v0 = COPY %1(<vscale x 64 x s1>)
+ PseudoRET implicit $v0
+
+...
+
>From b0762dfdd9b2556799d544e743d4125f8f98c930 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Tue, 1 Oct 2024 19:46:54 -0700
Subject: [PATCH 2/3] fixup! demonstrate the functionality supported in
selectVLOp
---
.../rvv/fail-select-vl-badnegative.mir | 17 +++++++++++++++++
.../rvv/fail-select-vl-nonconst.mir | 19 +++++++++++++++++++
.../rvv/fail-select-vl-nonzero.mir | 19 +++++++++++++++++++
.../rvv/fail-select-vl-zero.mir | 18 ++++++++++++++++++
4 files changed, 73 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-badnegative.mir
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-nonconst.mir
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-nonzero.mir
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-zero.mir
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-badnegative.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-badnegative.mir
new file mode 100644
index 00000000000000..f71c0aab9c05ef
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-badnegative.mir
@@ -0,0 +1,17 @@
+# RUN: not --crash llc -mtriple=riscv32 -mattr=+v,+m -run-pass=instruction-select \
+# RUN: -verify-machineinstrs %s 2>&1 | FileCheck %s
+
+---
+# CHECK: LLVM ERROR: cannot select:
+name: bad_negative_vl
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ %0:gprb(s32) = G_CONSTANT i32 -2
+ %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
+ $v0 = COPY %1(<vscale x 1 x s1>)
+ PseudoRET implicit $v0
+...
+
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-nonconst.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-nonconst.mir
new file mode 100644
index 00000000000000..88d301f752a7dc
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-nonconst.mir
@@ -0,0 +1,19 @@
+# RUN: not --crash llc -mtriple=riscv32 -mattr=+v,+m -run-pass=instruction-select \
+# RUN: -verify-machineinstrs %s 2>&1 | FileCheck %s
+
+# FIXME: This should be supported in the future
+---
+name: not_implemented_vl_nonconst
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $x10
+ %0:gprb(s32) = COPY $x10
+ %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
+ $v0 = COPY %1(<vscale x 1 x s1>)
+ PseudoRET implicit $v0
+
+# CHECK: LLVM ERROR: cannot select
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-nonzero.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-nonzero.mir
new file mode 100644
index 00000000000000..f12a800a4a2eef
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-nonzero.mir
@@ -0,0 +1,19 @@
+# RUN: not --crash llc -mtriple=riscv32 -mattr=+v,+m -run-pass=instruction-select \
+# RUN: -verify-machineinstrs %s 2>&1 | FileCheck %s
+
+# FIXME: This should be supported in the future
+---
+name: not_implemented_vl_nonzero
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ %0:gprb(s32) = G_CONSTANT i32 1
+ %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
+ $v0 = COPY %1(<vscale x 1 x s1>)
+ PseudoRET implicit $v0
+
+# CHECK: LLVM ERROR: cannot select
+...
+
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-zero.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-zero.mir
new file mode 100644
index 00000000000000..9338e4fb32e3a2
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-zero.mir
@@ -0,0 +1,18 @@
+# RUN: not --crash llc -mtriple=riscv32 -mattr=+v,+m -run-pass=instruction-select \
+# RUN: -verify-machineinstrs %s 2>&1 | FileCheck %s
+
+# FIXME: This should be supported in the future
+---
+# CHECK: LLVM ERROR: cannot select
+name: not_implemented_vl0
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ %0:gprb(s32) = G_CONSTANT i32 0
+ %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
+ $v0 = COPY %1(<vscale x 1 x s1>)
+ PseudoRET implicit $v0
+
+...
>From 16d50d2a817536cfe67ccc0ac4da871d3ae49317 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Tue, 1 Oct 2024 20:47:18 -0700
Subject: [PATCH 3/3] fixup! implement non-VLMAX cases in selectVLOp
---
.../RISCV/GISel/RISCVInstructionSelector.cpp | 26 ++++---
.../rvv/fail-select-vl-nonconst.mir | 19 -----
.../rvv/fail-select-vl-nonzero.mir | 19 -----
.../rvv/fail-select-vl-zero.mir | 18 -----
.../instruction-select/rvv/select-vlop.mir | 70 +++++++++++++++++++
5 files changed, 85 insertions(+), 67 deletions(-)
delete mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-nonconst.mir
delete mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-nonzero.mir
delete mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-zero.mir
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/select-vlop.mir
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index cb28f40d64b176..a5847d8c678a74 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -388,17 +388,21 @@ RISCVInstructionSelector::selectVLOp(MachineOperand &Root) const {
assert(Root.isReg() && "Expected operand to be a Register");
MachineInstr *RootDef = MRI.getVRegDef(Root.getReg());
- if (RootDef->getOpcode() == TargetOpcode::G_CONSTANT &&
- RootDef->getOperand(1).getCImm()->getSExtValue() == RISCV::VLMaxSentinel)
- // If the operand is a G_CONSTANT with value VLMaxSentinel, convert it
- // to an immediate with value VLMaxSentinel. This is recognized specially by
- // the vsetvli insertion pass.
- return {
- {[=](MachineInstrBuilder &MIB) { MIB.addImm(RISCV::VLMaxSentinel); }}};
-
- // FIXME: Implement non-VLMAX case. ISEL will fail gracefully by returning
- // like this for now.
- return std::nullopt;
+ if (RootDef->getOpcode() == TargetOpcode::G_CONSTANT) {
+ auto C = RootDef->getOperand(1).getCImm();
+ if (C->getSExtValue() == RISCV::VLMaxSentinel || C->getValue().isAllOnes())
+ // If the operand is a G_CONSTANT with value VLMaxSentinel or all ones,
+ // convert it to an immediate with value VLMaxSentinel. This is recognized
+ // specially by the vsetvli insertion pass.
+ return {{[=](MachineInstrBuilder &MIB) {
+ MIB.addImm(RISCV::VLMaxSentinel);
+ }}};
+
+ if (isUInt<5>(C->getZExtValue()))
+ return {
+ {[=](MachineInstrBuilder &MIB) { MIB.addImm(C->getZExtValue()); }}};
+ }
+ return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Root.getReg()); }}};
}
InstructionSelector::ComplexRendererFns
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-nonconst.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-nonconst.mir
deleted file mode 100644
index 88d301f752a7dc..00000000000000
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-nonconst.mir
+++ /dev/null
@@ -1,19 +0,0 @@
-# RUN: not --crash llc -mtriple=riscv32 -mattr=+v,+m -run-pass=instruction-select \
-# RUN: -verify-machineinstrs %s 2>&1 | FileCheck %s
-
-# FIXME: This should be supported in the future
----
-name: not_implemented_vl_nonconst
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1:
- liveins: $x10
- %0:gprb(s32) = COPY $x10
- %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
- $v0 = COPY %1(<vscale x 1 x s1>)
- PseudoRET implicit $v0
-
-# CHECK: LLVM ERROR: cannot select
-...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-nonzero.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-nonzero.mir
deleted file mode 100644
index f12a800a4a2eef..00000000000000
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-nonzero.mir
+++ /dev/null
@@ -1,19 +0,0 @@
-# RUN: not --crash llc -mtriple=riscv32 -mattr=+v,+m -run-pass=instruction-select \
-# RUN: -verify-machineinstrs %s 2>&1 | FileCheck %s
-
-# FIXME: This should be supported in the future
----
-name: not_implemented_vl_nonzero
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1:
- %0:gprb(s32) = G_CONSTANT i32 1
- %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
- $v0 = COPY %1(<vscale x 1 x s1>)
- PseudoRET implicit $v0
-
-# CHECK: LLVM ERROR: cannot select
-...
-
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-zero.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-zero.mir
deleted file mode 100644
index 9338e4fb32e3a2..00000000000000
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/fail-select-vl-zero.mir
+++ /dev/null
@@ -1,18 +0,0 @@
-# RUN: not --crash llc -mtriple=riscv32 -mattr=+v,+m -run-pass=instruction-select \
-# RUN: -verify-machineinstrs %s 2>&1 | FileCheck %s
-
-# FIXME: This should be supported in the future
----
-# CHECK: LLVM ERROR: cannot select
-name: not_implemented_vl0
-legalized: true
-regBankSelected: true
-tracksRegLiveness: true
-body: |
- bb.1:
- %0:gprb(s32) = G_CONSTANT i32 0
- %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
- $v0 = COPY %1(<vscale x 1 x s1>)
- PseudoRET implicit $v0
-
-...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/select-vlop.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/select-vlop.mir
new file mode 100644
index 00000000000000..d43195c8b00968
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/select-vlop.mir
@@ -0,0 +1,70 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=riscv32 -mattr=+v,+m -run-pass=instruction-select \
+# RUN: -verify-machineinstrs %s -o - | FileCheck %s
+
+name: negative_vl
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ %0:gprb(s32) = G_CONSTANT i32 -2
+ %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
+ $v0 = COPY %1(<vscale x 1 x s1>)
+ PseudoRET implicit $v0
+...
+---
+name: nonconst_vl
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $x10
+ ; CHECK-LABEL: name: nonconst_vl
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10
+ ; CHECK-NEXT: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 [[COPY]], 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s32) = COPY $x10
+ %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
+ $v0 = COPY %1(<vscale x 1 x s1>)
+ PseudoRET implicit $v0
+...
+
+---
+name: nonzero_vl
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: nonzero_vl
+ ; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s32) = G_CONSTANT i32 1
+ %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
+ $v0 = COPY %1(<vscale x 1 x s1>)
+ PseudoRET implicit $v0
+...
+
+---
+name: zero_vl
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: zero_vl
+ ; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 0, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s32) = G_CONSTANT i32 0
+ %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
+ $v0 = COPY %1(<vscale x 1 x s1>)
+ PseudoRET implicit $v0
+...
+
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