[llvm] [RISCV][GISEL] instruction-select vmclr (PR #110782)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 1 19:16:32 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Michael Maitland (michaelmaitland)
<details>
<summary>Changes</summary>
This is stacked on #<!-- -->110778
---
Full diff: https://github.com/llvm/llvm-project/pull/110782.diff
4 Files Affected:
- (modified) llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp (+22)
- (modified) llvm/lib/Target/RISCV/RISCVGISel.td (+5)
- (added) llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv32.mir (+124)
- (added) llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv64.mir (+124)
``````````diff
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 92d00c26bd219c..cb28f40d64b176 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -100,6 +100,8 @@ class RISCVInstructionSelector : public InstructionSelector {
return selectSHXADD_UWOp(Root, ShAmt);
}
+ ComplexRendererFns selectVLOp(MachineOperand &Root) const;
+
// Custom renderers for tablegen
void renderNegImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
int OpIdx) const;
@@ -379,6 +381,26 @@ RISCVInstructionSelector::selectSHXADD_UWOp(MachineOperand &Root,
return std::nullopt;
}
+InstructionSelector::ComplexRendererFns
+RISCVInstructionSelector::selectVLOp(MachineOperand &Root) const {
+ MachineRegisterInfo &MRI =
+ Root.getParent()->getParent()->getParent()->getRegInfo();
+ assert(Root.isReg() && "Expected operand to be a Register");
+ MachineInstr *RootDef = MRI.getVRegDef(Root.getReg());
+
+ if (RootDef->getOpcode() == TargetOpcode::G_CONSTANT &&
+ RootDef->getOperand(1).getCImm()->getSExtValue() == RISCV::VLMaxSentinel)
+ // If the operand is a G_CONSTANT with value VLMaxSentinel, convert it
+ // to an immediate with value VLMaxSentinel. This is recognized specially by
+ // the vsetvli insertion pass.
+ return {
+ {[=](MachineInstrBuilder &MIB) { MIB.addImm(RISCV::VLMaxSentinel); }}};
+
+ // FIXME: Implement non-VLMAX case. ISEL will fail gracefully by returning
+ // like this for now.
+ return std::nullopt;
+}
+
InstructionSelector::ComplexRendererFns
RISCVInstructionSelector::selectAddrRegImm(MachineOperand &Root) const {
MachineFunction &MF = *Root.getParent()->getParent()->getParent();
diff --git a/llvm/lib/Target/RISCV/RISCVGISel.td b/llvm/lib/Target/RISCV/RISCVGISel.td
index 319611111cf470..a7d46e6edd39f1 100644
--- a/llvm/lib/Target/RISCV/RISCVGISel.td
+++ b/llvm/lib/Target/RISCV/RISCVGISel.td
@@ -50,6 +50,11 @@ def GIAddrRegImm :
GIComplexOperandMatcher<s32, "selectAddrRegImm">,
GIComplexPatternEquiv<AddrRegImm>;
+def GIVLOpS32 : GIComplexOperandMatcher<s32, "selectVLOp">,
+ GIComplexPatternEquiv<VLOp>;
+def GIVLOpS64 : GIComplexOperandMatcher<s64, "selectVLOp">,
+ GIComplexPatternEquiv<VLOp>;
+
// Convert from i32 immediate to i64 target immediate to make SelectionDAG type
// checking happy so we can use ADDIW which expects an XLen immediate.
def as_i64imm : SDNodeXForm<imm, [{
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv32.mir
new file mode 100644
index 00000000000000..1ef1312cc17c0e
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv32.mir
@@ -0,0 +1,124 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -mattr=+v,+m -run-pass=instruction-select \
+# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: splat_zero_nxv1i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv1i1
+ ; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s32) = G_CONSTANT i32 -1
+ %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)
+ $v0 = COPY %1(<vscale x 1 x s1>)
+ PseudoRET implicit $v0
+
+...
+---
+name: splat_zero_nxv2i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv2i1
+ ; CHECK: [[PseudoVMCLR_M_B2_:%[0-9]+]]:vr = PseudoVMCLR_M_B2 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B2_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s32) = G_CONSTANT i32 -1
+ %1:vrb(<vscale x 2 x s1>) = G_VMCLR_VL %0(s32)
+ $v0 = COPY %1(<vscale x 2 x s1>)
+ PseudoRET implicit $v0
+
+...
+---
+name: splat_zero_nxv4i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv4i1
+ ; CHECK: [[PseudoVMCLR_M_B4_:%[0-9]+]]:vr = PseudoVMCLR_M_B4 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B4_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s32) = G_CONSTANT i32 -1
+ %1:vrb(<vscale x 4 x s1>) = G_VMCLR_VL %0(s32)
+ $v0 = COPY %1(<vscale x 4 x s1>)
+ PseudoRET implicit $v0
+
+...
+---
+name: splat_zero_nxv8i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv8i1
+ ; CHECK: [[PseudoVMCLR_M_B8_:%[0-9]+]]:vr = PseudoVMCLR_M_B8 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B8_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s32) = G_CONSTANT i32 -1
+ %1:vrb(<vscale x 8 x s1>) = G_VMCLR_VL %0(s32)
+ $v0 = COPY %1(<vscale x 8 x s1>)
+ PseudoRET implicit $v0
+
+...
+---
+name: splat_zero_nxv16i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv16i1
+ ; CHECK: [[PseudoVMCLR_M_B16_:%[0-9]+]]:vr = PseudoVMCLR_M_B16 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B16_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s32) = G_CONSTANT i32 -1
+ %1:vrb(<vscale x 16 x s1>) = G_VMCLR_VL %0(s32)
+ $v0 = COPY %1(<vscale x 16 x s1>)
+ PseudoRET implicit $v0
+
+...
+---
+name: splat_zero_nxv32i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv32i1
+ ; CHECK: [[PseudoVMCLR_M_B32_:%[0-9]+]]:vr = PseudoVMCLR_M_B32 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B32_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s32) = G_CONSTANT i32 -1
+ %1:vrb(<vscale x 32 x s1>) = G_VMCLR_VL %0(s32)
+ $v0 = COPY %1(<vscale x 32 x s1>)
+ PseudoRET implicit $v0
+
+...
+---
+name: splat_zero_nxv64i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv64i1
+ ; CHECK: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s32) = G_CONSTANT i32 -1
+ %1:vrb(<vscale x 64 x s1>) = G_VMCLR_VL %0(s32)
+ $v0 = COPY %1(<vscale x 64 x s1>)
+ PseudoRET implicit $v0
+
+...
+
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv64.mir
new file mode 100644
index 00000000000000..b7541cd4e96fb4
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv64.mir
@@ -0,0 +1,124 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -mattr=+v,+m -run-pass=instruction-select \
+# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: splat_zero_nxv1i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv1i1
+ ; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s64) = G_CONSTANT i64 -1
+ %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s64)
+ $v0 = COPY %1(<vscale x 1 x s1>)
+ PseudoRET implicit $v0
+
+...
+---
+name: splat_zero_nxv2i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv2i1
+ ; CHECK: [[PseudoVMCLR_M_B2_:%[0-9]+]]:vr = PseudoVMCLR_M_B2 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B2_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s64) = G_CONSTANT i64 -1
+ %1:vrb(<vscale x 2 x s1>) = G_VMCLR_VL %0(s64)
+ $v0 = COPY %1(<vscale x 2 x s1>)
+ PseudoRET implicit $v0
+
+...
+---
+name: splat_zero_nxv4i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv4i1
+ ; CHECK: [[PseudoVMCLR_M_B4_:%[0-9]+]]:vr = PseudoVMCLR_M_B4 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B4_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s64) = G_CONSTANT i64 -1
+ %1:vrb(<vscale x 4 x s1>) = G_VMCLR_VL %0(s64)
+ $v0 = COPY %1(<vscale x 4 x s1>)
+ PseudoRET implicit $v0
+
+...
+---
+name: splat_zero_nxv8i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv8i1
+ ; CHECK: [[PseudoVMCLR_M_B8_:%[0-9]+]]:vr = PseudoVMCLR_M_B8 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B8_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s64) = G_CONSTANT i64 -1
+ %1:vrb(<vscale x 8 x s1>) = G_VMCLR_VL %0(s64)
+ $v0 = COPY %1(<vscale x 8 x s1>)
+ PseudoRET implicit $v0
+
+...
+---
+name: splat_zero_nxv16i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv16i1
+ ; CHECK: [[PseudoVMCLR_M_B16_:%[0-9]+]]:vr = PseudoVMCLR_M_B16 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B16_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s64) = G_CONSTANT i64 -1
+ %1:vrb(<vscale x 16 x s1>) = G_VMCLR_VL %0(s64)
+ $v0 = COPY %1(<vscale x 16 x s1>)
+ PseudoRET implicit $v0
+
+...
+---
+name: splat_zero_nxv32i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv32i1
+ ; CHECK: [[PseudoVMCLR_M_B32_:%[0-9]+]]:vr = PseudoVMCLR_M_B32 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B32_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s64) = G_CONSTANT i64 -1
+ %1:vrb(<vscale x 32 x s1>) = G_VMCLR_VL %0(s64)
+ $v0 = COPY %1(<vscale x 32 x s1>)
+ PseudoRET implicit $v0
+
+...
+---
+name: splat_zero_nxv64i1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: splat_zero_nxv64i1
+ ; CHECK: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 -1, 0 /* e8 */
+ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]]
+ ; CHECK-NEXT: PseudoRET implicit $v0
+ %0:gprb(s64) = G_CONSTANT i64 -1
+ %1:vrb(<vscale x 64 x s1>) = G_VMCLR_VL %0(s64)
+ $v0 = COPY %1(<vscale x 64 x s1>)
+ PseudoRET implicit $v0
+
+...
+
``````````
</details>
https://github.com/llvm/llvm-project/pull/110782
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