[llvm] 916c830 - Revert "[RISCV][GISel] Remove unused isel patterns for s32 shifts with s64 shift amount."

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2024-10-01T12:14:55-07:00
New Revision: 916c83020967d72a5870b4b3d058998f367acd1a

URL: https://github.com/llvm/llvm-project/commit/916c83020967d72a5870b4b3d058998f367acd1a
DIFF: https://github.com/llvm/llvm-project/commit/916c83020967d72a5870b4b3d058998f367acd1a.diff

LOG: Revert "[RISCV][GISel] Remove unused isel patterns for s32 shifts with s64 shift amount."

This reverts commit 9e45e7facbdec209a06ee20fcfbb7d0622835e21.

I found a way that these can be used. I think it's a bug somewhere
else that I need to address separately first.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVGISel.td
    llvm/test/CodeGen/RISCV/GlobalISel/shift.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVGISel.td b/llvm/lib/Target/RISCV/RISCVGISel.td
index e14de46673aba8..84c00d31800cee 100644
--- a/llvm/lib/Target/RISCV/RISCVGISel.td
+++ b/llvm/lib/Target/RISCV/RISCVGISel.td
@@ -95,6 +95,10 @@ def : Pat<(XLenVT (sub GPR:$rs1, simm12Plus1:$imm)),
 let Predicates = [IsRV64] in {
 def : Pat<(i32 (sub GPR:$rs1, simm12Plus1i32:$imm)),
           (ADDIW GPR:$rs1, (i64 (NegImm $imm)))>;
+
+def : Pat<(i32 (shl GPR:$rs1, (i32 GPR:$rs2))), (SLLW GPR:$rs1, GPR:$rs2)>;
+def : Pat<(i32 (sra GPR:$rs1, (i32 GPR:$rs2))), (SRAW GPR:$rs1, GPR:$rs2)>;
+def : Pat<(i32 (srl GPR:$rs1, (i32 GPR:$rs2))), (SRLW GPR:$rs1, GPR:$rs2)>;
 }
 
 // Ptr type used in patterns with GlobalISelEmitter
@@ -191,9 +195,9 @@ def : PatGprGpr<sub, SUBW, i32, i32>;
 def : PatGprGpr<and, AND, i32, i32>;
 def : PatGprGpr<or, OR, i32, i32>;
 def : PatGprGpr<xor, XOR, i32, i32>;
-def : PatGprGpr<shl, SLLW, i32, i32>;
-def : PatGprGpr<srl, SRLW, i32, i32>;
-def : PatGprGpr<sra, SRAW, i32, i32>;
+def : PatGprGpr<shiftopw<shl>, SLLW, i32, i64>;
+def : PatGprGpr<shiftopw<srl>, SRLW, i32, i64>;
+def : PatGprGpr<shiftopw<sra>, SRAW, i32, i64>;
 
 def : Pat<(i32 (add GPR:$rs1, simm12i32:$imm)),
           (ADDIW GPR:$rs1, (i64 (as_i64imm $imm)))>;

diff  --git a/llvm/test/CodeGen/RISCV/GlobalISel/shift.ll b/llvm/test/CodeGen/RISCV/GlobalISel/shift.ll
index b75cbf8e871a1b..3e090507ad6428 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/shift.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/shift.ll
@@ -46,3 +46,57 @@ define i16 @test_shl_i48(i48 %x) {
   %trunc = trunc i48 %shl to i16
   ret i16 %trunc
 }
+
+define i16 @test_lshr_i48_2(i48 %x, i48 %y) {
+; RV32-LABEL: test_lshr_i48_2:
+; RV32:       # %bb.0:
+; RV32-NEXT:    andi a2, a2, 15
+; RV32-NEXT:    srl a0, a0, a2
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: test_lshr_i48_2:
+; RV64:       # %bb.0:
+; RV64-NEXT:    andi a1, a1, 15
+; RV64-NEXT:    srlw a0, a0, a1
+; RV64-NEXT:    ret
+  %and = and i48 %y, 15
+  %lshr = lshr i48 %x, %and
+  %trunc = trunc i48 %lshr to i16
+  ret i16 %trunc
+}
+
+define i16 @test_ashr_i48_2(i48 %x, i48 %y) {
+; RV32-LABEL: test_ashr_i48_2:
+; RV32:       # %bb.0:
+; RV32-NEXT:    andi a2, a2, 15
+; RV32-NEXT:    sra a0, a0, a2
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: test_ashr_i48_2:
+; RV64:       # %bb.0:
+; RV64-NEXT:    andi a1, a1, 15
+; RV64-NEXT:    sraw a0, a0, a1
+; RV64-NEXT:    ret
+  %and = and i48 %y, 15
+  %ashr = ashr i48 %x, %and
+  %trunc = trunc i48 %ashr to i16
+  ret i16 %trunc
+}
+
+define i16 @test_shl_i48_2(i48 %x, i48 %y) {
+; RV32-LABEL: test_shl_i48_2:
+; RV32:       # %bb.0:
+; RV32-NEXT:    andi a2, a2, 15
+; RV32-NEXT:    sll a0, a0, a2
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: test_shl_i48_2:
+; RV64:       # %bb.0:
+; RV64-NEXT:    andi a1, a1, 15
+; RV64-NEXT:    sllw a0, a0, a1
+; RV64-NEXT:    ret
+  %and = and i48 %y, 15
+  %shl = shl i48 %x, %and
+  %trunc = trunc i48 %shl to i16
+  ret i16 %trunc
+}