[llvm] [RISCV][MC] Support Assembling 48- and 64-bit Instructions (PR #110022)

[Alex Bradbury via llvm-commits]

================
@@ -426,6 +426,20 @@ line.  This currently applies to the following extensions:
 
 No extensions have experimental intrinsics.
 
+Long (>32-bit) Instruction Support
+==================================
+
+RISC-V is a variable-length ISA, but the standard currently only defines 16- and 32-bit instructions. The specification describes longer instruction encodings, but these are not stable.
----------------
asb wrote:

are not stable => not ratified

We use "ratified" a lot elsewhere in the document, but not "stable" at all so I think it's the better term to use.

https://github.com/llvm/llvm-project/pull/110022