[llvm] [RISCV] Add 32 bit GPR sub-register for Zfinx. (PR #108336)

[Alex Bradbury via llvm-commits]

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@@ -723,9 +772,18 @@ bool llvm::CC_RISCV_GHC(unsigned ValNo, MVT ValVT, MVT LocVT,
     }
   }
 
-  if ((LocVT == MVT::f32 && Subtarget.hasStdExtZfinx()) ||
-      (LocVT == MVT::f64 && Subtarget.hasStdExtZdinx() &&
-       Subtarget.is64Bit())) {
+  if (LocVT == MVT::f32 && Subtarget.hasStdExtZfinx()) {
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asb wrote:

Not really an issue for this review directly, but I wonder if we should be more aggressive about erroring out of the GHC calling convention for more obscure targets that are unlikely to ever need it. Is the ghc cc realistically ever going to be needed on a zfinx/zdinx system?

Change looks fine though.

https://github.com/llvm/llvm-project/pull/108336