[llvm] [RISCV][llvm] Handle `ptr` element type in `lowerDeinterleaveIntrinsicToLoad` and `lowerInterleaveIntrinsicToStore` (PR #107079)

[Craig Topper via llvm-commits]

topperc wrote:

> Apparently this change also fixes a problem with illegal instructions being generated for some RISC-V RVV code which we have observed with llvm 18 and 19. I'm not sure if it is a coincidence or both issues have the same root cause. I've found this commit and PR by bisecting llvm between start of 20th dev cycle and some commit at the main ([10c6d63](https://github.com/llvm/llvm-project/commit/10c6d6349e51bb245b9deec4aafca9885971135b) - [4822e9d](https://github.com/llvm/llvm-project/commit/4822e9dce3483fdec7957cea092384041c8ca013)).
> 
> Our issue was with `vfncvt` instruction being added in the generated code with register overlap (source is a register group of 2 = v8-v9 and destination is a single register v9) which is illegal instruction:
> 
> ```
> vsetvli	a0, zero, e32, m1, ta, ma
> vfncvt.f.f.w	v9, v8
> ```
> 
> I couldn't create small reproducer, so I'm attaching a larger one for completeness: [repro-19.1.0.zip](https://github.com/user-attachments/files/17187374/repro-19.1.0.zip)

I checked out 19.1 and built it. I don't see `vfncvt.f.f.w	v9, v8`. The only `vfncvt.f.f.w` I see is `vfncvt.f.f.w v10, v8`.

https://github.com/llvm/llvm-project/pull/107079