[llvm] [AArch64][GlobalISel] Combine G_EXTRACT_VECTOR_ELT and G_BUILD_VECTOR sequences into G_SHUFFLE_VECTOR (PR #110545)

[via llvm-commits]

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@@ -772,8 +772,6 @@ MachineInstrBuilder MachineIRBuilder::buildShuffleVector(const DstOp &Res,
   LLT DstTy = Res.getLLTTy(*getMRI());
   LLT Src1Ty = Src1.getLLTTy(*getMRI());
   LLT Src2Ty = Src2.getLLTTy(*getMRI());
-  assert((size_t)(Src1Ty.getNumElements() + Src2Ty.getNumElements()) >=
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ValentijnvdBeek wrote:

As outlined in the commit, there are a couple of locations in the AArch64 where this assertion doesn't hold. Therefore, I removed it to bring the build function in line with the real(?) world usage of ShuffleVector.

https://github.com/llvm/llvm-project/blob/5d45815473496db4b041a008e60be17bd78c06ae/llvm/test/CodeGen/AArch64/GlobalISel/combine-shufflevector.mir#L35
https://github.com/llvm/llvm-project/blob/5d45815473496db4b041a008e60be17bd78c06ae/llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir#L285
https://github.com/llvm/llvm-project/blob/5d45815473496db4b041a008e60be17bd78c06ae/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-shuffle-vector.mir#L192

https://github.com/llvm/llvm-project/pull/110545