[llvm] [RISCV] Take known minimum vlen into account when calculating alignment padding in assignRVVStackObjectOffsets. (PR #110312)

[Philip Reames via llvm-commits]

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@@ -65,44 +67,47 @@ define riscv_vector_cc <vscale x 1 x i32> @test_vector_callee_cfi(<vscale x 1 x
 ; NO-OMIT-FP-NEXT:    addi s0, sp, 32
 ; NO-OMIT-FP-NEXT:    .cfi_def_cfa s0, 0
 ; NO-OMIT-FP-NEXT:    csrr a0, vlenb
-; NO-OMIT-FP-NEXT:    slli a0, a0, 3
+; NO-OMIT-FP-NEXT:    slli a1, a0, 3
+; NO-OMIT-FP-NEXT:    sub a0, a1, a0
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preames wrote:

One thought for a possible follow up.  Should we pad the stack in cases where it simplifies our addressing?  I think this might be really complicated to work through the profitable cases, but there's at least a possibility here.  Worth noting is that the "obvious" cases are all covered by ZBA, and thus this might not be worth it on profile compliant hardware.  With ZBA, one case might be 7 registers padded to 8.  With the padding being as far from the base register as possible.

(Having written this, I'm pretty sure this isn't worth bothering with, but throwing it out in case someone is inspired.)

https://github.com/llvm/llvm-project/pull/110312