[llvm] [AMDGPU][GlobalISel] Align `selectVOP3PMadMixModsImpl` with the `SelectionDAG` counterpart (PR #110168)

[Petar Avramovic via llvm-commits]

petar-avramovic wrote:

Hi @shiltian, I did not look into the patch carefully, can you provide LLVM IR test that violates constant bus restriction first.

What I had in mind was that you somehow end up with sgpr register after selectVOP3PMadMixModsImpl

If you want to use existing functions you could
- add it to machine instruction **first** (without checking anything).
- **then** constrain its register class to vgpr.
expected result is that if sgpr was added to instruction, constrainOperandRegClass(...,*VGPRSrc, SrcOp) would replace it by inserting a copy to vgpr.
The constrainSelectedInstRegOperands allows both sgpr and vgpr for that operand. We have to explicitly constrain all operands to vgpr. Other option is to do this in tablegen. End result should be the same.

```
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index febf0711c7d5..9a81e7609dac 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -5356,6 +5356,13 @@ AMDGPUInstructionSelector::selectVOP3PMadMixModsImpl(MachineOperand &Root,
   return {Src, Mods};
 }
 
+MachineOperand &getLastOp(MachineInstrBuilder &MIB) {
+  unsigned Idx = MIB->getNumOperands() - 1;
+  while (MIB->getOperand(Idx).isImplicit())
+    --Idx;
+  return MIB->getOperand(Idx);
+}
+
 InstructionSelector::ComplexRendererFns
 AMDGPUInstructionSelector::selectVOP3PMadMixModsExt(
     MachineOperand &Root) const {
@@ -5367,7 +5374,14 @@ AMDGPUInstructionSelector::selectVOP3PMadMixModsExt(
     return {};
 
   return {{
-      [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); },
+      [=](MachineInstrBuilder &MIB) {
+        MIB.addReg(Src);
+        const TargetRegisterClass *VGPRSrc = &AMDGPU::VGPR_32RegClass;
+        MachineOperand &SrcOp = getLastOp(MIB);
+        constrainOperandRegClass(*MF, TRI, *MRI, TII, RBI, *MIB, *VGPRSrc,
+                                 SrcOp);
+      },
       [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods
   }};
 }
```
I added snippet that I would assume works, but don't have test for it.

https://github.com/llvm/llvm-project/pull/110168