[llvm] 8e0daab - AMDGPU: Make a frame index test more realistic
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 30 02:03:03 PDT 2024
Author: Matt Arsenault
Date: 2024-09-30T13:02:56+04:00
New Revision: 8e0daabe97cf5e73402bcb4c3e54b3583199ba8f
URL: https://github.com/llvm/llvm-project/commit/8e0daabe97cf5e73402bcb4c3e54b3583199ba8f
DIFF: https://github.com/llvm/llvm-project/commit/8e0daabe97cf5e73402bcb4c3e54b3583199ba8f.diff
LOG: AMDGPU: Make a frame index test more realistic
We do not expect to see live carry out outputs on these adds,
so add a dead flag. Split the test for the degenerate case. This
makes it more apparent a regression in a future commit does not matter.
Added:
Modified:
llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32-wave32.mir
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32-wave32.mir b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32-wave32.mir
index 18828bb4618925..2695fdbda87556 100644
--- a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32-wave32.mir
+++ b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32-wave32.mir
@@ -16,10 +16,33 @@ machineFunctionInfo:
body: |
bb.0:
; MUBUFW32-LABEL: name: v_add_co_u32_e64__inline_imm__fi_offset0
- ; MUBUFW32: renamable $vgpr0, $vcc_lo = V_ADD_CO_U32_e64 12, $sgpr32, 0, implicit $exec
+ ; MUBUFW32: renamable $vgpr0, dead $vcc_lo = V_ADD_CO_U32_e64 12, $sgpr32, 0, implicit $exec
; MUBUFW32-NEXT: SI_RETURN implicit $vgpr0, implicit $sgpr0
;
; FLATSCRW32-LABEL: name: v_add_co_u32_e64__inline_imm__fi_offset0
+ ; FLATSCRW32: renamable $vgpr0, dead $vcc_lo = V_ADD_CO_U32_e64 12, $sgpr32, 0, implicit $exec
+ ; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0, implicit $sgpr0
+ renamable $vgpr0, dead $vcc_lo = V_ADD_CO_U32_e64 12, %stack.0, 0, implicit $exec
+ SI_RETURN implicit $vgpr0, implicit $sgpr0
+
+...
+
+---
+name: v_add_co_u32_e64__inline_imm__fi_offset0__live_vcc
+tracksRegLiveness: true
+stack:
+ - { id: 0, size: 4, alignment: 16 }
+machineFunctionInfo:
+ scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
+ frameOffsetReg: '$sgpr33'
+ stackPtrOffsetReg: '$sgpr32'
+body: |
+ bb.0:
+ ; MUBUFW32-LABEL: name: v_add_co_u32_e64__inline_imm__fi_offset0__live_vcc
+ ; MUBUFW32: renamable $vgpr0, $vcc_lo = V_ADD_CO_U32_e64 12, $sgpr32, 0, implicit $exec
+ ; MUBUFW32-NEXT: SI_RETURN implicit $vgpr0, implicit $sgpr0
+ ;
+ ; FLATSCRW32-LABEL: name: v_add_co_u32_e64__inline_imm__fi_offset0__live_vcc
; FLATSCRW32: renamable $vgpr0, $vcc_lo = V_ADD_CO_U32_e64 12, $sgpr32, 0, implicit $exec
; FLATSCRW32-NEXT: SI_RETURN implicit $vgpr0, implicit $sgpr0
renamable $vgpr0, $vcc_lo = V_ADD_CO_U32_e64 12, %stack.0, 0, implicit $exec
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