[lld] c3e4998 - [ELF] Pass Ctx & to TargetInfo. NFC
Fangrui Song via llvm-commits
llvm-commits at lists.llvm.org
Sat Sep 28 21:48:31 PDT 2024
Author: Fangrui Song
Date: 2024-09-28T21:48:26-07:00
New Revision: c3e4998c0b5541e73dfd21e5a0fbda4c93cd8f11
URL: https://github.com/llvm/llvm-project/commit/c3e4998c0b5541e73dfd21e5a0fbda4c93cd8f11
DIFF: https://github.com/llvm/llvm-project/commit/c3e4998c0b5541e73dfd21e5a0fbda4c93cd8f11.diff
LOG: [ELF] Pass Ctx & to TargetInfo. NFC
Added:
Modified:
lld/ELF/Arch/AArch64.cpp
lld/ELF/Arch/AMDGPU.cpp
lld/ELF/Arch/ARM.cpp
lld/ELF/Arch/AVR.cpp
lld/ELF/Arch/Hexagon.cpp
lld/ELF/Arch/LoongArch.cpp
lld/ELF/Arch/MSP430.cpp
lld/ELF/Arch/Mips.cpp
lld/ELF/Arch/PPC.cpp
lld/ELF/Arch/PPC64.cpp
lld/ELF/Arch/RISCV.cpp
lld/ELF/Arch/SPARCV9.cpp
lld/ELF/Arch/SystemZ.cpp
lld/ELF/Arch/X86.cpp
lld/ELF/Arch/X86_64.cpp
lld/ELF/SyntheticSections.cpp
lld/ELF/Target.cpp
lld/ELF/Target.h
lld/ELF/Thunks.cpp
Removed:
################################################################################
diff --git a/lld/ELF/Arch/AArch64.cpp b/lld/ELF/Arch/AArch64.cpp
index d1e2834f1ee2c2..cfea605e2da601 100644
--- a/lld/ELF/Arch/AArch64.cpp
+++ b/lld/ELF/Arch/AArch64.cpp
@@ -31,7 +31,7 @@ uint64_t elf::getAArch64Page(uint64_t expr) {
namespace {
class AArch64 : public TargetInfo {
public:
- AArch64();
+ AArch64(Ctx &);
RelExpr getRelExpr(RelType type, const Symbol &s,
const uint8_t *loc) const override;
RelType getDynRel(RelType type) const override;
@@ -76,7 +76,7 @@ static uint64_t getBits(uint64_t val, int start, int end) {
return (val >> start) & mask;
}
-AArch64::AArch64() {
+AArch64::AArch64(Ctx &ctx) : TargetInfo(ctx) {
copyRel = R_AARCH64_COPY;
relativeRel = R_AARCH64_RELATIVE;
iRelativeRel = R_AARCH64_IRELATIVE;
@@ -960,7 +960,7 @@ void AArch64::relocateAlloc(InputSectionBase &sec, uint8_t *buf) const {
namespace {
class AArch64BtiPac final : public AArch64 {
public:
- AArch64BtiPac();
+ AArch64BtiPac(Ctx &);
void writePltHeader(uint8_t *buf) const override;
void writePlt(uint8_t *buf, const Symbol &sym,
uint64_t pltEntryAddr) const override;
@@ -971,7 +971,7 @@ class AArch64BtiPac final : public AArch64 {
};
} // namespace
-AArch64BtiPac::AArch64BtiPac() {
+AArch64BtiPac::AArch64BtiPac(Ctx &ctx) : AArch64(ctx) {
btiHeader = (ctx.arg.andFeatures & GNU_PROPERTY_AARCH64_FEATURE_1_BTI);
// A BTI (Branch Target Indicator) Plt Entry is only required if the
// address of the PLT entry can be taken by the program, which permits an
@@ -1176,12 +1176,12 @@ void lld::elf::createTaggedSymbols(const SmallVector<ELFFileBase *, 0> &files) {
}
}
-TargetInfo *elf::getAArch64TargetInfo() {
+TargetInfo *elf::getAArch64TargetInfo(Ctx &ctx) {
if ((ctx.arg.andFeatures & GNU_PROPERTY_AARCH64_FEATURE_1_BTI) ||
ctx.arg.zPacPlt) {
- static AArch64BtiPac t;
+ static AArch64BtiPac t(ctx);
return &t;
}
- static AArch64 t;
+ static AArch64 t(ctx);
return &t;
}
diff --git a/lld/ELF/Arch/AMDGPU.cpp b/lld/ELF/Arch/AMDGPU.cpp
index d9440acec9ddad..29b21f1b953989 100644
--- a/lld/ELF/Arch/AMDGPU.cpp
+++ b/lld/ELF/Arch/AMDGPU.cpp
@@ -28,7 +28,7 @@ class AMDGPU final : public TargetInfo {
uint32_t calcEFlagsV6() const;
public:
- AMDGPU();
+ AMDGPU(Ctx &);
uint32_t calcEFlags() const override;
void relocate(uint8_t *loc, const Relocation &rel,
uint64_t val) const override;
@@ -39,7 +39,7 @@ class AMDGPU final : public TargetInfo {
};
} // namespace
-AMDGPU::AMDGPU() {
+AMDGPU::AMDGPU(Ctx &ctx) : TargetInfo(ctx) {
relativeRel = R_AMDGPU_RELATIVE64;
gotRel = R_AMDGPU_ABS64;
symbolicRel = R_AMDGPU_ABS64;
@@ -219,7 +219,7 @@ int64_t AMDGPU::getImplicitAddend(const uint8_t *buf, RelType type) const {
}
}
-TargetInfo *elf::getAMDGPUTargetInfo() {
- static AMDGPU target;
+TargetInfo *elf::getAMDGPUTargetInfo(Ctx &ctx) {
+ static AMDGPU target(ctx);
return ⌖
}
diff --git a/lld/ELF/Arch/ARM.cpp b/lld/ELF/Arch/ARM.cpp
index 29f0b7c71d43c1..93eaf135dc058f 100644
--- a/lld/ELF/Arch/ARM.cpp
+++ b/lld/ELF/Arch/ARM.cpp
@@ -28,7 +28,7 @@ using namespace llvm::object;
namespace {
class ARM final : public TargetInfo {
public:
- ARM();
+ ARM(Ctx &);
uint32_t calcEFlags() const override;
RelExpr getRelExpr(RelType type, const Symbol &s,
const uint8_t *loc) const override;
@@ -54,7 +54,7 @@ enum class CodeState { Data = 0, Thumb = 2, Arm = 4 };
static DenseMap<InputSection *, SmallVector<const Defined *, 0>> sectionMap{};
-ARM::ARM() {
+ARM::ARM(Ctx &ctx) : TargetInfo(ctx) {
copyRel = R_ARM_COPY;
relativeRel = R_ARM_RELATIVE;
iRelativeRel = R_ARM_IRELATIVE;
@@ -1533,8 +1533,8 @@ template <typename ELFT> void elf::writeARMCmseImportLib() {
"': " + toString(std::move(e)));
}
-TargetInfo *elf::getARMTargetInfo() {
- static ARM target;
+TargetInfo *elf::getARMTargetInfo(Ctx &ctx) {
+ static ARM target(ctx);
return ⌖
}
diff --git a/lld/ELF/Arch/AVR.cpp b/lld/ELF/Arch/AVR.cpp
index 2275f869428712..cc2d9fa3daf798 100644
--- a/lld/ELF/Arch/AVR.cpp
+++ b/lld/ELF/Arch/AVR.cpp
@@ -43,7 +43,7 @@ using namespace lld::elf;
namespace {
class AVR final : public TargetInfo {
public:
- AVR() { needsThunks = true; }
+ AVR(Ctx &ctx) : TargetInfo(ctx) { needsThunks = true; }
uint32_t calcEFlags() const override;
RelExpr getRelExpr(RelType type, const Symbol &s,
const uint8_t *loc) const override;
@@ -267,8 +267,8 @@ void AVR::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
}
}
-TargetInfo *elf::getAVRTargetInfo() {
- static AVR target;
+TargetInfo *elf::getAVRTargetInfo(Ctx &ctx) {
+ static AVR target(ctx);
return ⌖
}
diff --git a/lld/ELF/Arch/Hexagon.cpp b/lld/ELF/Arch/Hexagon.cpp
index a492d0a630b46e..d689fc2a152101 100644
--- a/lld/ELF/Arch/Hexagon.cpp
+++ b/lld/ELF/Arch/Hexagon.cpp
@@ -24,7 +24,7 @@ using namespace lld::elf;
namespace {
class Hexagon final : public TargetInfo {
public:
- Hexagon();
+ Hexagon(Ctx &);
uint32_t calcEFlags() const override;
RelExpr getRelExpr(RelType type, const Symbol &s,
const uint8_t *loc) const override;
@@ -38,7 +38,7 @@ class Hexagon final : public TargetInfo {
};
} // namespace
-Hexagon::Hexagon() {
+Hexagon::Hexagon(Ctx &ctx) : TargetInfo(ctx) {
pltRel = R_HEX_JMP_SLOT;
relativeRel = R_HEX_RELATIVE;
gotRel = R_HEX_GLOB_DAT;
@@ -404,7 +404,7 @@ int64_t Hexagon::getImplicitAddend(const uint8_t *buf, RelType type) const {
}
}
-TargetInfo *elf::getHexagonTargetInfo() {
- static Hexagon target;
+TargetInfo *elf::getHexagonTargetInfo(Ctx &ctx) {
+ static Hexagon target(ctx);
return ⌖
}
diff --git a/lld/ELF/Arch/LoongArch.cpp b/lld/ELF/Arch/LoongArch.cpp
index 662dcb2ef3c62f..c195b8eea13c04 100644
--- a/lld/ELF/Arch/LoongArch.cpp
+++ b/lld/ELF/Arch/LoongArch.cpp
@@ -24,7 +24,7 @@ using namespace lld::elf;
namespace {
class LoongArch final : public TargetInfo {
public:
- LoongArch();
+ LoongArch(Ctx &);
uint32_t calcEFlags() const override;
int64_t getImplicitAddend(const uint8_t *buf, RelType type) const override;
void writeGotPlt(uint8_t *buf, const Symbol &s) const override;
@@ -170,7 +170,7 @@ static void handleUleb128(uint8_t *loc, uint64_t val) {
encodeULEB128((orig + val) & mask, loc, count);
}
-LoongArch::LoongArch() {
+LoongArch::LoongArch(Ctx &ctx) : TargetInfo(ctx) {
// The LoongArch ISA itself does not have a limit on page sizes. According to
// the ISA manual, the PS (page size) field in MTLB entries and CSR.STLBPS is
// 6 bits wide, meaning the maximum page size is 2^63 which is equivalent to
@@ -893,7 +893,7 @@ void LoongArch::finalizeRelax(int passes) const {
}
}
-TargetInfo *elf::getLoongArchTargetInfo() {
- static LoongArch target;
+TargetInfo *elf::getLoongArchTargetInfo(Ctx &ctx) {
+ static LoongArch target(ctx);
return ⌖
}
diff --git a/lld/ELF/Arch/MSP430.cpp b/lld/ELF/Arch/MSP430.cpp
index 378b2878d442b9..7563f7cfaa02c6 100644
--- a/lld/ELF/Arch/MSP430.cpp
+++ b/lld/ELF/Arch/MSP430.cpp
@@ -31,7 +31,7 @@ using namespace lld::elf;
namespace {
class MSP430 final : public TargetInfo {
public:
- MSP430();
+ MSP430(Ctx &);
RelExpr getRelExpr(RelType type, const Symbol &s,
const uint8_t *loc) const override;
void relocate(uint8_t *loc, const Relocation &rel,
@@ -39,7 +39,7 @@ class MSP430 final : public TargetInfo {
};
} // namespace
-MSP430::MSP430() {
+MSP430::MSP430(Ctx &ctx) : TargetInfo(ctx) {
// mov.b #0, r3
trapInstr = {0x43, 0x43, 0x43, 0x43};
}
@@ -88,7 +88,7 @@ void MSP430::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
}
}
-TargetInfo *elf::getMSP430TargetInfo() {
- static MSP430 target;
+TargetInfo *elf::getMSP430TargetInfo(Ctx &ctx) {
+ static MSP430 target(ctx);
return ⌖
}
diff --git a/lld/ELF/Arch/Mips.cpp b/lld/ELF/Arch/Mips.cpp
index 8822be5ea8d5b5..0e65df347031ef 100644
--- a/lld/ELF/Arch/Mips.cpp
+++ b/lld/ELF/Arch/Mips.cpp
@@ -23,7 +23,7 @@ using namespace lld::elf;
namespace {
template <class ELFT> class MIPS final : public TargetInfo {
public:
- MIPS();
+ MIPS(Ctx &);
uint32_t calcEFlags() const override;
RelExpr getRelExpr(RelType type, const Symbol &s,
const uint8_t *loc) const override;
@@ -42,7 +42,7 @@ template <class ELFT> class MIPS final : public TargetInfo {
};
} // namespace
-template <class ELFT> MIPS<ELFT>::MIPS() {
+template <class ELFT> MIPS<ELFT>::MIPS(Ctx &ctx) : TargetInfo(ctx) {
gotPltHeaderEntriesNum = 2;
defaultMaxPageSize = 65536;
pltEntrySize = 16;
@@ -778,16 +778,29 @@ template <class ELFT> bool elf::isMipsPIC(const Defined *sym) {
return cast<ObjFile<ELFT>>(file)->getObj().getHeader().e_flags & EF_MIPS_PIC;
}
-template <class ELFT> TargetInfo *elf::getMipsTargetInfo() {
- static MIPS<ELFT> target;
- return ⌖
+TargetInfo *elf::getMipsTargetInfo(Ctx &ctx) {
+ switch (ctx.arg.ekind) {
+ case ELF32LEKind: {
+ static MIPS<ELF32LE> t(ctx);
+ return &t;
+ }
+ case ELF32BEKind: {
+ static MIPS<ELF32BE> t(ctx);
+ return &t;
+ }
+ case ELF64LEKind: {
+ static MIPS<ELF64LE> t(ctx);
+ return &t;
+ }
+ case ELF64BEKind: {
+ static MIPS<ELF64BE> t(ctx);
+ return &t;
+ }
+ default:
+ llvm_unreachable("unsupported target");
+ }
}
-template TargetInfo *elf::getMipsTargetInfo<ELF32LE>();
-template TargetInfo *elf::getMipsTargetInfo<ELF32BE>();
-template TargetInfo *elf::getMipsTargetInfo<ELF64LE>();
-template TargetInfo *elf::getMipsTargetInfo<ELF64BE>();
-
template bool elf::isMipsPIC<ELF32LE>(const Defined *);
template bool elf::isMipsPIC<ELF32BE>(const Defined *);
template bool elf::isMipsPIC<ELF64LE>(const Defined *);
diff --git a/lld/ELF/Arch/PPC.cpp b/lld/ELF/Arch/PPC.cpp
index c5f9de5a2f2a5c..997061cb48d0ba 100644
--- a/lld/ELF/Arch/PPC.cpp
+++ b/lld/ELF/Arch/PPC.cpp
@@ -26,7 +26,7 @@ using namespace lld::elf;
namespace {
class PPC final : public TargetInfo {
public:
- PPC();
+ PPC(Ctx &);
RelExpr getRelExpr(RelType type, const Symbol &s,
const uint8_t *loc) const override;
RelType getDynRel(RelType type) const override;
@@ -152,7 +152,7 @@ void elf::writePPC32GlinkSection(uint8_t *buf, size_t numEntries) {
write32(buf, 0x60000000);
}
-PPC::PPC() {
+PPC::PPC(Ctx &ctx) : TargetInfo(ctx) {
copyRel = R_PPC_COPY;
gotRel = R_PPC_GLOB_DAT;
pltRel = R_PPC_JMP_SLOT;
@@ -525,7 +525,7 @@ void PPC::relocateAlloc(InputSectionBase &sec, uint8_t *buf) const {
}
}
-TargetInfo *elf::getPPCTargetInfo() {
- static PPC target;
+TargetInfo *elf::getPPCTargetInfo(Ctx &ctx) {
+ static PPC target(ctx);
return ⌖
}
diff --git a/lld/ELF/Arch/PPC64.cpp b/lld/ELF/Arch/PPC64.cpp
index fdf3d07b98bca1..da2a5aeed43b06 100644
--- a/lld/ELF/Arch/PPC64.cpp
+++ b/lld/ELF/Arch/PPC64.cpp
@@ -168,7 +168,7 @@ enum class LegacyToPrefixMask : uint64_t {
class PPC64 final : public TargetInfo {
public:
- PPC64();
+ PPC64(Ctx &);
int getTlsGdRelaxSkip(RelType type) const override;
uint32_t calcEFlags() const override;
RelExpr getRelExpr(RelType type, const Symbol &s,
@@ -578,7 +578,7 @@ static uint64_t readPrefixedInstruction(const uint8_t *loc) {
return ctx.arg.isLE ? (fullInstr << 32 | fullInstr >> 32) : fullInstr;
}
-PPC64::PPC64() {
+PPC64::PPC64(Ctx &ctx) : TargetInfo(ctx) {
copyRel = R_PPC64_COPY;
gotRel = R_PPC64_GLOB_DAT;
pltRel = R_PPC64_JMP_SLOT;
@@ -1750,7 +1750,7 @@ bool PPC64::adjustPrologueForCrossSplitStack(uint8_t *loc, uint8_t *end,
return true;
}
-TargetInfo *elf::getPPC64TargetInfo() {
- static PPC64 target;
+TargetInfo *elf::getPPC64TargetInfo(Ctx &ctx) {
+ static PPC64 target(ctx);
return ⌖
}
diff --git a/lld/ELF/Arch/RISCV.cpp b/lld/ELF/Arch/RISCV.cpp
index 4b02612bec870f..8a4ccc567e5fac 100644
--- a/lld/ELF/Arch/RISCV.cpp
+++ b/lld/ELF/Arch/RISCV.cpp
@@ -29,7 +29,7 @@ namespace {
class RISCV final : public TargetInfo {
public:
- RISCV();
+ RISCV(Ctx &);
uint32_t calcEFlags() const override;
int64_t getImplicitAddend(const uint8_t *buf, RelType type) const override;
void writeGotHeader(uint8_t *buf) const override;
@@ -107,7 +107,7 @@ static uint32_t setLO12_S(uint32_t insn, uint32_t imm) {
(extractBits(imm, 4, 0) << 7);
}
-RISCV::RISCV() {
+RISCV::RISCV(Ctx &ctx) : TargetInfo(ctx) {
copyRel = R_RISCV_COPY;
pltRel = R_RISCV_JUMP_SLOT;
relativeRel = R_RISCV_RELATIVE;
@@ -1328,7 +1328,7 @@ void elf::mergeRISCVAttributesSections() {
mergeAttributesSection(sections));
}
-TargetInfo *elf::getRISCVTargetInfo() {
- static RISCV target;
+TargetInfo *elf::getRISCVTargetInfo(Ctx &ctx) {
+ static RISCV target(ctx);
return ⌖
}
diff --git a/lld/ELF/Arch/SPARCV9.cpp b/lld/ELF/Arch/SPARCV9.cpp
index f7f296c81f335d..15c7c9c28b2ed8 100644
--- a/lld/ELF/Arch/SPARCV9.cpp
+++ b/lld/ELF/Arch/SPARCV9.cpp
@@ -21,7 +21,7 @@ using namespace lld::elf;
namespace {
class SPARCV9 final : public TargetInfo {
public:
- SPARCV9();
+ SPARCV9(Ctx &);
RelExpr getRelExpr(RelType type, const Symbol &s,
const uint8_t *loc) const override;
void writePlt(uint8_t *buf, const Symbol &sym,
@@ -31,7 +31,7 @@ class SPARCV9 final : public TargetInfo {
};
} // namespace
-SPARCV9::SPARCV9() {
+SPARCV9::SPARCV9(Ctx &ctx) : TargetInfo(ctx) {
copyRel = R_SPARC_COPY;
gotRel = R_SPARC_GLOB_DAT;
pltRel = R_SPARC_JMP_SLOT;
@@ -193,7 +193,7 @@ void SPARCV9::writePlt(uint8_t *buf, const Symbol & /*sym*/,
relocateNoSym(buf + 4, R_SPARC_WDISP19, -(off + 4 - pltEntrySize));
}
-TargetInfo *elf::getSPARCV9TargetInfo() {
- static SPARCV9 target;
+TargetInfo *elf::getSPARCV9TargetInfo(Ctx &ctx) {
+ static SPARCV9 target(ctx);
return ⌖
}
diff --git a/lld/ELF/Arch/SystemZ.cpp b/lld/ELF/Arch/SystemZ.cpp
index 1ffc3c54ee0e95..fc87103165fd4d 100644
--- a/lld/ELF/Arch/SystemZ.cpp
+++ b/lld/ELF/Arch/SystemZ.cpp
@@ -23,7 +23,7 @@ using namespace lld::elf;
namespace {
class SystemZ : public TargetInfo {
public:
- SystemZ();
+ SystemZ(Ctx &);
int getTlsGdRelaxSkip(RelType type) const override;
RelExpr getRelExpr(RelType type, const Symbol &s,
const uint8_t *loc) const override;
@@ -51,7 +51,7 @@ class SystemZ : public TargetInfo {
};
} // namespace
-SystemZ::SystemZ() {
+SystemZ::SystemZ(Ctx &ctx) : TargetInfo(ctx) {
copyRel = R_390_COPY;
gotRel = R_390_GLOB_DAT;
pltRel = R_390_JMP_SLOT;
@@ -601,7 +601,7 @@ void SystemZ::relocate(uint8_t *loc, const Relocation &rel,
}
}
-TargetInfo *elf::getSystemZTargetInfo() {
- static SystemZ t;
+TargetInfo *elf::getSystemZTargetInfo(Ctx &ctx) {
+ static SystemZ t(ctx);
return &t;
}
diff --git a/lld/ELF/Arch/X86.cpp b/lld/ELF/Arch/X86.cpp
index e02038b1689c49..0a16ca24fcb318 100644
--- a/lld/ELF/Arch/X86.cpp
+++ b/lld/ELF/Arch/X86.cpp
@@ -22,7 +22,7 @@ using namespace lld::elf;
namespace {
class X86 : public TargetInfo {
public:
- X86();
+ X86(Ctx &);
int getTlsGdRelaxSkip(RelType type) const override;
RelExpr getRelExpr(RelType type, const Symbol &s,
const uint8_t *loc) const override;
@@ -42,7 +42,7 @@ class X86 : public TargetInfo {
};
} // namespace
-X86::X86() {
+X86::X86(Ctx &ctx) : TargetInfo(ctx) {
copyRel = R_386_COPY;
gotRel = R_386_GLOB_DAT;
pltRel = R_386_JUMP_SLOT;
@@ -518,7 +518,7 @@ void X86::relocateAlloc(InputSectionBase &sec, uint8_t *buf) const {
namespace {
class IntelIBT : public X86 {
public:
- IntelIBT();
+ IntelIBT(Ctx &ctx) : X86(ctx) { pltHeaderSize = 0; }
void writeGotPlt(uint8_t *buf, const Symbol &s) const override;
void writePlt(uint8_t *buf, const Symbol &sym,
uint64_t pltEntryAddr) const override;
@@ -528,8 +528,6 @@ class IntelIBT : public X86 {
};
} // namespace
-IntelIBT::IntelIBT() { pltHeaderSize = 0; }
-
void IntelIBT::writeGotPlt(uint8_t *buf, const Symbol &s) const {
uint64_t va =
ctx.in.ibtPlt->getVA() + IBTPltHeaderSize + s.getPltIdx() * pltEntrySize;
@@ -580,7 +578,7 @@ void IntelIBT::writeIBTPlt(uint8_t *buf, size_t numEntries) const {
namespace {
class RetpolinePic : public X86 {
public:
- RetpolinePic();
+ RetpolinePic(Ctx &);
void writeGotPlt(uint8_t *buf, const Symbol &s) const override;
void writePltHeader(uint8_t *buf) const override;
void writePlt(uint8_t *buf, const Symbol &sym,
@@ -589,7 +587,7 @@ class RetpolinePic : public X86 {
class RetpolineNoPic : public X86 {
public:
- RetpolineNoPic();
+ RetpolineNoPic(Ctx &);
void writeGotPlt(uint8_t *buf, const Symbol &s) const override;
void writePltHeader(uint8_t *buf) const override;
void writePlt(uint8_t *buf, const Symbol &sym,
@@ -597,7 +595,7 @@ class RetpolineNoPic : public X86 {
};
} // namespace
-RetpolinePic::RetpolinePic() {
+RetpolinePic::RetpolinePic(Ctx &ctx) : X86(ctx) {
pltHeaderSize = 48;
pltEntrySize = 32;
ipltEntrySize = 32;
@@ -651,7 +649,7 @@ void RetpolinePic::writePlt(uint8_t *buf, const Symbol &sym,
write32le(buf + 23, -off - 27);
}
-RetpolineNoPic::RetpolineNoPic() {
+RetpolineNoPic::RetpolineNoPic(Ctx &ctx) : X86(ctx) {
pltHeaderSize = 48;
pltEntrySize = 32;
ipltEntrySize = 32;
@@ -710,21 +708,21 @@ void RetpolineNoPic::writePlt(uint8_t *buf, const Symbol &sym,
write32le(buf + 22, -off - 26);
}
-TargetInfo *elf::getX86TargetInfo() {
+TargetInfo *elf::getX86TargetInfo(Ctx &ctx) {
if (ctx.arg.zRetpolineplt) {
if (ctx.arg.isPic) {
- static RetpolinePic t;
+ static RetpolinePic t(ctx);
return &t;
}
- static RetpolineNoPic t;
+ static RetpolineNoPic t(ctx);
return &t;
}
if (ctx.arg.andFeatures & GNU_PROPERTY_X86_FEATURE_1_IBT) {
- static IntelIBT t;
+ static IntelIBT t(ctx);
return &t;
}
- static X86 t;
+ static X86 t(ctx);
return &t;
}
diff --git a/lld/ELF/Arch/X86_64.cpp b/lld/ELF/Arch/X86_64.cpp
index 6e13333edb8e41..9b07946a79525c 100644
--- a/lld/ELF/Arch/X86_64.cpp
+++ b/lld/ELF/Arch/X86_64.cpp
@@ -26,7 +26,7 @@ using namespace lld::elf;
namespace {
class X86_64 : public TargetInfo {
public:
- X86_64();
+ X86_64(Ctx &);
int getTlsGdRelaxSkip(RelType type) const override;
RelExpr getRelExpr(RelType type, const Symbol &s,
const uint8_t *loc) const override;
@@ -67,7 +67,7 @@ static const std::vector<std::vector<uint8_t>> nopInstructions = {
{0x0F, 0x1F, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
{0x66, 0x0F, 0x1F, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00}};
-X86_64::X86_64() {
+X86_64::X86_64(Ctx &ctx) : TargetInfo(ctx) {
copyRel = R_X86_64_COPY;
gotRel = R_X86_64_GLOB_DAT;
pltRel = R_X86_64_JUMP_SLOT;
@@ -1059,7 +1059,7 @@ void X86_64::relocateAlloc(InputSectionBase &sec, uint8_t *buf) const {
namespace {
class IntelIBT : public X86_64 {
public:
- IntelIBT();
+ IntelIBT(Ctx &ctx) : X86_64(ctx) { pltHeaderSize = 0; };
void writeGotPlt(uint8_t *buf, const Symbol &s) const override;
void writePlt(uint8_t *buf, const Symbol &sym,
uint64_t pltEntryAddr) const override;
@@ -1069,8 +1069,6 @@ class IntelIBT : public X86_64 {
};
} // namespace
-IntelIBT::IntelIBT() { pltHeaderSize = 0; }
-
void IntelIBT::writeGotPlt(uint8_t *buf, const Symbol &s) const {
uint64_t va =
ctx.in.ibtPlt->getVA() + IBTPltHeaderSize + s.getPltIdx() * pltEntrySize;
@@ -1119,7 +1117,7 @@ void IntelIBT::writeIBTPlt(uint8_t *buf, size_t numEntries) const {
namespace {
class Retpoline : public X86_64 {
public:
- Retpoline();
+ Retpoline(Ctx &);
void writeGotPlt(uint8_t *buf, const Symbol &s) const override;
void writePltHeader(uint8_t *buf) const override;
void writePlt(uint8_t *buf, const Symbol &sym,
@@ -1128,7 +1126,7 @@ class Retpoline : public X86_64 {
class RetpolineZNow : public X86_64 {
public:
- RetpolineZNow();
+ RetpolineZNow(Ctx &);
void writeGotPlt(uint8_t *buf, const Symbol &s) const override {}
void writePltHeader(uint8_t *buf) const override;
void writePlt(uint8_t *buf, const Symbol &sym,
@@ -1136,7 +1134,7 @@ class RetpolineZNow : public X86_64 {
};
} // namespace
-Retpoline::Retpoline() {
+Retpoline::Retpoline(Ctx &ctx) : X86_64(ctx) {
pltHeaderSize = 48;
pltEntrySize = 32;
ipltEntrySize = 32;
@@ -1189,7 +1187,7 @@ void Retpoline::writePlt(uint8_t *buf, const Symbol &sym,
write32le(buf + 23, -off - 27);
}
-RetpolineZNow::RetpolineZNow() {
+RetpolineZNow::RetpolineZNow(Ctx &ctx) : X86_64(ctx) {
pltHeaderSize = 32;
pltEntrySize = 16;
ipltEntrySize = 16;
@@ -1224,21 +1222,21 @@ void RetpolineZNow::writePlt(uint8_t *buf, const Symbol &sym,
write32le(buf + 8, ctx.in.plt->getVA() - pltEntryAddr - 12);
}
-TargetInfo *elf::getX86_64TargetInfo() {
+TargetInfo *elf::getX86_64TargetInfo(Ctx &ctx) {
if (ctx.arg.zRetpolineplt) {
if (ctx.arg.zNow) {
- static RetpolineZNow t;
+ static RetpolineZNow t(ctx);
return &t;
}
- static Retpoline t;
+ static Retpoline t(ctx);
return &t;
}
if (ctx.arg.andFeatures & GNU_PROPERTY_X86_FEATURE_1_IBT) {
- static IntelIBT t;
+ static IntelIBT t(ctx);
return &t;
}
- static X86_64 t;
+ static X86_64 t(ctx);
return &t;
}
diff --git a/lld/ELF/SyntheticSections.cpp b/lld/ELF/SyntheticSections.cpp
index ce31c379ab1829..4d83a722231e64 100644
--- a/lld/ELF/SyntheticSections.cpp
+++ b/lld/ELF/SyntheticSections.cpp
@@ -1568,7 +1568,7 @@ DynamicSection<ELFT>::computeContents() {
}
if (ctx.arg.emachine == EM_PPC64)
- addInt(DT_PPC64_OPT, getPPC64TargetInfo()->ppc64DynamicSectionOpt);
+ addInt(DT_PPC64_OPT, getPPC64TargetInfo(ctx)->ppc64DynamicSectionOpt);
addInt(DT_NULL, 0);
return entries;
diff --git a/lld/ELF/Target.cpp b/lld/ELF/Target.cpp
index ea8dc98e9a2e73..d5d11b9549e03f 100644
--- a/lld/ELF/Target.cpp
+++ b/lld/ELF/Target.cpp
@@ -49,46 +49,35 @@ TargetInfo *elf::getTarget(Ctx &ctx) {
switch (ctx.arg.emachine) {
case EM_386:
case EM_IAMCU:
- return getX86TargetInfo();
+ return getX86TargetInfo(ctx);
case EM_AARCH64:
- return getAArch64TargetInfo();
+ return getAArch64TargetInfo(ctx);
case EM_AMDGPU:
- return getAMDGPUTargetInfo();
+ return getAMDGPUTargetInfo(ctx);
case EM_ARM:
- return getARMTargetInfo();
+ return getARMTargetInfo(ctx);
case EM_AVR:
- return getAVRTargetInfo();
+ return getAVRTargetInfo(ctx);
case EM_HEXAGON:
- return getHexagonTargetInfo();
+ return getHexagonTargetInfo(ctx);
case EM_LOONGARCH:
- return getLoongArchTargetInfo();
+ return getLoongArchTargetInfo(ctx);
case EM_MIPS:
- switch (ctx.arg.ekind) {
- case ELF32LEKind:
- return getMipsTargetInfo<ELF32LE>();
- case ELF32BEKind:
- return getMipsTargetInfo<ELF32BE>();
- case ELF64LEKind:
- return getMipsTargetInfo<ELF64LE>();
- case ELF64BEKind:
- return getMipsTargetInfo<ELF64BE>();
- default:
- llvm_unreachable("unsupported MIPS target");
- }
+ return getMipsTargetInfo(ctx);
case EM_MSP430:
- return getMSP430TargetInfo();
+ return getMSP430TargetInfo(ctx);
case EM_PPC:
- return getPPCTargetInfo();
+ return getPPCTargetInfo(ctx);
case EM_PPC64:
- return getPPC64TargetInfo();
+ return getPPC64TargetInfo(ctx);
case EM_RISCV:
- return getRISCVTargetInfo();
+ return getRISCVTargetInfo(ctx);
case EM_SPARCV9:
- return getSPARCV9TargetInfo();
+ return getSPARCV9TargetInfo(ctx);
case EM_S390:
- return getSystemZTargetInfo();
+ return getSystemZTargetInfo(ctx);
case EM_X86_64:
- return getX86_64TargetInfo();
+ return getX86_64TargetInfo(ctx);
default:
fatal("unsupported e_machine value: " + Twine(ctx.arg.emachine));
}
diff --git a/lld/ELF/Target.h b/lld/ELF/Target.h
index 951b2f36fdda93..648d0c3fe9eb28 100644
--- a/lld/ELF/Target.h
+++ b/lld/ELF/Target.h
@@ -29,6 +29,7 @@ class Symbol;
class TargetInfo {
public:
+ TargetInfo(Ctx &ctx) : ctx(ctx) {}
virtual uint32_t calcEFlags() const { return 0; }
virtual RelExpr getRelExpr(RelType type, const Symbol &s,
const uint8_t *loc) const = 0;
@@ -113,6 +114,7 @@ class TargetInfo {
return false;
}
+ Ctx &ctx;
unsigned defaultCommonPageSize = 4096;
unsigned defaultMaxPageSize = 4096;
@@ -177,21 +179,21 @@ class TargetInfo {
uint64_t defaultImageBase = 0x10000;
};
-TargetInfo *getAArch64TargetInfo();
-TargetInfo *getAMDGPUTargetInfo();
-TargetInfo *getARMTargetInfo();
-TargetInfo *getAVRTargetInfo();
-TargetInfo *getHexagonTargetInfo();
-TargetInfo *getLoongArchTargetInfo();
-TargetInfo *getMSP430TargetInfo();
-TargetInfo *getPPC64TargetInfo();
-TargetInfo *getPPCTargetInfo();
-TargetInfo *getRISCVTargetInfo();
-TargetInfo *getSPARCV9TargetInfo();
-TargetInfo *getSystemZTargetInfo();
-TargetInfo *getX86TargetInfo();
-TargetInfo *getX86_64TargetInfo();
-template <class ELFT> TargetInfo *getMipsTargetInfo();
+TargetInfo *getAArch64TargetInfo(Ctx &);
+TargetInfo *getAMDGPUTargetInfo(Ctx &);
+TargetInfo *getARMTargetInfo(Ctx &);
+TargetInfo *getAVRTargetInfo(Ctx &);
+TargetInfo *getHexagonTargetInfo(Ctx &);
+TargetInfo *getLoongArchTargetInfo(Ctx &);
+TargetInfo *getMSP430TargetInfo(Ctx &);
+TargetInfo *getMipsTargetInfo(Ctx &);
+TargetInfo *getPPC64TargetInfo(Ctx &);
+TargetInfo *getPPCTargetInfo(Ctx &);
+TargetInfo *getRISCVTargetInfo(Ctx &);
+TargetInfo *getSPARCV9TargetInfo(Ctx &);
+TargetInfo *getSystemZTargetInfo(Ctx &);
+TargetInfo *getX86TargetInfo(Ctx &);
+TargetInfo *getX86_64TargetInfo(Ctx &);
struct ErrorPlace {
InputSectionBase *isec;
@@ -241,7 +243,7 @@ void convertArmInstructionstoBE8(InputSection *sec, uint8_t *buf);
void createTaggedSymbols(const SmallVector<ELFFileBase *, 0> &files);
void initSymbolAnchors();
-TargetInfo *getTarget(Ctx &ctx);
+TargetInfo *getTarget(Ctx &);
template <class ELFT> bool isMipsPIC(const Defined *sym);
diff --git a/lld/ELF/Thunks.cpp b/lld/ELF/Thunks.cpp
index 4ac651ba1ad66f..5b9263021b9ed7 100644
--- a/lld/ELF/Thunks.cpp
+++ b/lld/ELF/Thunks.cpp
@@ -1438,7 +1438,7 @@ static Thunk *addThunkPPC64(RelType type, Symbol &s, int64_t a) {
// If we are emitting stubs for NOTOC relocations, we need to tell
// the PLT resolver that there can be multiple TOCs.
if (type == R_PPC64_REL24_NOTOC)
- getPPC64TargetInfo()->ppc64DynamicSectionOpt = 0x2;
+ getPPC64TargetInfo(ctx)->ppc64DynamicSectionOpt = 0x2;
if (s.isInPlt())
return type == R_PPC64_REL24_NOTOC
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