[llvm] 6b81357 - [Hexagon] Use MCRegister. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat Sep 28 11:41:08 PDT 2024
Author: Craig Topper
Date: 2024-09-28T11:40:26-07:00
New Revision: 6b8135762cf77028499819464cf769f222297da4
URL: https://github.com/llvm/llvm-project/commit/6b8135762cf77028499819464cf769f222297da4
DIFF: https://github.com/llvm/llvm-project/commit/6b8135762cf77028499819464cf769f222297da4.diff
LOG: [Hexagon] Use MCRegister. NFC
Added:
Modified:
llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCompound.cpp
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h
Removed:
################################################################################
diff --git a/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp b/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
index 62f188957cccf5..e2157f1593e90e 100644
--- a/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
+++ b/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
@@ -124,7 +124,7 @@ class HexagonAsmParser : public MCTargetAsmParser {
bool parseDirectiveAttribute(SMLoc L);
- bool RegisterMatchesArch(unsigned MatchNum) const;
+ bool RegisterMatchesArch(MCRegister MatchNum) const;
bool matchBundleOptions();
bool handleNoncontigiousRegister(bool Contigious, SMLoc &Loc);
@@ -145,10 +145,10 @@ class HexagonAsmParser : public MCTargetAsmParser {
int processInstruction(MCInst &Inst, OperandVector const &Operands,
SMLoc IDLoc);
- unsigned matchRegister(StringRef Name);
+ MCRegister matchRegister(StringRef Name);
-/// @name Auto-generated Match Functions
-/// {
+ /// @name Auto-generated Match Functions
+ /// {
#define GET_ASSEMBLER_HEADER
#include "HexagonGenAsmMatcher.inc"
@@ -205,7 +205,7 @@ struct HexagonOperand : public MCParsedAsmOperand {
};
struct RegTy {
- unsigned RegNum;
+ MCRegister RegNum;
};
struct ImmTy {
@@ -434,9 +434,9 @@ struct HexagonOperand : public MCParsedAsmOperand {
}
static std::unique_ptr<HexagonOperand>
- CreateReg(MCContext &Context, unsigned RegNum, SMLoc S, SMLoc E) {
+ CreateReg(MCContext &Context, MCRegister Reg, SMLoc S, SMLoc E) {
HexagonOperand *Op = new HexagonOperand(Register, Context);
- Op->Reg.RegNum = RegNum;
+ Op->Reg.RegNum = Reg;
Op->StartLoc = S;
Op->EndLoc = E;
return std::unique_ptr<HexagonOperand>(Op);
@@ -867,7 +867,7 @@ bool HexagonAsmParser::ParseDirectiveComm(bool IsLocal, SMLoc Loc) {
}
// validate register against architecture
-bool HexagonAsmParser::RegisterMatchesArch(unsigned MatchNum) const {
+bool HexagonAsmParser::RegisterMatchesArch(MCRegister MatchNum) const {
if (HexagonMCRegisterClasses[Hexagon::V62RegsRegClassID].contains(MatchNum))
if (!getSTI().hasFeature(Hexagon::ArchV62))
return false;
@@ -929,7 +929,7 @@ bool HexagonAsmParser::parseOperand(OperandVector &Operands) {
MCAsmLexer &Lexer = getLexer();
if (!parseRegister(Register, Begin, End)) {
if (!ErrorMissingParenthesis)
- switch (Register) {
+ switch (Register.id()) {
default:
break;
case Hexagon::P0:
@@ -1054,8 +1054,8 @@ ParseStatus HexagonAsmParser::tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
llvm::erase_if(Collapsed, isSpace);
StringRef FullString = Collapsed;
std::pair<StringRef, StringRef> DotSplit = FullString.split('.');
- unsigned DotReg = matchRegister(DotSplit.first.lower());
- if (DotReg != Hexagon::NoRegister && RegisterMatchesArch(DotReg)) {
+ MCRegister DotReg = matchRegister(DotSplit.first.lower());
+ if (DotReg && RegisterMatchesArch(DotReg)) {
if (DotSplit.second.empty()) {
Reg = DotReg;
EndLoc = Lexer.getLoc();
@@ -1074,8 +1074,8 @@ ParseStatus HexagonAsmParser::tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
}
}
std::pair<StringRef, StringRef> ColonSplit = StringRef(FullString).split(':');
- unsigned ColonReg = matchRegister(ColonSplit.first.lower());
- if (ColonReg != Hexagon::NoRegister && RegisterMatchesArch(DotReg)) {
+ MCRegister ColonReg = matchRegister(ColonSplit.first.lower());
+ if (ColonReg && RegisterMatchesArch(DotReg)) {
do {
Lexer.UnLex(Lookahead.pop_back_val());
} while (!Lookahead.empty() && !Lexer.is(AsmToken::Colon));
@@ -1358,13 +1358,13 @@ int HexagonAsmParser::processInstruction(MCInst &Inst,
return std::make_pair(matchRegister(R1), matchRegister(R2));
};
- auto GetScalarRegs = [RI, GetRegPair](unsigned RegPair) {
+ auto GetScalarRegs = [RI, GetRegPair](MCRegister RegPair) {
const unsigned Lower = RI->getEncodingValue(RegPair);
const RegPairVals RegPair_ = std::make_pair(Lower + 1, Lower);
return GetRegPair(RegPair_);
};
- auto GetVecRegs = [GetRegPair](unsigned VecRegPair) {
+ auto GetVecRegs = [GetRegPair](MCRegister VecRegPair) {
const RegPairVals RegPair =
HexagonMCInstrInfo::GetVecRegPairIndices(VecRegPair);
@@ -1461,7 +1461,8 @@ int HexagonAsmParser::processInstruction(MCInst &Inst,
// Translate a "$Rdd = $Rss" to "$Rdd = combine($Rs, $Rt)"
case Hexagon::A2_tfrp: {
MCOperand &MO = Inst.getOperand(1);
- const std::pair<unsigned, unsigned> RegPair = GetScalarRegs(MO.getReg());
+ const std::pair<MCRegister, MCRegister> RegPair =
+ GetScalarRegs(MO.getReg());
MO.setReg(RegPair.first);
Inst.addOperand(MCOperand::createReg(RegPair.second));
Inst.setOpcode(Hexagon::A2_combinew);
@@ -1471,7 +1472,8 @@ int HexagonAsmParser::processInstruction(MCInst &Inst,
case Hexagon::A2_tfrpt:
case Hexagon::A2_tfrpf: {
MCOperand &MO = Inst.getOperand(2);
- const std::pair<unsigned, unsigned> RegPair = GetScalarRegs(MO.getReg());
+ const std::pair<MCRegister, MCRegister> RegPair =
+ GetScalarRegs(MO.getReg());
MO.setReg(RegPair.first);
Inst.addOperand(MCOperand::createReg(RegPair.second));
Inst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrpt)
@@ -1482,7 +1484,8 @@ int HexagonAsmParser::processInstruction(MCInst &Inst,
case Hexagon::A2_tfrptnew:
case Hexagon::A2_tfrpfnew: {
MCOperand &MO = Inst.getOperand(2);
- const std::pair<unsigned, unsigned> RegPair = GetScalarRegs(MO.getReg());
+ const std::pair<MCRegister, MCRegister> RegPair =
+ GetScalarRegs(MO.getReg());
MO.setReg(RegPair.first);
Inst.addOperand(MCOperand::createReg(RegPair.second));
Inst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrptnew)
@@ -1494,7 +1497,7 @@ int HexagonAsmParser::processInstruction(MCInst &Inst,
// Translate a "$Vdd = $Vss" to "$Vdd = vcombine($Vs, $Vt)"
case Hexagon::V6_vassignp: {
MCOperand &MO = Inst.getOperand(1);
- const std::pair<unsigned, unsigned> RegPair = GetVecRegs(MO.getReg());
+ const std::pair<MCRegister, MCRegister> RegPair = GetVecRegs(MO.getReg());
MO.setReg(RegPair.first);
Inst.addOperand(MCOperand::createReg(RegPair.second));
Inst.setOpcode(Hexagon::V6_vcombine);
@@ -2051,8 +2054,8 @@ int HexagonAsmParser::processInstruction(MCInst &Inst,
return Match_Success;
}
-unsigned HexagonAsmParser::matchRegister(StringRef Name) {
- if (unsigned Reg = MatchRegisterName(Name))
+MCRegister HexagonAsmParser::matchRegister(StringRef Name) {
+ if (MCRegister Reg = MatchRegisterName(Name))
return Reg;
return MatchRegisterAltName(Name);
}
diff --git a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
index 44a5cd73c6e89f..231004f6c1dc0d 100644
--- a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
+++ b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
@@ -499,13 +499,14 @@ DecodeStatus HexagonDisassembler::getSingleInstruction(MCInst &MI, MCInst &MCB,
bool SubregBit = (Register & 0x1) != 0;
if (HexagonMCInstrInfo::hasNewValue2(*MCII, Inst)) {
// If subreg bit is set we're selecting the second produced newvalue
- unsigned Producer = SubregBit ?
- HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg() :
- HexagonMCInstrInfo::getNewValueOperand2(*MCII, Inst).getReg();
+ MCRegister Producer =
+ SubregBit
+ ? HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg()
+ : HexagonMCInstrInfo::getNewValueOperand2(*MCII, Inst).getReg();
assert(Producer != Hexagon::NoRegister);
MCO.setReg(Producer);
} else if (HexagonMCInstrInfo::hasNewValue(*MCII, Inst)) {
- unsigned Producer =
+ MCRegister Producer =
HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg();
if (HexagonMCInstrInfo::IsVecRegPair(Producer)) {
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp
index ef4c23df54121f..9b6bc5ade379d6 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp
@@ -65,8 +65,8 @@ void HexagonMCChecker::init() {
init(MCB);
}
-void HexagonMCChecker::initReg(MCInst const &MCI, unsigned R, unsigned &PredReg,
- bool &isTrue) {
+void HexagonMCChecker::initReg(MCInst const &MCI, MCRegister R,
+ MCRegister &PredReg, bool &isTrue) {
if (HexagonMCInstrInfo::isPredicated(MCII, MCI) &&
HexagonMCInstrInfo::isPredReg(RI, R)) {
// Note an used predicate register.
@@ -91,7 +91,7 @@ void HexagonMCChecker::initReg(MCInst const &MCI, unsigned R, unsigned &PredReg,
void HexagonMCChecker::init(MCInst const &MCI) {
const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MCI);
- unsigned PredReg = Hexagon::NoRegister;
+ MCRegister PredReg;
bool isTrue = false;
// Get used registers.
@@ -133,7 +133,7 @@ void HexagonMCChecker::init(MCInst const &MCI) {
// Figure out explicit register definitions.
for (unsigned i = 0; i < MCID.getNumDefs(); ++i) {
- unsigned R = MCI.getOperand(i).getReg(), S = Hexagon::NoRegister;
+ MCRegister R = MCI.getOperand(i).getReg(), S = MCRegister();
// USR has subregisters (while C8 does not for technical reasons), so
// reset R to USR, since we know how to handle multiple defs of USR,
// taking into account its subregisters.
@@ -187,7 +187,7 @@ void HexagonMCChecker::init(MCInst const &MCI) {
if (HexagonMCInstrInfo::isPredicatedNew(MCII, MCI))
for (unsigned i = MCID.getNumDefs(); i < MCID.getNumOperands(); ++i)
if (MCI.getOperand(i).isReg()) {
- unsigned P = MCI.getOperand(i).getReg();
+ MCRegister P = MCI.getOperand(i).getReg();
if (HexagonMCInstrInfo::isPredReg(RI, P))
NewPreds.insert(P);
@@ -531,7 +531,7 @@ bool HexagonMCChecker::checkRegistersReadOnly() {
for (unsigned j = 0; j < Defs; ++j) {
MCOperand const &Operand = Inst.getOperand(j);
assert(Operand.isReg() && "Def is not a register");
- unsigned Register = Operand.getReg();
+ MCRegister Register = Operand.getReg();
if (ReadOnly.find(Register) != ReadOnly.end()) {
reportError(Inst.getLoc(), "Cannot write to read-only register `" +
Twine(RI.getName(Register)) + "'");
@@ -542,7 +542,7 @@ bool HexagonMCChecker::checkRegistersReadOnly() {
return true;
}
-bool HexagonMCChecker::registerUsed(unsigned Register) {
+bool HexagonMCChecker::registerUsed(MCRegister Register) {
for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB))
for (unsigned j = HexagonMCInstrInfo::getDesc(MCII, I).getNumDefs(),
n = I.getNumOperands();
@@ -556,7 +556,7 @@ bool HexagonMCChecker::registerUsed(unsigned Register) {
std::tuple<MCInst const *, unsigned, HexagonMCInstrInfo::PredicateInfo>
HexagonMCChecker::registerProducer(
- unsigned Register, HexagonMCInstrInfo::PredicateInfo ConsumerPredicate) {
+ MCRegister Register, HexagonMCInstrInfo::PredicateInfo ConsumerPredicate) {
std::tuple<MCInst const *, unsigned, HexagonMCInstrInfo::PredicateInfo>
WrongSense;
@@ -588,7 +588,7 @@ void HexagonMCChecker::checkRegisterCurDefs() {
for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
if (HexagonMCInstrInfo::isCVINew(MCII, I) &&
HexagonMCInstrInfo::getDesc(MCII, I).mayLoad()) {
- const unsigned RegDef = I.getOperand(0).getReg();
+ const MCRegister RegDef = I.getOperand(0).getReg();
bool HasRegDefUse = false;
for (MCRegAliasIterator Alias(RegDef, &RI, true); Alias.isValid();
@@ -819,7 +819,7 @@ bool HexagonMCChecker::checkHVXAccum()
HexagonMCInstrInfo::isAccumulator(MCII, I) && I.getOperand(0).isReg();
if (!IsTarget)
continue;
- unsigned int R = I.getOperand(0).getReg();
+ MCRegister R = I.getOperand(0).getReg();
TmpDefsIterator It = TmpDefs.find(R);
if (It != TmpDefs.end()) {
reportError("register `" + Twine(RI.getName(R)) + ".tmp" +
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h
index 42d91f559f51a6..e9b87c5315fe4b 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h
@@ -77,15 +77,15 @@ class HexagonMCChecker {
void init();
void init(MCInst const &);
- void initReg(MCInst const &, unsigned, unsigned &PredReg, bool &isTrue);
+ void initReg(MCInst const &, MCRegister, MCRegister &PredReg, bool &isTrue);
- bool registerUsed(unsigned Register);
+ bool registerUsed(MCRegister Register);
/// \return a tuple of: pointer to the producer instruction or nullptr if
/// none was found, the operand index, and the PredicateInfo for the
/// producer.
std::tuple<MCInst const *, unsigned, HexagonMCInstrInfo::PredicateInfo>
- registerProducer(unsigned Register,
+ registerProducer(MCRegister Register,
HexagonMCInstrInfo::PredicateInfo Predicated);
// Checks performed.
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
index 96ec81cd86abe6..b744519b9725ce 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
@@ -388,8 +388,8 @@ void HexagonMCCodeEmitter::encodeInstruction(const MCInst &MI,
}
}
-static bool RegisterMatches(unsigned Consumer, unsigned Producer,
- unsigned Producer2) {
+static bool RegisterMatches(MCRegister Consumer, MCRegister Producer,
+ MCRegister Producer2) {
return (Consumer == Producer) || (Consumer == Producer2) ||
HexagonMCInstrInfo::IsSingleConsumerRefPairProducer(Producer,
Consumer);
@@ -721,9 +721,9 @@ HexagonMCCodeEmitter::getMachineOpValue(MCInst const &MI, MCOperand const &MO,
// Calculate the new value distance to the associated producer
unsigned SOffset = 0;
unsigned VOffset = 0;
- unsigned UseReg = MO.getReg();
- unsigned DefReg1 = Hexagon::NoRegister;
- unsigned DefReg2 = Hexagon::NoRegister;
+ MCRegister UseReg = MO.getReg();
+ MCRegister DefReg1;
+ MCRegister DefReg2;
auto Instrs = HexagonMCInstrInfo::bundleInstructions(*State.Bundle);
const MCOperand *I = Instrs.begin() + State.Index - 1;
@@ -734,8 +734,8 @@ HexagonMCCodeEmitter::getMachineOpValue(MCInst const &MI, MCOperand const &MO,
if (HexagonMCInstrInfo::isImmext(Inst))
continue;
- DefReg1 = Hexagon::NoRegister;
- DefReg2 = Hexagon::NoRegister;
+ DefReg1 = MCRegister();
+ DefReg2 = MCRegister();
++SOffset;
if (HexagonMCInstrInfo::isVector(MCII, Inst)) {
// Vector instructions don't count scalars.
@@ -770,7 +770,7 @@ HexagonMCCodeEmitter::getMachineOpValue(MCInst const &MI, MCOperand const &MO,
assert(!MO.isImm());
if (MO.isReg()) {
- unsigned Reg = MO.getReg();
+ MCRegister Reg = MO.getReg();
switch (HexagonMCInstrInfo::getDesc(MCII, MI)
.operands()[OperandNumber]
.RegClass) {
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCompound.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCompound.cpp
index 3deef95df32450..c1a9a01aaf7abc 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCompound.cpp
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCompound.cpp
@@ -78,7 +78,7 @@ static const unsigned cmpgtn1BitOpcode[8] = {
// enum HexagonII::CompoundGroup
static unsigned getCompoundCandidateGroup(MCInst const &MI, bool IsExtended) {
- unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
+ MCRegister DstReg, SrcReg, Src1Reg, Src2Reg;
switch (MI.getOpcode()) {
default:
@@ -174,7 +174,7 @@ static unsigned getCompoundCandidateGroup(MCInst const &MI, bool IsExtended) {
/// getCompoundOp - Return the index from 0-7 into the above opcode lists.
static unsigned getCompoundOp(MCInst const &HMCI) {
const MCOperand &Predicate = HMCI.getOperand(0);
- unsigned PredReg = Predicate.getReg();
+ MCRegister PredReg = Predicate.getReg();
assert((PredReg == Hexagon::P0) || (PredReg == Hexagon::P1) ||
(PredReg == Hexagon::P2) || (PredReg == Hexagon::P3));
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp
index 36d6c8c9f84b8e..f3bdaf7921efec 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp
@@ -187,7 +187,7 @@ unsigned HexagonMCInstrInfo::iClassOfDuplexPair(unsigned Ga, unsigned Gb) {
}
unsigned HexagonMCInstrInfo::getDuplexCandidateGroup(MCInst const &MCI) {
- unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg;
+ MCRegister DstReg, PredReg, SrcReg, Src1Reg, Src2Reg;
switch (MCI.getOpcode()) {
default:
@@ -533,7 +533,7 @@ unsigned HexagonMCInstrInfo::getDuplexCandidateGroup(MCInst const &MCI) {
}
bool HexagonMCInstrInfo::subInstWouldBeExtended(MCInst const &potentialDuplex) {
- unsigned DstReg, SrcReg;
+ MCRegister DstReg, SrcReg;
switch (potentialDuplex.getOpcode()) {
case Hexagon::A2_addi:
// testing for case of: Rx = add(Rx,#s7)
@@ -657,7 +657,7 @@ bool HexagonMCInstrInfo::isDuplexPair(MCInst const &MIa, MCInst const &MIb) {
inline static void addOps(MCInst &subInstPtr, MCInst const &Inst,
unsigned opNum) {
if (Inst.getOperand(opNum).isReg()) {
- switch (Inst.getOperand(opNum).getReg()) {
+ switch (Inst.getOperand(opNum).getReg().id()) {
default:
llvm_unreachable("Not Duplexable Register");
break;
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
index a6de2ab9c75a26..a2ac8b70b9db46 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
@@ -257,10 +257,10 @@ MCInstrDesc const &HexagonMCInstrInfo::getDesc(MCInstrInfo const &MCII,
return MCII.get(MCI.getOpcode());
}
-unsigned HexagonMCInstrInfo::getDuplexRegisterNumbering(unsigned Reg) {
+unsigned HexagonMCInstrInfo::getDuplexRegisterNumbering(MCRegister Reg) {
using namespace Hexagon;
- switch (Reg) {
+ switch (Reg.id()) {
default:
llvm_unreachable("unknown duplex register");
// Rs Rss
@@ -616,7 +616,7 @@ bool HexagonMCInstrInfo::isCVINew(MCInstrInfo const &MCII, MCInst const &MCI) {
return ((F >> HexagonII::CVINewPos) & HexagonII::CVINewMask);
}
-bool HexagonMCInstrInfo::isDblRegForSubInst(unsigned Reg) {
+bool HexagonMCInstrInfo::isDblRegForSubInst(MCRegister Reg) {
return ((Reg >= Hexagon::D0 && Reg <= Hexagon::D3) ||
(Reg >= Hexagon::D8 && Reg <= Hexagon::D11));
}
@@ -657,11 +657,11 @@ bool HexagonMCInstrInfo::isInnerLoop(MCInst const &MCI) {
return (Flags & innerLoopMask) != 0;
}
-bool HexagonMCInstrInfo::isIntReg(unsigned Reg) {
+bool HexagonMCInstrInfo::isIntReg(MCRegister Reg) {
return (Reg >= Hexagon::R0 && Reg <= Hexagon::R31);
}
-bool HexagonMCInstrInfo::isIntRegForSubInst(unsigned Reg) {
+bool HexagonMCInstrInfo::isIntRegForSubInst(MCRegister Reg) {
return ((Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
(Reg >= Hexagon::R16 && Reg <= Hexagon::R23));
}
@@ -691,21 +691,21 @@ bool HexagonMCInstrInfo::isOuterLoop(MCInst const &MCI) {
return (Flags & outerLoopMask) != 0;
}
-bool HexagonMCInstrInfo::IsVecRegPair(unsigned VecReg) {
+bool HexagonMCInstrInfo::IsVecRegPair(MCRegister VecReg) {
return (VecReg >= Hexagon::W0 && VecReg <= Hexagon::W15) ||
(VecReg >= Hexagon::WR0 && VecReg <= Hexagon::WR15);
}
-bool HexagonMCInstrInfo::IsReverseVecRegPair(unsigned VecReg) {
+bool HexagonMCInstrInfo::IsReverseVecRegPair(MCRegister VecReg) {
return (VecReg >= Hexagon::WR0 && VecReg <= Hexagon::WR15);
}
-bool HexagonMCInstrInfo::IsVecRegSingle(unsigned VecReg) {
+bool HexagonMCInstrInfo::IsVecRegSingle(MCRegister VecReg) {
return (VecReg >= Hexagon::V0 && VecReg <= Hexagon::V31);
}
std::pair<unsigned, unsigned>
-HexagonMCInstrInfo::GetVecRegPairIndices(unsigned VecRegPair) {
+HexagonMCInstrInfo::GetVecRegPairIndices(MCRegister VecRegPair) {
assert(IsVecRegPair(VecRegPair) &&
"VecRegPair must be a vector register pair");
@@ -717,8 +717,8 @@ HexagonMCInstrInfo::GetVecRegPairIndices(unsigned VecRegPair) {
: std::make_pair(PairIndex + 1, PairIndex);
}
-bool HexagonMCInstrInfo::IsSingleConsumerRefPairProducer(unsigned Producer,
- unsigned Consumer) {
+bool HexagonMCInstrInfo::IsSingleConsumerRefPairProducer(MCRegister Producer,
+ MCRegister Consumer) {
if (IsVecRegPair(Producer) && IsVecRegSingle(Consumer)) {
const unsigned ProdPairIndex = IsReverseVecRegPair(Producer)
? Producer - Hexagon::WR0
@@ -760,7 +760,7 @@ bool HexagonMCInstrInfo::isPredicatedTrue(MCInstrInfo const &MCII,
!((F >> HexagonII::PredicatedFalsePos) & HexagonII::PredicatedFalseMask));
}
-bool HexagonMCInstrInfo::isPredReg(MCRegisterInfo const &MRI, unsigned Reg) {
+bool HexagonMCInstrInfo::isPredReg(MCRegisterInfo const &MRI, MCRegister Reg) {
auto &PredRegClass = MRI.getRegClass(Hexagon::PredRegsRegClassID);
return PredRegClass.contains(Reg);
}
@@ -1031,9 +1031,9 @@ void HexagonMCInstrInfo::setOuterLoop(MCInst &MCI) {
Operand.setImm(Operand.getImm() | outerLoopMask);
}
-unsigned HexagonMCInstrInfo::SubregisterBit(unsigned Consumer,
- unsigned Producer,
- unsigned Producer2) {
+unsigned HexagonMCInstrInfo::SubregisterBit(MCRegister Consumer,
+ MCRegister Producer,
+ MCRegister Producer2) {
// If we're a single vector consumer of a double producer, set subreg bit
// based on if we're accessing the lower or upper register component
if (IsVecRegPair(Producer) && IsVecRegSingle(Consumer)) {
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h
index ccd2482c3fd766..df942b63ee2827 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h
@@ -132,7 +132,7 @@ unsigned getDuplexCandidateGroup(MCInst const &MI);
SmallVector<DuplexCandidate, 8>
getDuplexPossibilties(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
MCInst const &MCB);
-unsigned getDuplexRegisterNumbering(unsigned Reg);
+unsigned getDuplexRegisterNumbering(MCRegister Reg);
MCExpr const &getExpr(MCExpr const &Expr);
@@ -231,7 +231,7 @@ bool isConstExtended(MCInstrInfo const &MCII, MCInst const &MCI);
bool isCVINew(MCInstrInfo const &MCII, MCInst const &MCI);
// Is this double register suitable for use in a duplex subinst
-bool isDblRegForSubInst(unsigned Reg);
+bool isDblRegForSubInst(MCRegister Reg);
// Is this a duplex instruction
bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI);
@@ -260,10 +260,10 @@ bool isImmext(MCInst const &MCI);
bool isInnerLoop(MCInst const &MCI);
// Is this an integer register
-bool isIntReg(unsigned Reg);
+bool isIntReg(MCRegister Reg);
// Is this register suitable for use in a duplex subinst
-bool isIntRegForSubInst(unsigned Reg);
+bool isIntRegForSubInst(MCRegister Reg);
bool isMemReorderDisabled(MCInst const &MCI);
// Return whether the insn is a new-value consumer.
@@ -289,7 +289,7 @@ bool isPredicatedNew(MCInstrInfo const &MCII, MCInst const &MCI);
bool isPredicatedTrue(MCInstrInfo const &MCII, MCInst const &MCI);
// Return true if this is a scalar predicate register.
-bool isPredReg(MCRegisterInfo const &MRI, unsigned Reg);
+bool isPredReg(MCRegisterInfo const &MRI, MCRegister Reg);
// Returns true if the Ith operand is a predicate register.
bool isPredRegister(MCInstrInfo const &MCII, MCInst const &Inst, unsigned I);
@@ -333,11 +333,11 @@ unsigned slotsConsumed(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
void padEndloop(MCInst &MCI, MCContext &Context);
class PredicateInfo {
public:
- PredicateInfo() : Register(0), Operand(0), PredicatedTrue(false) {}
- PredicateInfo(unsigned Register, unsigned Operand, bool PredicatedTrue)
+ PredicateInfo() : Operand(0), PredicatedTrue(false) {}
+ PredicateInfo(MCRegister Register, unsigned Operand, bool PredicatedTrue)
: Register(Register), Operand(Operand), PredicatedTrue(PredicatedTrue) {}
bool isPredicated() const;
- unsigned Register;
+ MCRegister Register;
unsigned Operand;
bool PredicatedTrue;
};
@@ -360,18 +360,18 @@ void setOuterLoop(MCInst &MCI);
// Would duplexing this instruction create a requirement to extend
bool subInstWouldBeExtended(MCInst const &potentialDuplex);
-unsigned SubregisterBit(unsigned Consumer, unsigned Producer,
- unsigned Producer2);
+unsigned SubregisterBit(MCRegister Consumer, MCRegister Producer,
+ MCRegister Producer2);
-bool IsVecRegSingle(unsigned VecReg);
-bool IsVecRegPair(unsigned VecReg);
-bool IsReverseVecRegPair(unsigned VecReg);
-bool IsSingleConsumerRefPairProducer(unsigned Producer, unsigned Consumer);
+bool IsVecRegSingle(MCRegister VecReg);
+bool IsVecRegPair(MCRegister VecReg);
+bool IsReverseVecRegPair(MCRegister VecReg);
+bool IsSingleConsumerRefPairProducer(MCRegister Producer, MCRegister Consumer);
/// Returns an ordered pair of the constituent register ordinals for
/// each of the elements of \a VecRegPair. For example, Hexagon::W0 ("v0:1")
/// returns { 0, 1 } and Hexagon::W1 ("v3:2") returns { 3, 2 }.
-std::pair<unsigned, unsigned> GetVecRegPairIndices(unsigned VecRegPair);
+std::pair<unsigned, unsigned> GetVecRegPairIndices(MCRegister VecRegPair);
// Attempt to find and replace compound pairs
void tryCompound(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
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