[llvm] fd50cdf - [AMDGPU] Use MCRegister. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat Sep 28 11:41:04 PDT 2024
Author: Craig Topper
Date: 2024-09-28T11:40:25-07:00
New Revision: fd50cdfb94c9013ca0c194a4f5d001160c0f6171
URL: https://github.com/llvm/llvm-project/commit/fd50cdfb94c9013ca0c194a4f5d001160c0f6171
DIFF: https://github.com/llvm/llvm-project/commit/fd50cdfb94c9013ca0c194a4f5d001160c0f6171.diff
LOG: [AMDGPU] Use MCRegister. NFC
Added:
Modified:
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
llvm/lib/Target/AMDGPU/MCTargetDesc/R600InstPrinter.cpp
llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 1308e18f88b9d8..e12db4ab058ed6 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -203,7 +203,7 @@ class AMDGPUOperand : public MCParsedAsmOperand {
};
struct RegOp {
- unsigned RegNo;
+ MCRegister RegNo;
Modifiers Mods;
};
@@ -1192,10 +1192,9 @@ class AMDGPUOperand : public MCParsedAsmOperand {
}
static AMDGPUOperand::Ptr CreateReg(const AMDGPUAsmParser *AsmParser,
- unsigned RegNo, SMLoc S,
- SMLoc E) {
+ MCRegister Reg, SMLoc S, SMLoc E) {
auto Op = std::make_unique<AMDGPUOperand>(Register, AsmParser);
- Op->Reg.RegNo = RegNo;
+ Op->Reg.RegNo = Reg;
Op->Reg.Mods = Modifiers();
Op->StartLoc = S;
Op->EndLoc = E;
@@ -1357,7 +1356,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
bool ParseAMDKernelCodeTValue(StringRef ID, AMDGPUMCKernelCodeT &Header);
bool ParseDirectiveAMDKernelCodeT();
// TODO: Possibly make subtargetHasRegister const.
- bool subtargetHasRegister(const MCRegisterInfo &MRI, unsigned RegNo);
+ bool subtargetHasRegister(const MCRegisterInfo &MRI, MCRegister Reg);
bool ParseDirectiveAMDGPUHsaKernel();
bool ParseDirectiveISAVersion();
@@ -1372,25 +1371,26 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
const char *AssemblerDirectiveEnd,
std::string &CollectString);
- bool AddNextRegisterToList(unsigned& Reg, unsigned& RegWidth,
- RegisterKind RegKind, unsigned Reg1, SMLoc Loc);
- bool ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg,
+ bool AddNextRegisterToList(MCRegister &Reg, unsigned &RegWidth,
+ RegisterKind RegKind, MCRegister Reg1, SMLoc Loc);
+ bool ParseAMDGPURegister(RegisterKind &RegKind, MCRegister &Reg,
unsigned &RegNum, unsigned &RegWidth,
bool RestoreOnFailure = false);
- bool ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg,
+ bool ParseAMDGPURegister(RegisterKind &RegKind, MCRegister &Reg,
unsigned &RegNum, unsigned &RegWidth,
SmallVectorImpl<AsmToken> &Tokens);
- unsigned ParseRegularReg(RegisterKind &RegKind, unsigned &RegNum,
- unsigned &RegWidth,
- SmallVectorImpl<AsmToken> &Tokens);
- unsigned ParseSpecialReg(RegisterKind &RegKind, unsigned &RegNum,
- unsigned &RegWidth,
- SmallVectorImpl<AsmToken> &Tokens);
- unsigned ParseRegList(RegisterKind &RegKind, unsigned &RegNum,
- unsigned &RegWidth, SmallVectorImpl<AsmToken> &Tokens);
+ MCRegister ParseRegularReg(RegisterKind &RegKind, unsigned &RegNum,
+ unsigned &RegWidth,
+ SmallVectorImpl<AsmToken> &Tokens);
+ MCRegister ParseSpecialReg(RegisterKind &RegKind, unsigned &RegNum,
+ unsigned &RegWidth,
+ SmallVectorImpl<AsmToken> &Tokens);
+ MCRegister ParseRegList(RegisterKind &RegKind, unsigned &RegNum,
+ unsigned &RegWidth,
+ SmallVectorImpl<AsmToken> &Tokens);
bool ParseRegRange(unsigned& Num, unsigned& Width);
- unsigned getRegularReg(RegisterKind RegKind, unsigned RegNum, unsigned SubReg,
- unsigned RegWidth, SMLoc Loc);
+ MCRegister getRegularReg(RegisterKind RegKind, unsigned RegNum,
+ unsigned SubReg, unsigned RegWidth, SMLoc Loc);
bool isRegister();
bool isRegister(const AsmToken &Token, const AsmToken &NextToken) const;
@@ -1746,7 +1746,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
SMLoc getOperandLoc(std::function<bool(const AMDGPUOperand&)> Test,
const OperandVector &Operands) const;
SMLoc getImmLoc(AMDGPUOperand::ImmTy Type, const OperandVector &Operands) const;
- SMLoc getRegLoc(unsigned Reg, const OperandVector &Operands) const;
+ SMLoc getRegLoc(MCRegister Reg, const OperandVector &Operands) const;
SMLoc getLitLoc(const OperandVector &Operands,
bool SearchMandatoryLiterals = false) const;
SMLoc getMandatoryLitLoc(const OperandVector &Operands) const;
@@ -1773,7 +1773,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
bool validateOpSel(const MCInst &Inst);
bool validateNeg(const MCInst &Inst, int OpName);
bool validateDPP(const MCInst &Inst, const OperandVector &Operands);
- bool validateVccOperand(unsigned Reg) const;
+ bool validateVccOperand(MCRegister Reg) const;
bool validateVOPLiteral(const MCInst &Inst, const OperandVector &Operands);
bool validateMAIAccWrite(const MCInst &Inst, const OperandVector &Operands);
bool validateMAISrc2(const MCInst &Inst, const OperandVector &Operands);
@@ -2637,7 +2637,7 @@ static int getRegClass(RegisterKind Is, unsigned RegWidth) {
return -1;
}
-static unsigned getSpecialRegForName(StringRef RegName) {
+static MCRegister getSpecialRegForName(StringRef RegName) {
return StringSwitch<unsigned>(RegName)
.Case("exec", AMDGPU::EXEC)
.Case("vcc", AMDGPU::VCC)
@@ -2709,9 +2709,9 @@ ParseStatus AMDGPUAsmParser::tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
return ParseStatus::Success;
}
-bool AMDGPUAsmParser::AddNextRegisterToList(unsigned &Reg, unsigned &RegWidth,
- RegisterKind RegKind, unsigned Reg1,
- SMLoc Loc) {
+bool AMDGPUAsmParser::AddNextRegisterToList(MCRegister &Reg, unsigned &RegWidth,
+ RegisterKind RegKind,
+ MCRegister Reg1, SMLoc Loc) {
switch (RegKind) {
case IS_SPECIAL:
if (Reg == AMDGPU::EXEC_LO && Reg1 == AMDGPU::EXEC_HI) {
@@ -2824,7 +2824,7 @@ AMDGPUAsmParser::isRegister(const AsmToken &Token,
}
}
- return getSpecialRegForName(Str) != AMDGPU::NoRegister;
+ return getSpecialRegForName(Str).isValid();
}
bool
@@ -2833,9 +2833,9 @@ AMDGPUAsmParser::isRegister()
return isRegister(getToken(), peekToken());
}
-unsigned AMDGPUAsmParser::getRegularReg(RegisterKind RegKind, unsigned RegNum,
- unsigned SubReg, unsigned RegWidth,
- SMLoc Loc) {
+MCRegister AMDGPUAsmParser::getRegularReg(RegisterKind RegKind, unsigned RegNum,
+ unsigned SubReg, unsigned RegWidth,
+ SMLoc Loc) {
assert(isRegularReg(RegKind));
unsigned AlignSize = 1;
@@ -2847,24 +2847,24 @@ unsigned AMDGPUAsmParser::getRegularReg(RegisterKind RegKind, unsigned RegNum,
if (RegNum % AlignSize != 0) {
Error(Loc, "invalid register alignment");
- return AMDGPU::NoRegister;
+ return MCRegister();
}
unsigned RegIdx = RegNum / AlignSize;
int RCID = getRegClass(RegKind, RegWidth);
if (RCID == -1) {
Error(Loc, "invalid or unsupported register size");
- return AMDGPU::NoRegister;
+ return MCRegister();
}
const MCRegisterInfo *TRI = getContext().getRegisterInfo();
const MCRegisterClass RC = TRI->getRegClass(RCID);
if (RegIdx >= RC.getNumRegs()) {
Error(Loc, "register index is out of range");
- return AMDGPU::NoRegister;
+ return MCRegister();
}
- unsigned Reg = RC.getRegister(RegIdx);
+ MCRegister Reg = RC.getRegister(RegIdx);
if (SubReg) {
Reg = TRI->getSubReg(Reg, SubReg);
@@ -2919,11 +2919,12 @@ bool AMDGPUAsmParser::ParseRegRange(unsigned &Num, unsigned &RegWidth) {
return true;
}
-unsigned AMDGPUAsmParser::ParseSpecialReg(RegisterKind &RegKind,
- unsigned &RegNum, unsigned &RegWidth,
- SmallVectorImpl<AsmToken> &Tokens) {
+MCRegister AMDGPUAsmParser::ParseSpecialReg(RegisterKind &RegKind,
+ unsigned &RegNum,
+ unsigned &RegWidth,
+ SmallVectorImpl<AsmToken> &Tokens) {
assert(isToken(AsmToken::Identifier));
- unsigned Reg = getSpecialRegForName(getTokenStr());
+ MCRegister Reg = getSpecialRegForName(getTokenStr());
if (Reg) {
RegNum = 0;
RegWidth = 32;
@@ -2934,9 +2935,10 @@ unsigned AMDGPUAsmParser::ParseSpecialReg(RegisterKind &RegKind,
return Reg;
}
-unsigned AMDGPUAsmParser::ParseRegularReg(RegisterKind &RegKind,
- unsigned &RegNum, unsigned &RegWidth,
- SmallVectorImpl<AsmToken> &Tokens) {
+MCRegister AMDGPUAsmParser::ParseRegularReg(RegisterKind &RegKind,
+ unsigned &RegNum,
+ unsigned &RegWidth,
+ SmallVectorImpl<AsmToken> &Tokens) {
assert(isToken(AsmToken::Identifier));
StringRef RegName = getTokenStr();
auto Loc = getLoc();
@@ -2944,7 +2946,7 @@ unsigned AMDGPUAsmParser::ParseRegularReg(RegisterKind &RegKind,
const RegInfo *RI = getRegularRegInfo(RegName);
if (!RI) {
Error(Loc, "invalid register name");
- return AMDGPU::NoRegister;
+ return MCRegister();
}
Tokens.push_back(getToken());
@@ -2962,64 +2964,65 @@ unsigned AMDGPUAsmParser::ParseRegularReg(RegisterKind &RegKind,
// Single 32-bit register: vXX.
if (!getRegNum(RegSuffix, RegNum)) {
Error(Loc, "invalid register index");
- return AMDGPU::NoRegister;
+ return MCRegister();
}
RegWidth = 32;
} else {
// Range of registers: v[XX:YY]. ":YY" is optional.
if (!ParseRegRange(RegNum, RegWidth))
- return AMDGPU::NoRegister;
+ return MCRegister();
}
return getRegularReg(RegKind, RegNum, SubReg, RegWidth, Loc);
}
-unsigned AMDGPUAsmParser::ParseRegList(RegisterKind &RegKind, unsigned &RegNum,
- unsigned &RegWidth,
- SmallVectorImpl<AsmToken> &Tokens) {
- unsigned Reg = AMDGPU::NoRegister;
+MCRegister AMDGPUAsmParser::ParseRegList(RegisterKind &RegKind,
+ unsigned &RegNum, unsigned &RegWidth,
+ SmallVectorImpl<AsmToken> &Tokens) {
+ MCRegister Reg;
auto ListLoc = getLoc();
if (!skipToken(AsmToken::LBrac,
"expected a register or a list of registers")) {
- return AMDGPU::NoRegister;
+ return MCRegister();
}
// List of consecutive registers, e.g.: [s0,s1,s2,s3]
auto Loc = getLoc();
if (!ParseAMDGPURegister(RegKind, Reg, RegNum, RegWidth))
- return AMDGPU::NoRegister;
+ return MCRegister();
if (RegWidth != 32) {
Error(Loc, "expected a single 32-bit register");
- return AMDGPU::NoRegister;
+ return MCRegister();
}
for (; trySkipToken(AsmToken::Comma); ) {
RegisterKind NextRegKind;
- unsigned NextReg, NextRegNum, NextRegWidth;
+ MCRegister NextReg;
+ unsigned NextRegNum, NextRegWidth;
Loc = getLoc();
if (!ParseAMDGPURegister(NextRegKind, NextReg,
NextRegNum, NextRegWidth,
Tokens)) {
- return AMDGPU::NoRegister;
+ return MCRegister();
}
if (NextRegWidth != 32) {
Error(Loc, "expected a single 32-bit register");
- return AMDGPU::NoRegister;
+ return MCRegister();
}
if (NextRegKind != RegKind) {
Error(Loc, "registers in a list must be of the same kind");
- return AMDGPU::NoRegister;
+ return MCRegister();
}
if (!AddNextRegisterToList(Reg, RegWidth, RegKind, NextReg, Loc))
- return AMDGPU::NoRegister;
+ return MCRegister();
}
if (!skipToken(AsmToken::RBrac,
"expected a comma or a closing square bracket")) {
- return AMDGPU::NoRegister;
+ return MCRegister();
}
if (isRegularReg(RegKind))
@@ -3028,22 +3031,23 @@ unsigned AMDGPUAsmParser::ParseRegList(RegisterKind &RegKind, unsigned &RegNum,
return Reg;
}
-bool AMDGPUAsmParser::ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg,
- unsigned &RegNum, unsigned &RegWidth,
+bool AMDGPUAsmParser::ParseAMDGPURegister(RegisterKind &RegKind,
+ MCRegister &Reg, unsigned &RegNum,
+ unsigned &RegWidth,
SmallVectorImpl<AsmToken> &Tokens) {
auto Loc = getLoc();
- Reg = AMDGPU::NoRegister;
+ Reg = MCRegister();
if (isToken(AsmToken::Identifier)) {
Reg = ParseSpecialReg(RegKind, RegNum, RegWidth, Tokens);
- if (Reg == AMDGPU::NoRegister)
+ if (!Reg)
Reg = ParseRegularReg(RegKind, RegNum, RegWidth, Tokens);
} else {
Reg = ParseRegList(RegKind, RegNum, RegWidth, Tokens);
}
const MCRegisterInfo *TRI = getContext().getRegisterInfo();
- if (Reg == AMDGPU::NoRegister) {
+ if (!Reg) {
assert(Parser.hasPendingError());
return false;
}
@@ -3061,10 +3065,11 @@ bool AMDGPUAsmParser::ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg,
return true;
}
-bool AMDGPUAsmParser::ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg,
- unsigned &RegNum, unsigned &RegWidth,
+bool AMDGPUAsmParser::ParseAMDGPURegister(RegisterKind &RegKind,
+ MCRegister &Reg, unsigned &RegNum,
+ unsigned &RegWidth,
bool RestoreOnFailure /*=false*/) {
- Reg = AMDGPU::NoRegister;
+ Reg = MCRegister();
SmallVector<AsmToken, 1> Tokens;
if (ParseAMDGPURegister(RegKind, Reg, RegNum, RegWidth, Tokens)) {
@@ -3132,7 +3137,8 @@ AMDGPUAsmParser::parseRegister(bool RestoreOnFailure) {
SMLoc StartLoc = Tok.getLoc();
SMLoc EndLoc = Tok.getEndLoc();
RegisterKind RegKind;
- unsigned Reg, RegNum, RegWidth;
+ MCRegister Reg;
+ unsigned RegNum, RegWidth;
if (!ParseAMDGPURegister(RegKind, Reg, RegNum, RegWidth)) {
return nullptr;
@@ -3735,7 +3741,7 @@ bool AMDGPUAsmParser::validateConstantBusLimitations(
const MCInst &Inst, const OperandVector &Operands) {
const unsigned Opcode = Inst.getOpcode();
const MCInstrDesc &Desc = MII.get(Opcode);
- unsigned LastSGPR = AMDGPU::NoRegister;
+ MCRegister LastSGPR;
unsigned ConstantBusUseCount = 0;
unsigned NumLiterals = 0;
unsigned LiteralSize;
@@ -4688,7 +4694,7 @@ bool AMDGPUAsmParser::validateDPP(const MCInst &Inst,
}
// Check if VCC register matches wavefront size
-bool AMDGPUAsmParser::validateVccOperand(unsigned Reg) const {
+bool AMDGPUAsmParser::validateVccOperand(MCRegister Reg) const {
auto FB = getFeatureBits();
return (FB[AMDGPU::FeatureWavefrontSize64] && Reg == AMDGPU::VCC) ||
(FB[AMDGPU::FeatureWavefrontSize32] && Reg == AMDGPU::VCC_LO);
@@ -4820,7 +4826,7 @@ bool AMDGPUAsmParser::validateVGPRAlign(const MCInst &Inst) const {
if (!Op.isReg())
continue;
- unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0);
+ MCRegister Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0);
if (!Sub)
continue;
@@ -6248,15 +6254,15 @@ bool AMDGPUAsmParser::ParseDirective(AsmToken DirectiveID) {
}
bool AMDGPUAsmParser::subtargetHasRegister(const MCRegisterInfo &MRI,
- unsigned RegNo) {
- if (MRI.regsOverlap(TTMP12_TTMP13_TTMP14_TTMP15, RegNo))
+ MCRegister Reg) {
+ if (MRI.regsOverlap(TTMP12_TTMP13_TTMP14_TTMP15, Reg))
return isGFX9Plus();
// GFX10+ has 2 more SGPRs 104 and 105.
- if (MRI.regsOverlap(SGPR104_SGPR105, RegNo))
+ if (MRI.regsOverlap(SGPR104_SGPR105, Reg))
return hasSGPR104_SGPR105();
- switch (RegNo) {
+ switch (Reg.id()) {
case SRC_SHARED_BASE_LO:
case SRC_SHARED_BASE:
case SRC_SHARED_LIMIT_LO:
@@ -6295,7 +6301,7 @@ bool AMDGPUAsmParser::subtargetHasRegister(const MCRegisterInfo &MRI,
// No flat_scr on SI.
// On GFX10Plus flat scratch is not a valid register operand and can only be
// accessed with s_setreg/s_getreg.
- switch (RegNo) {
+ switch (Reg.id()) {
case FLAT_SCR:
case FLAT_SCR_LO:
case FLAT_SCR_HI:
@@ -6307,7 +6313,7 @@ bool AMDGPUAsmParser::subtargetHasRegister(const MCRegisterInfo &MRI,
// VI only has 102 SGPRs, so make sure we aren't trying to use the 2 more that
// SI/CI have.
- if (MRI.regsOverlap(SGPR102_SGPR103, RegNo))
+ if (MRI.regsOverlap(SGPR102_SGPR103, Reg))
return hasSGPR102_SGPR103();
return true;
@@ -7105,7 +7111,7 @@ void AMDGPUAsmParser::cvtExp(MCInst &Inst, const OperandVector &Operands) {
if (Op.isOff()) {
assert(SrcIdx < 4);
OperandIdx[SrcIdx] = Inst.size();
- Inst.addOperand(MCOperand::createReg(AMDGPU::NoRegister));
+ Inst.addOperand(MCOperand::createReg(MCRegister()));
++SrcIdx;
continue;
}
@@ -7128,12 +7134,12 @@ void AMDGPUAsmParser::cvtExp(MCInst &Inst, const OperandVector &Operands) {
if (OptionalIdx.find(AMDGPUOperand::ImmTyExpCompr) != OptionalIdx.end()) {
Compr = true;
Inst.getOperand(OperandIdx[1]) = Inst.getOperand(OperandIdx[2]);
- Inst.getOperand(OperandIdx[2]).setReg(AMDGPU::NoRegister);
- Inst.getOperand(OperandIdx[3]).setReg(AMDGPU::NoRegister);
+ Inst.getOperand(OperandIdx[2]).setReg(MCRegister());
+ Inst.getOperand(OperandIdx[3]).setReg(MCRegister());
}
for (auto i = 0; i < SrcIdx; ++i) {
- if (Inst.getOperand(OperandIdx[i]).getReg() != AMDGPU::NoRegister) {
+ if (Inst.getOperand(OperandIdx[i]).getReg()) {
EnMask |= Compr? (0x3 << i * 2) : (0x1 << i);
}
}
@@ -7902,9 +7908,8 @@ AMDGPUAsmParser::getImmLoc(AMDGPUOperand::ImmTy Type,
return getOperandLoc(Test, Operands);
}
-SMLoc
-AMDGPUAsmParser::getRegLoc(unsigned Reg,
- const OperandVector &Operands) const {
+SMLoc AMDGPUAsmParser::getRegLoc(MCRegister Reg,
+ const OperandVector &Operands) const {
auto Test = [=](const AMDGPUOperand& Op) {
return Op.isRegKind() && Op.getReg() == Reg;
};
@@ -9347,7 +9352,7 @@ void AMDGPUAsmParser::cvtVOP3DPP(MCInst &Inst, const OperandVector &Operands,
if (IsVOP3CvtSrDpp) {
if (Src2ModIdx == static_cast<int>(Inst.getNumOperands())) {
Inst.addOperand(MCOperand::createImm(0));
- Inst.addOperand(MCOperand::createReg(0));
+ Inst.addOperand(MCOperand::createReg(MCRegister()));
}
}
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
index ca4be01736c1f2..9eedcc636fd94e 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -1038,18 +1038,18 @@ void AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const {
return;
// Widen the register to the correct number of enabled channels.
- unsigned NewVdata = AMDGPU::NoRegister;
+ MCRegister NewVdata;
if (DstSize != Info->VDataDwords) {
auto DataRCID = MCII->get(NewOpcode).operands()[VDataIdx].RegClass;
// Get first subregister of VData
- unsigned Vdata0 = MI.getOperand(VDataIdx).getReg();
- unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0);
+ MCRegister Vdata0 = MI.getOperand(VDataIdx).getReg();
+ MCRegister VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0);
Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0;
NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0,
&MRI.getRegClass(DataRCID));
- if (NewVdata == AMDGPU::NoRegister) {
+ if (!NewVdata) {
// It's possible to encode this such that the low register + enabled
// components exceeds the register count.
return;
@@ -1059,11 +1059,11 @@ void AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const {
// If not using NSA on GFX10+, widen vaddr0 address register to correct size.
// If using partial NSA on GFX11+ widen last address register.
int VAddrSAIdx = IsPartialNSA ? (RsrcIdx - 1) : VAddr0Idx;
- unsigned NewVAddrSA = AMDGPU::NoRegister;
+ MCRegister NewVAddrSA;
if (STI.hasFeature(AMDGPU::FeatureNSAEncoding) && (!IsNSA || IsPartialNSA) &&
AddrSize != Info->VAddrDwords) {
- unsigned VAddrSA = MI.getOperand(VAddrSAIdx).getReg();
- unsigned VAddrSubSA = MRI.getSubReg(VAddrSA, AMDGPU::sub0);
+ MCRegister VAddrSA = MI.getOperand(VAddrSAIdx).getReg();
+ MCRegister VAddrSubSA = MRI.getSubReg(VAddrSA, AMDGPU::sub0);
VAddrSA = VAddrSubSA ? VAddrSubSA : VAddrSA;
auto AddrRCID = MCII->get(NewOpcode).operands()[VAddrSAIdx].RegClass;
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
index 91e8f52df5b41d..dd8d93c3f0b72a 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
@@ -315,10 +315,10 @@ void AMDGPUInstPrinter::printSymbolicFormat(const MCInst *MI,
}
}
-void AMDGPUInstPrinter::printRegOperand(unsigned RegNo, raw_ostream &O,
+void AMDGPUInstPrinter::printRegOperand(MCRegister Reg, raw_ostream &O,
const MCRegisterInfo &MRI) {
#if !defined(NDEBUG)
- switch (RegNo) {
+ switch (Reg.id()) {
case AMDGPU::FP_REG:
case AMDGPU::SP_REG:
case AMDGPU::PRIVATE_RSRC_REG:
@@ -328,7 +328,7 @@ void AMDGPUInstPrinter::printRegOperand(unsigned RegNo, raw_ostream &O,
}
#endif
- O << getRegisterName(RegNo);
+ O << getRegisterName(Reg);
}
void AMDGPUInstPrinter::printVOPDst(const MCInst *MI, unsigned OpNo,
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
index 4d44db5d9d818c..a72e0fe6ea769f 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
@@ -32,7 +32,7 @@ class AMDGPUInstPrinter : public MCInstPrinter {
void printRegName(raw_ostream &OS, MCRegister Reg) const override;
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
const MCSubtargetInfo &STI, raw_ostream &O) override;
- static void printRegOperand(unsigned RegNo, raw_ostream &O,
+ static void printRegOperand(MCRegister Reg, raw_ostream &O,
const MCRegisterInfo &MRI);
private:
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
index 2af1f919730257..f5e05f6bd658a8 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
@@ -489,7 +489,7 @@ void AMDGPUMCCodeEmitter::getSDWASrcEncoding(const MCInst &MI, unsigned OpNo,
const MCOperand &MO = MI.getOperand(OpNo);
if (MO.isReg()) {
- unsigned Reg = MO.getReg();
+ MCRegister Reg = MO.getReg();
RegEnc |= MRI.getEncodingValue(Reg);
RegEnc &= SDWA9EncValues::SRC_VGPR_MASK;
if (AMDGPU::isSGPR(AMDGPU::mc2PseudoReg(Reg), &MRI)) {
@@ -518,7 +518,7 @@ void AMDGPUMCCodeEmitter::getSDWAVopcDstEncoding(
const MCOperand &MO = MI.getOperand(OpNo);
- unsigned Reg = MO.getReg();
+ MCRegister Reg = MO.getReg();
if (Reg != AMDGPU::VCC && Reg != AMDGPU::VCC_LO) {
RegEnc |= MRI.getEncodingValue(Reg);
RegEnc &= SDWA9EncValues::VOPC_DST_SGPR_MASK;
@@ -530,7 +530,7 @@ void AMDGPUMCCodeEmitter::getSDWAVopcDstEncoding(
void AMDGPUMCCodeEmitter::getAVOperandEncoding(
const MCInst &MI, unsigned OpNo, APInt &Op,
SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const {
- unsigned Reg = MI.getOperand(OpNo).getReg();
+ MCRegister Reg = MI.getOperand(OpNo).getReg();
unsigned Enc = MRI.getEncodingValue(Reg);
unsigned Idx = Enc & AMDGPU::HWEncoding::REG_IDX_MASK;
bool IsVGPROrAGPR =
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/R600InstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/R600InstPrinter.cpp
index 56a23e26b8d9f0..7a9ed80bd1a6c5 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/R600InstPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/R600InstPrinter.cpp
@@ -141,7 +141,7 @@ void R600InstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
const MCOperand &Op = MI->getOperand(OpNo);
if (Op.isReg()) {
- switch (Op.getReg()) {
+ switch (Op.getReg().id()) {
// This is the default predicate state, so we don't need to print it.
case R600::PRED_SEL_OFF:
break;
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp
index fa040d548f64cd..134f30518d5017 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp
@@ -52,7 +52,7 @@ class R600MCCodeEmitter : public MCCodeEmitter {
void emit(uint32_t value, SmallVectorImpl<char> &CB) const;
void emit(uint64_t value, SmallVectorImpl<char> &CB) const;
- unsigned getHWReg(unsigned regNo) const;
+ unsigned getHWReg(MCRegister Reg) const;
uint64_t getBinaryCodeForInstr(const MCInst &MI,
SmallVectorImpl<MCFixup> &Fixups,
@@ -145,8 +145,8 @@ void R600MCCodeEmitter::emit(uint64_t Value, SmallVectorImpl<char> &CB) const {
support::endian::write(CB, Value, llvm::endianness::little);
}
-unsigned R600MCCodeEmitter::getHWReg(unsigned RegNo) const {
- return MRI.getEncodingValue(RegNo) & HW_REG_MASK;
+unsigned R600MCCodeEmitter::getHWReg(MCRegister Reg) const {
+ return MRI.getEncodingValue(Reg) & HW_REG_MASK;
}
uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI,
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
index f32c82f1e4ba4c..8901e4a50bab94 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -2219,9 +2219,9 @@ int32_t getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR,
return std::max(ArgNumVGPR, ArgNumAGPR);
}
-bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI) {
+bool isSGPR(MCRegister Reg, const MCRegisterInfo *TRI) {
const MCRegisterClass SGPRClass = TRI->getRegClass(AMDGPU::SReg_32RegClassID);
- const unsigned FirstSubReg = TRI->getSubReg(Reg, AMDGPU::sub0);
+ const MCRegister FirstSubReg = TRI->getSubReg(Reg, AMDGPU::sub0);
return SGPRClass.contains(FirstSubReg != 0 ? FirstSubReg : Reg) ||
Reg == AMDGPU::SCC;
}
@@ -2232,7 +2232,7 @@ bool isHi16Reg(MCRegister Reg, const MCRegisterInfo &MRI) {
#define MAP_REG2REG \
using namespace AMDGPU; \
- switch(Reg) { \
+ switch(Reg.id()) { \
default: return Reg; \
CASE_CI_VI(FLAT_SCR) \
CASE_CI_VI(FLAT_SCR_LO) \
@@ -2287,7 +2287,7 @@ bool isHi16Reg(MCRegister Reg, const MCRegisterInfo &MRI) {
#define CASE_GFXPRE11_GFX11PLUS_TO(node, result) \
case node: return isGFX11Plus(STI) ? result##_gfx11plus : result##_gfxpre11;
-unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI) {
+MCRegister getMCReg(MCRegister Reg, const MCSubtargetInfo &STI) {
if (STI.getTargetTriple().getArch() == Triple::r600)
return Reg;
MAP_REG2REG
@@ -2303,9 +2303,7 @@ unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI) {
#define CASE_GFXPRE11_GFX11PLUS(node) case node##_gfx11plus: case node##_gfxpre11: return node;
#define CASE_GFXPRE11_GFX11PLUS_TO(node, result)
-unsigned mc2PseudoReg(unsigned Reg) {
- MAP_REG2REG
-}
+MCRegister mc2PseudoReg(MCRegister Reg) { MAP_REG2REG }
bool isInlineValue(unsigned Reg) {
switch (Reg) {
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
index da37534f2fa4ff..d1d84394cc0705 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
@@ -1316,18 +1316,18 @@ unsigned hasKernargPreload(const MCSubtargetInfo &STI);
bool hasSMRDSignedImmOffset(const MCSubtargetInfo &ST);
/// Is Reg - scalar register
-bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI);
+bool isSGPR(MCRegister Reg, const MCRegisterInfo *TRI);
/// \returns if \p Reg occupies the high 16-bits of a 32-bit register.
bool isHi16Reg(MCRegister Reg, const MCRegisterInfo &MRI);
/// If \p Reg is a pseudo reg, return the correct hardware register given
/// \p STI otherwise return \p Reg.
-unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
+MCRegister getMCReg(MCRegister Reg, const MCSubtargetInfo &STI);
/// Convert hardware register \p Reg to a pseudo register
LLVM_READNONE
-unsigned mc2PseudoReg(unsigned Reg);
+MCRegister mc2PseudoReg(MCRegister Reg);
LLVM_READNONE
bool isInlineValue(unsigned Reg);
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