[llvm] [RISCV] Add 32 bit GPR sub-register for Zfinx. (PR #108336)

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git-clang-format --diff cca32174fef004aadc177fcde44904e326c639fb aba04177fbc10d4c44075b087c3ca125ed7f0ad0 --extensions cpp -- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp llvm/lib/Target/RISCV/RISCVCallingConv.cpp llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp llvm/lib/Target/RISCV/RISCVInstrInfo.cpp llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
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diff --git a/llvm/lib/Target/RISCV/RISCVCallingConv.cpp b/llvm/lib/Target/RISCV/RISCVCallingConv.cpp
index 4bc74b0cbd..7038d4e261 100644
--- a/llvm/lib/Target/RISCV/RISCVCallingConv.cpp
+++ b/llvm/lib/Target/RISCV/RISCVCallingConv.cpp
@@ -783,8 +783,7 @@ bool llvm::CC_RISCV_GHC(unsigned ValNo, MVT ValVT, MVT LocVT,
     }
   }
 
-  if (LocVT == MVT::f64 && Subtarget.hasStdExtZdinx() &&
-       Subtarget.is64Bit()) {
+  if (LocVT == MVT::f64 && Subtarget.hasStdExtZdinx() && Subtarget.is64Bit()) {
     if (MCRegister Reg = State.AllocateReg(GPRList)) {
       State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
       return false;

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https://github.com/llvm/llvm-project/pull/108336