[llvm] SelectionDAG/expandFMINNUM_FMAXNUM: skips vector if Op is legal for elements (PR #109570)

[YunQiang Su via llvm-commits]

================
@@ -8485,6 +8485,11 @@ SDValue TargetLowering::expandFMINNUM_FMAXNUM(SDNode *Node,
                          Node->getOperand(1), Node->getFlags());
   }
 
+  // If we have INSN fitting this operation strictly for the elements of the
+  // vector, normally, splitting it is better than compare+select.
+  if (VT.isVector() && isOperationLegal(Node->getOpcode(), VT.getScalarType()))
+    return SDValue();
----------------
wzssyqa wrote:

Do you mean something like
```
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index a2a232ed93b7..2c9fb4961df3 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -8424,6 +8424,9 @@ TargetLowering::createSelectForFMINNUM_FMAXNUM(SDNode *Node,
 
   if (Node->getFlags().hasNoNaNs()) {
     ISD::CondCode Pred = Opcode == ISD::FMINNUM ? ISD::SETLT : ISD::SETGT;
+    EVT VT = Node->getValueType(0);
+    if (!isOperationLegal(Pred, VT) && VT.isVector() && isOperationLegal(Node->getOpcode(), VT.getScalarType()))
+      return SDValue();
     SDValue Op1 = Node->getOperand(0);
     SDValue Op2 = Node->getOperand(1);
     SDValue SelCC = DAG.getSelectCC(SDLoc(Node), Op1, Op2, Op1, Op2, Pred);
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 1733424a8b66..208ebff5882b 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -894,6 +894,9 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
     setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
     setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
     setOperationAction(ISD::FMA, MVT::v2f64, Expand);
+
+    for(unsigned int i = 0; i < ISD::SETCC_INVALID; i++)
+      setOperationAction(i, MVT::v2f64, Expand);
   }
 
   if (Subtarget->hasNEON()) {
@@ -915,6 +918,8 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
     setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
     setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
     setOperationAction(ISD::FFLOOR, MVT::v4f32, Expand);
+    for(unsigned int i = 0; i < ISD::SETCC_INVALID; i++)
+      setOperationAction(i, MVT::v4f32, Expand);
 
     // Mark v2f32 intrinsics.
     setOperationAction(ISD::FSQRT, MVT::v2f32, Expand);
@@ -933,6 +938,8 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
     setOperationAction(ISD::FRINT, MVT::v2f32, Expand);
     setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Expand);
     setOperationAction(ISD::FFLOOR, MVT::v2f32, Expand);
+    for(unsigned int i = 0; i < ISD::SETCC_INVALID; i++)
+      setOperationAction(i, MVT::v2f32, Expand);
 
     // Neon does not support some operations on v1i64 and v2i64 types.
     setOperationAction(ISD::MUL, MVT::v1i64, Expand);
```

https://github.com/llvm/llvm-project/pull/109570