[llvm] [RISCV] Add 32 bit GPR sub-register for Zfinx. (PR #108336)

[Yingwei Zheng via llvm-commits]

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@@ -306,6 +305,19 @@ def FLW : FPLoad_r<0b010, "flw", FPR32, WriteFLD32>;
 def FSW : FPStore_r<0b010, "fsw", FPR32, WriteFST32>;
 } // Predicates = [HasStdExtF]
 
+let Predicates = [HasStdExtZfinx], isCodeGenOnly = 1 in {
+def LW_INX : Load_ri<0b010, "lw", GPRF32>, Sched<[WriteLDW, ReadMemBase]>;
+def SW_INX : Store_rri<0b010, "sw", GPRF32>,
+             Sched<[WriteSTW, ReadStoreData, ReadMemBase]>;
+
+// ADDI with GPRF16 register class to use for copy. This should not be used as
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dtcxzyw wrote:

```suggestion
// ADDI with GPRF32 register class to use for copy. This should not be used as
```

https://github.com/llvm/llvm-project/pull/108336