[llvm] [AMDGPU][GlobalISel] Align `selectVOP3PMadMixModsImpl` with the `SelectionDAG` counterpart (PR #110168)

[Shilei Tian via llvm-commits]

shiltian wrote:

I added the following code into `selectVOP3PMadMixModsExt` and `selectVOP3PMadMixMods`. Not sure if this is what you suggested, but it's not able to fix the issue.

```
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index febf0711c7d5..d95e0ee944bf 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -5366,6 +5366,13 @@ AMDGPUInstructionSelector::selectVOP3PMadMixModsExt(
   if (!Matched)
     return {};
 
+  const TargetRegisterClass *SrcRC =
+      TRI.getConstrainedRegClassForOperand(Root, *MRI);
+  const TargetRegisterClass *VGPRSrc =
+      TRI.getVGPRClassForBitWidth(AMDGPU::getRegBitWidth(SrcRC->getID()));
+  MachineInstr *I = Root.getParent();
+  Src = constrainOperandRegClass(*MF, TRI, *MRI, TII, RBI, *I, *VGPRSrc, Root);
+
   return {{
       [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); },
       [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods
@@ -5379,6 +5386,13 @@ AMDGPUInstructionSelector::selectVOP3PMadMixMods(MachineOperand &Root) const {
   bool Matched;
   std::tie(Src, Mods) = selectVOP3PMadMixModsImpl(Root, Matched);
 
+  const TargetRegisterClass *SrcRC =
+      TRI.getConstrainedRegClassForOperand(Root, *MRI);
+  const TargetRegisterClass *VGPRSrc =
+      TRI.getVGPRClassForBitWidth(AMDGPU::getRegBitWidth(SrcRC->getID()));
+  MachineInstr *I = Root.getParent();
+  Src = constrainOperandRegClass(*MF, TRI, *MRI, TII, RBI, *I, *VGPRSrc, Root);
+
   return {{
       [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); },
       [=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); } // src_mods
```

https://github.com/llvm/llvm-project/pull/110168