[llvm] [AArch64][NEON][SVE] Lower i8 to i64 partial reduction to a dot product (PR #110220)

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<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

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``````````bash
git-clang-format --diff fe06a6daae6be85d47cd1e51654e91f9ac6e63d7 58b92fd1b9119e59e36a206e55cb52aaaa674a14 --extensions cpp -- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index af66b6b0e4..1775de31e6 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -21948,14 +21948,14 @@ SDValue tryLowerPartialReductionToDot(SDNode *N,
   // product followed by a zero / sign extension
   if ((ReducedType == MVT::nxv4i64 && MulSrcType == MVT::nxv16i8) ||
       (ReducedType == MVT::v4i64 && MulSrcType == MVT::v16i8)) {
-    EVT ReducedTypeHalved = (ReducedType.isScalableVector()) ? MVT::nxv4i32 : MVT::v4i32;
+    EVT ReducedTypeHalved =
+        (ReducedType.isScalableVector()) ? MVT::nxv4i32 : MVT::v4i32;
 
-    auto Doti32 =
-        DAG.getNode(Opcode, DL, ReducedTypeHalved,
-                    DAG.getConstant(0, DL, ReducedTypeHalved), A, B);
+    auto Doti32 = DAG.getNode(Opcode, DL, ReducedTypeHalved,
+                              DAG.getConstant(0, DL, ReducedTypeHalved), A, B);
     auto Extended = DAG.getSExtOrTrunc(Doti32, DL, ReducedType);
     return DAG.getNode(ISD::ADD, DL, NarrowOp.getValueType(),
-                                  {NarrowOp, Extended});
+                       {NarrowOp, Extended});
   }
 
   return DAG.getNode(Opcode, DL, ReducedType, NarrowOp, A, B);

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https://github.com/llvm/llvm-project/pull/110220