[llvm] [MIPS] Fix miscompiles consecutive half operations (PR #110199)

[via llvm-commits]

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@@ -390,8 +392,8 @@ class TargetRegisterClass;
           DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
                       MachinePointerInfo::getGOT(DAG.getMachineFunction()));
       unsigned LoFlag = IsN32OrN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
-      SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty,
-                               getTargetNode(N, Ty, DAG, LoFlag));
+      SDValue Lo =
+          DAG.getNode(MipsISD::Lo, DL, Ty, getTargetNode(N, Ty, DAG, LoFlag));
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yingopq wrote:

I had used the `git clang-format ` tool before submitting this PR, and it automatically modified the irrelevant code format, so I submitted it together.

https://github.com/llvm/llvm-project/pull/110199