[llvm] af3837c - [AArch64] Use MCRegister. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2024-09-26T22:38:18-07:00
New Revision: af3837cfd98cbd6bc9fb1fb12a20e29211b88280

URL: https://github.com/llvm/llvm-project/commit/af3837cfd98cbd6bc9fb1fb12a20e29211b88280
DIFF: https://github.com/llvm/llvm-project/commit/af3837cfd98cbd6bc9fb1fb12a20e29211b88280.diff

LOG: [AArch64] Use MCRegister. NFC

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
index 97c5f96388abe6..c7f44ec018f5a4 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
@@ -447,10 +447,10 @@ class AArch64MCInstrAnalysis : public MCInstrAnalysis {
     const MCRegisterClass &FPR128RC =
         MRI.getRegClass(AArch64::FPR128RegClassID);
 
-    auto ClearsSuperReg = [=](unsigned RegID) {
+    auto ClearsSuperReg = [=](MCRegister Reg) {
       // An update to the lower 32 bits of a 64 bit integer register is
       // architecturally defined to zero extend the upper 32 bits on a write.
-      if (GPR32RC.contains(RegID))
+      if (GPR32RC.contains(Reg))
         return true;
       // SIMD&FP instructions operating on scalar data only acccess the lower
       // bits of a register, the upper bits are zero extended on a write. For
@@ -458,9 +458,9 @@ class AArch64MCInstrAnalysis : public MCInstrAnalysis {
       // register are zero extended on a write.
       // When VL is higher than 128 bits, any write to a SIMD&FP register sets
       // bits higher than 128 to zero.
-      return FPR8RC.contains(RegID) || FPR16RC.contains(RegID) ||
-             FPR32RC.contains(RegID) || FPR64RC.contains(RegID) ||
-             FPR128RC.contains(RegID);
+      return FPR8RC.contains(Reg) || FPR16RC.contains(Reg) ||
+             FPR32RC.contains(Reg) || FPR64RC.contains(Reg) ||
+             FPR128RC.contains(Reg);
     };
 
     Mask.clearAllBits();