[llvm] 6d6d15b - [X86] Avoid repeated hash lookups (NFC) (#110077)

via llvm-commits llvm-commits at lists.llvm.org
Thu Sep 26 08:00:06 PDT 2024


Author: Kazu Hirata
Date: 2024-09-26T08:00:01-07:00
New Revision: 6d6d15b626a3d6132765a75a103a773b0e45327b

URL: https://github.com/llvm/llvm-project/commit/6d6d15b626a3d6132765a75a103a773b0e45327b
DIFF: https://github.com/llvm/llvm-project/commit/6d6d15b626a3d6132765a75a103a773b0e45327b.diff

LOG: [X86] Avoid repeated hash lookups (NFC) (#110077)

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index d9eedfdfd53a43..73f7f52846f625 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -35451,11 +35451,11 @@ static MachineInstrBuilder createPHIsForCMOVsInSinkBB(
     if (MIIt->getOperand(3).getImm() == OppCC)
       std::swap(Op1Reg, Op2Reg);
 
-    if (RegRewriteTable.contains(Op1Reg))
-      Op1Reg = RegRewriteTable[Op1Reg].first;
+    if (auto It = RegRewriteTable.find(Op1Reg); It != RegRewriteTable.end())
+      Op1Reg = It->second.first;
 
-    if (RegRewriteTable.contains(Op2Reg))
-      Op2Reg = RegRewriteTable[Op2Reg].second;
+    if (auto It = RegRewriteTable.find(Op2Reg); It != RegRewriteTable.end())
+      Op2Reg = It->second.second;
 
     MIB =
         BuildMI(*SinkMBB, SinkInsertionPoint, MIMD, TII->get(X86::PHI), DestReg)


        


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