[llvm] [AMDGPU] Check vector sizes for physical register constraints in inline asm (PR #109955)

[Fabian Ritter via llvm-commits]

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@@ -0,0 +1,114 @@
+; RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s 2>&1 | FileCheck -check-prefix=ERR %s
+
+; Diagnose register constraints that are not wide enough.
+
+; ERR: error: couldn't allocate output register for constraint '{v[8:15]}'
+define <9 x i32> @inline_asm_9xi32_in_8v_def() {
+  %asm = call <9 x i32> asm sideeffect "; def $0", "={v[8:15]}"()
+  ret <9 x i32> %asm
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ritter-x2a wrote:

For the cases here, where I didn't add tests with plain `v` or `s` constraint (that is the virtual case you mean, right?), there is no mismatched size. We have register classes for ranges of 9 and 8 registers defined, so that is what the compiler uses for these cases.
Would you like me to add these cases to the non-error test, or is there a way of requesting exactly 8 or 9 virtual registers that I'm not aware off?

https://github.com/llvm/llvm-project/pull/109955