[llvm] [RISCV] Add lowerVECTOR_SHUFFLEAsCONCAT_VECTORS. (PR #109948)

[Craig Topper via llvm-commits]

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@@ -0,0 +1,32 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple riscv64 -mattr=+v -riscv-v-vector-bits-min=512 -verify-machineinstrs < %s | FileCheck %s
+
+define <16 x float> @test1(<8 x float> %0) {
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topperc wrote:

This also doesn't seem like a RISC-V specific optimization.

https://github.com/llvm/llvm-project/pull/109948