[llvm] [RISCV] Add lowerINSERT_SUBVECTORAsBUILD_VECTOR. (PR #110069)

[Craig Topper via llvm-commits]

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@@ -10140,6 +10140,35 @@ SDValue RISCVTargetLowering::lowerVPREDUCE(SDValue Op,
       DAG.getConstantFP(APFloat::getNaN(ResVT.getFltSemantics()), DL, ResVT));
 }
 
+// Merge BUILD_VECTOR and insert_subvector into BUILD_VECTOR.
+// e.g.,
+// t7: v8i32 = BUILD_VECTOR 0, 0, 0, 0, 0, 0, 0, 0
+// t9: v16i32 = insert_subvector undef:v16i32, t7, i64<8>
+// ->
+// BUILD_VECTOR undef, undef, undef, undef, undef, undef, undef, undef, 0, 0, 0,
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topperc wrote:

Should this be a DAG combine?

https://github.com/llvm/llvm-project/pull/110069