[llvm] cd53c84 - [RISCV] Fix a warning

Kazu Hirata via llvm-commits llvm-commits at lists.llvm.org
Tue Sep 24 16:22:58 PDT 2024


Author: Kazu Hirata
Date: 2024-09-24T16:22:53-07:00
New Revision: cd53c8429efc82c8756d85c23fc347901c3c948d

URL: https://github.com/llvm/llvm-project/commit/cd53c8429efc82c8756d85c23fc347901c3c948d
DIFF: https://github.com/llvm/llvm-project/commit/cd53c8429efc82c8756d85c23fc347901c3c948d.diff

LOG: [RISCV] Fix a warning

This patch fixes:

  llvm/lib/Target/RISCV/RISCVISelLowering.cpp:10479:12: error:
  variable 'SubRegIdx' set but not used
  [-Werror,-Wunused-but-set-variable]

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 1a52f927d69f78..7b00b2514c4ef1 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -10527,6 +10527,7 @@ SDValue RISCVTargetLowering::lowerEXTRACT_SUBVECTOR(SDValue Op,
     // we should have successfully decomposed the extract into a subregister.
     // We use an extract_subvector that will resolve to a subreg extract.
     assert(SubRegIdx != RISCV::NoSubRegister);
+    (void)SubRegIdx;
     unsigned Idx = OrigIdx - RemIdx.getKnownMinValue();
     if (SubVecVT.isFixedLengthVector()) {
       assert(VLen);


        


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