[llvm] [RegisterPressure] NFC: Clean up RP handling for instructions with overlapping Def/Use (PR #109875)

[Jeffrey Byrnes via llvm-commits]

https://github.com/jrbyrnes created https://github.com/llvm/llvm-project/pull/109875

The current RP handling for uses of an MI that overlap with defs is confusing and unnecessary. Moreover, it is incorrect if the RP tracked register by subreg / lane. This cleans it up a bit by snking the use handling into the subsequent use loop (which has more accurate handling if we were to track RP by subreg).

The effect of this PR is to replace

A. `increaseRegPressure(Reg, LiveAfter, ~LiveAfter & LiveBefore)`

with 

B. `increaseRegPressure(Reg, LiveAfter, LiveBefore)`

Note that A and B have different definitions of LiveBefore

A. `LiveBefore = (LiveAfter & ~DefLanes) | UseLanes`

and 

B. `LiveBefore =  LiveAfter | UseLanes`

Also note, `increaseRegPressure` will exit if `PrevMask` (`LiveAfter` for both cases) has any active lanes, thus these calls will only have effect if `LiveAfter` is 0.


A. NewMask = ~LiveAfter & ((LiveAfter & ~DefLanes) | UseLanes) => (1 & UseLanes) => UseLanes = (0 | UseLanes) => (LiveAfter | UseLanes) = NewMask B.

>From fe734447188d3d3d2d94a08ddccfada201711b89 Mon Sep 17 00:00:00 2001
From: Jeffrey Byrnes <Jeffrey.Byrnes at amd.com>
Date: Tue, 24 Sep 2024 14:40:31 -0700
Subject: [PATCH] [RegisterPressure] NFC: Clean up RP handling for instructions
 with overlapping Def/Use

Change-Id: I4edebef95688a9814c46b73166e9ca88a97e5304
---
 llvm/lib/CodeGen/RegisterPressure.cpp | 10 ++--------
 1 file changed, 2 insertions(+), 8 deletions(-)

diff --git a/llvm/lib/CodeGen/RegisterPressure.cpp b/llvm/lib/CodeGen/RegisterPressure.cpp
index 59a1911555e9cd..a517cb9631556e 100644
--- a/llvm/lib/CodeGen/RegisterPressure.cpp
+++ b/llvm/lib/CodeGen/RegisterPressure.cpp
@@ -1060,18 +1060,12 @@ void RegPressureTracker::bumpUpwardPressure(const MachineInstr *MI) {
     LaneBitmask LiveBefore = (LiveAfter & ~DefLanes) | UseLanes;
 
     // There may be parts of the register that were dead before the
-    // instruction, but became live afterwards. Similarly, some parts
-    // may have been killed in this instruction.
+    // instruction, but became live afterwards.
     decreaseRegPressure(Reg, LiveAfter, LiveAfter & LiveBefore);
-    increaseRegPressure(Reg, LiveAfter, ~LiveAfter & LiveBefore);
   }
-  // Generate liveness for uses.
+  // Generate liveness for uses. Also handle any uses which overlap with defs.
   for (const RegisterMaskPair &P : RegOpers.Uses) {
     Register Reg = P.RegUnit;
-    // If this register was also in a def operand, we've handled it
-    // with defs.
-    if (getRegLanes(RegOpers.Defs, Reg).any())
-      continue;
     LaneBitmask LiveAfter = LiveRegs.contains(Reg);
     LaneBitmask LiveBefore = LiveAfter | P.LaneMask;
     increaseRegPressure(Reg, LiveAfter, LiveBefore);