[llvm] ebbf664 - [AMDGPU] Use shared prefix in GFX12 barrier test
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 24 06:20:15 PDT 2024
Author: Jay Foad
Date: 2024-09-24T14:19:51+01:00
New Revision: ebbf664aa31ac51c43a345a8a3d0734c54be7c4b
URL: https://github.com/llvm/llvm-project/commit/ebbf664aa31ac51c43a345a8a3d0734c54be7c4b
DIFF: https://github.com/llvm/llvm-project/commit/ebbf664aa31ac51c43a345a8a3d0734c54be7c4b.diff
LOG: [AMDGPU] Use shared prefix in GFX12 barrier test
Added:
Modified:
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.wait.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.wait.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.wait.ll
index 6e029f7c0a95e5..a4be9ed8c2b4af 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.wait.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.wait.ll
@@ -1,43 +1,43 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -check-prefixes=GLOBAL-ISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s
define amdgpu_kernel void @test1_s_barrier_signal(ptr addrspace(1) %out) #0 {
-; GCN-LABEL: test1_s_barrier_signal:
-; GCN: ; %bb.0: ; %entry
-; GCN-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
-; GCN-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GCN-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
-; GCN-NEXT: v_mul_u32_u24_e32 v1, v0, v0
-; GCN-NEXT: v_sub_nc_u32_e32 v0, v1, v0
-; GCN-NEXT: s_wait_kmcnt 0x0
-; GCN-NEXT: global_store_b32 v3, v2, s[0:1]
-; GCN-NEXT: s_wait_storecnt 0x0
-; GCN-NEXT: s_barrier_signal -1
-; GCN-NEXT: s_barrier_wait -1
-; GCN-NEXT: global_store_b32 v3, v0, s[0:1]
-; GCN-NEXT: s_nop 0
-; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GCN-NEXT: s_endpgm
+; GFX12-SDAG-LABEL: test1_s_barrier_signal:
+; GFX12-SDAG: ; %bb.0: ; %entry
+; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
+; GFX12-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
+; GFX12-SDAG-NEXT: v_mul_u32_u24_e32 v1, v0, v0
+; GFX12-SDAG-NEXT: v_sub_nc_u32_e32 v0, v1, v0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: global_store_b32 v3, v2, s[0:1]
+; GFX12-SDAG-NEXT: s_wait_storecnt 0x0
+; GFX12-SDAG-NEXT: s_barrier_signal -1
+; GFX12-SDAG-NEXT: s_barrier_wait -1
+; GFX12-SDAG-NEXT: global_store_b32 v3, v0, s[0:1]
+; GFX12-SDAG-NEXT: s_nop 0
+; GFX12-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-SDAG-NEXT: s_endpgm
;
-; GLOBAL-ISEL-LABEL: test1_s_barrier_signal:
-; GLOBAL-ISEL: ; %bb.0: ; %entry
-; GLOBAL-ISEL-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
-; GLOBAL-ISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GLOBAL-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
-; GLOBAL-ISEL-NEXT: v_mul_lo_u32 v1, v0, v0
-; GLOBAL-ISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0
-; GLOBAL-ISEL-NEXT: s_wait_kmcnt 0x0
-; GLOBAL-ISEL-NEXT: global_store_b32 v3, v2, s[0:1]
-; GLOBAL-ISEL-NEXT: s_wait_storecnt 0x0
-; GLOBAL-ISEL-NEXT: s_barrier_signal -1
-; GLOBAL-ISEL-NEXT: s_barrier_wait -1
-; GLOBAL-ISEL-NEXT: global_store_b32 v3, v0, s[0:1]
-; GLOBAL-ISEL-NEXT: s_nop 0
-; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GLOBAL-ISEL-NEXT: s_endpgm
+; GFX12-GISEL-LABEL: test1_s_barrier_signal:
+; GFX12-GISEL: ; %bb.0: ; %entry
+; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
+; GFX12-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
+; GFX12-GISEL-NEXT: v_mul_lo_u32 v1, v0, v0
+; GFX12-GISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: global_store_b32 v3, v2, s[0:1]
+; GFX12-GISEL-NEXT: s_wait_storecnt 0x0
+; GFX12-GISEL-NEXT: s_barrier_signal -1
+; GFX12-GISEL-NEXT: s_barrier_wait -1
+; GFX12-GISEL-NEXT: global_store_b32 v3, v0, s[0:1]
+; GFX12-GISEL-NEXT: s_nop 0
+; GFX12-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-GISEL-NEXT: s_endpgm
entry:
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
%tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp
@@ -51,41 +51,41 @@ entry:
}
define amdgpu_kernel void @test2_s_barrier_signal(ptr addrspace(1) %out) #0 {
-; GCN-LABEL: test2_s_barrier_signal:
-; GCN: ; %bb.0: ; %entry
-; GCN-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
-; GCN-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GCN-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
-; GCN-NEXT: v_mul_u32_u24_e32 v1, v0, v0
-; GCN-NEXT: v_sub_nc_u32_e32 v0, v1, v0
-; GCN-NEXT: s_wait_kmcnt 0x0
-; GCN-NEXT: global_store_b32 v3, v2, s[0:1]
-; GCN-NEXT: s_wait_storecnt 0x0
-; GCN-NEXT: s_barrier_signal 1
-; GCN-NEXT: s_barrier_wait 1
-; GCN-NEXT: global_store_b32 v3, v0, s[0:1]
-; GCN-NEXT: s_nop 0
-; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GCN-NEXT: s_endpgm
+; GFX12-SDAG-LABEL: test2_s_barrier_signal:
+; GFX12-SDAG: ; %bb.0: ; %entry
+; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
+; GFX12-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
+; GFX12-SDAG-NEXT: v_mul_u32_u24_e32 v1, v0, v0
+; GFX12-SDAG-NEXT: v_sub_nc_u32_e32 v0, v1, v0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: global_store_b32 v3, v2, s[0:1]
+; GFX12-SDAG-NEXT: s_wait_storecnt 0x0
+; GFX12-SDAG-NEXT: s_barrier_signal 1
+; GFX12-SDAG-NEXT: s_barrier_wait 1
+; GFX12-SDAG-NEXT: global_store_b32 v3, v0, s[0:1]
+; GFX12-SDAG-NEXT: s_nop 0
+; GFX12-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-SDAG-NEXT: s_endpgm
;
-; GLOBAL-ISEL-LABEL: test2_s_barrier_signal:
-; GLOBAL-ISEL: ; %bb.0: ; %entry
-; GLOBAL-ISEL-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
-; GLOBAL-ISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GLOBAL-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
-; GLOBAL-ISEL-NEXT: v_mul_lo_u32 v1, v0, v0
-; GLOBAL-ISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0
-; GLOBAL-ISEL-NEXT: s_wait_kmcnt 0x0
-; GLOBAL-ISEL-NEXT: global_store_b32 v3, v2, s[0:1]
-; GLOBAL-ISEL-NEXT: s_wait_storecnt 0x0
-; GLOBAL-ISEL-NEXT: s_barrier_signal 1
-; GLOBAL-ISEL-NEXT: s_barrier_wait 1
-; GLOBAL-ISEL-NEXT: global_store_b32 v3, v0, s[0:1]
-; GLOBAL-ISEL-NEXT: s_nop 0
-; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GLOBAL-ISEL-NEXT: s_endpgm
+; GFX12-GISEL-LABEL: test2_s_barrier_signal:
+; GFX12-GISEL: ; %bb.0: ; %entry
+; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
+; GFX12-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
+; GFX12-GISEL-NEXT: v_mul_lo_u32 v1, v0, v0
+; GFX12-GISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: global_store_b32 v3, v2, s[0:1]
+; GFX12-GISEL-NEXT: s_wait_storecnt 0x0
+; GFX12-GISEL-NEXT: s_barrier_signal 1
+; GFX12-GISEL-NEXT: s_barrier_wait 1
+; GFX12-GISEL-NEXT: global_store_b32 v3, v0, s[0:1]
+; GFX12-GISEL-NEXT: s_nop 0
+; GFX12-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-GISEL-NEXT: s_endpgm
entry:
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
%tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp
@@ -99,41 +99,41 @@ entry:
}
define amdgpu_kernel void @test3_s_barrier_signal(ptr addrspace(1) %out) #0 {
-; GCN-LABEL: test3_s_barrier_signal:
-; GCN: ; %bb.0: ; %entry
-; GCN-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
-; GCN-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GCN-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
-; GCN-NEXT: v_mul_u32_u24_e32 v1, v0, v0
-; GCN-NEXT: v_sub_nc_u32_e32 v0, v1, v0
-; GCN-NEXT: s_wait_kmcnt 0x0
-; GCN-NEXT: global_store_b32 v3, v2, s[0:1]
-; GCN-NEXT: s_wait_storecnt 0x0
-; GCN-NEXT: s_barrier_signal 0
-; GCN-NEXT: s_barrier_wait 0
-; GCN-NEXT: global_store_b32 v3, v0, s[0:1]
-; GCN-NEXT: s_nop 0
-; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GCN-NEXT: s_endpgm
+; GFX12-SDAG-LABEL: test3_s_barrier_signal:
+; GFX12-SDAG: ; %bb.0: ; %entry
+; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
+; GFX12-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
+; GFX12-SDAG-NEXT: v_mul_u32_u24_e32 v1, v0, v0
+; GFX12-SDAG-NEXT: v_sub_nc_u32_e32 v0, v1, v0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: global_store_b32 v3, v2, s[0:1]
+; GFX12-SDAG-NEXT: s_wait_storecnt 0x0
+; GFX12-SDAG-NEXT: s_barrier_signal 0
+; GFX12-SDAG-NEXT: s_barrier_wait 0
+; GFX12-SDAG-NEXT: global_store_b32 v3, v0, s[0:1]
+; GFX12-SDAG-NEXT: s_nop 0
+; GFX12-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-SDAG-NEXT: s_endpgm
;
-; GLOBAL-ISEL-LABEL: test3_s_barrier_signal:
-; GLOBAL-ISEL: ; %bb.0: ; %entry
-; GLOBAL-ISEL-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
-; GLOBAL-ISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GLOBAL-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
-; GLOBAL-ISEL-NEXT: v_mul_lo_u32 v1, v0, v0
-; GLOBAL-ISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0
-; GLOBAL-ISEL-NEXT: s_wait_kmcnt 0x0
-; GLOBAL-ISEL-NEXT: global_store_b32 v3, v2, s[0:1]
-; GLOBAL-ISEL-NEXT: s_wait_storecnt 0x0
-; GLOBAL-ISEL-NEXT: s_barrier_signal 0
-; GLOBAL-ISEL-NEXT: s_barrier_wait 0
-; GLOBAL-ISEL-NEXT: global_store_b32 v3, v0, s[0:1]
-; GLOBAL-ISEL-NEXT: s_nop 0
-; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GLOBAL-ISEL-NEXT: s_endpgm
+; GFX12-GISEL-LABEL: test3_s_barrier_signal:
+; GFX12-GISEL: ; %bb.0: ; %entry
+; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
+; GFX12-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
+; GFX12-GISEL-NEXT: v_mul_lo_u32 v1, v0, v0
+; GFX12-GISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: global_store_b32 v3, v2, s[0:1]
+; GFX12-GISEL-NEXT: s_wait_storecnt 0x0
+; GFX12-GISEL-NEXT: s_barrier_signal 0
+; GFX12-GISEL-NEXT: s_barrier_wait 0
+; GFX12-GISEL-NEXT: global_store_b32 v3, v0, s[0:1]
+; GFX12-GISEL-NEXT: s_nop 0
+; GFX12-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-GISEL-NEXT: s_endpgm
entry:
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
%tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp
@@ -147,44 +147,44 @@ entry:
}
define amdgpu_kernel void @test1_s_barrier_signal_var(ptr addrspace(1) %out) #0 {
-; GCN-LABEL: test1_s_barrier_signal_var:
-; GCN: ; %bb.0: ; %entry
-; GCN-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
-; GCN-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
-; GCN-NEXT: s_mov_b32 m0, 1
-; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GCN-NEXT: v_mul_u32_u24_e32 v2, v0, v0
-; GCN-NEXT: v_lshlrev_b32_e32 v3, 2, v0
-; GCN-NEXT: v_sub_nc_u32_e32 v0, v2, v0
-; GCN-NEXT: s_wait_kmcnt 0x0
-; GCN-NEXT: global_store_b32 v3, v1, s[0:1]
-; GCN-NEXT: s_wait_storecnt 0x0
-; GCN-NEXT: s_barrier_signal m0
-; GCN-NEXT: s_barrier_wait 1
-; GCN-NEXT: global_store_b32 v3, v0, s[0:1]
-; GCN-NEXT: s_nop 0
-; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GCN-NEXT: s_endpgm
+; GFX12-SDAG-LABEL: test1_s_barrier_signal_var:
+; GFX12-SDAG: ; %bb.0: ; %entry
+; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
+; GFX12-SDAG-NEXT: s_mov_b32 m0, 1
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-NEXT: v_mul_u32_u24_e32 v2, v0, v0
+; GFX12-SDAG-NEXT: v_lshlrev_b32_e32 v3, 2, v0
+; GFX12-SDAG-NEXT: v_sub_nc_u32_e32 v0, v2, v0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: global_store_b32 v3, v1, s[0:1]
+; GFX12-SDAG-NEXT: s_wait_storecnt 0x0
+; GFX12-SDAG-NEXT: s_barrier_signal m0
+; GFX12-SDAG-NEXT: s_barrier_wait 1
+; GFX12-SDAG-NEXT: global_store_b32 v3, v0, s[0:1]
+; GFX12-SDAG-NEXT: s_nop 0
+; GFX12-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-SDAG-NEXT: s_endpgm
;
-; GLOBAL-ISEL-LABEL: test1_s_barrier_signal_var:
-; GLOBAL-ISEL: ; %bb.0: ; %entry
-; GLOBAL-ISEL-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
-; GLOBAL-ISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GLOBAL-ISEL-NEXT: v_mov_b32_e32 v2, 0
-; GLOBAL-ISEL-NEXT: s_mov_b32 m0, 1
-; GLOBAL-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GLOBAL-ISEL-NEXT: v_lshlrev_b32_e32 v3, 2, v0
-; GLOBAL-ISEL-NEXT: v_mul_lo_u32 v1, v0, v0
-; GLOBAL-ISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0
-; GLOBAL-ISEL-NEXT: s_wait_kmcnt 0x0
-; GLOBAL-ISEL-NEXT: global_store_b32 v3, v2, s[0:1]
-; GLOBAL-ISEL-NEXT: s_wait_storecnt 0x0
-; GLOBAL-ISEL-NEXT: s_barrier_signal m0
-; GLOBAL-ISEL-NEXT: s_barrier_wait 1
-; GLOBAL-ISEL-NEXT: global_store_b32 v3, v0, s[0:1]
-; GLOBAL-ISEL-NEXT: s_nop 0
-; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GLOBAL-ISEL-NEXT: s_endpgm
+; GFX12-GISEL-LABEL: test1_s_barrier_signal_var:
+; GFX12-GISEL: ; %bb.0: ; %entry
+; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
+; GFX12-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX12-GISEL-NEXT: s_mov_b32 m0, 1
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_lshlrev_b32_e32 v3, 2, v0
+; GFX12-GISEL-NEXT: v_mul_lo_u32 v1, v0, v0
+; GFX12-GISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: global_store_b32 v3, v2, s[0:1]
+; GFX12-GISEL-NEXT: s_wait_storecnt 0x0
+; GFX12-GISEL-NEXT: s_barrier_signal m0
+; GFX12-GISEL-NEXT: s_barrier_wait 1
+; GFX12-GISEL-NEXT: global_store_b32 v3, v0, s[0:1]
+; GFX12-GISEL-NEXT: s_nop 0
+; GFX12-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-GISEL-NEXT: s_endpgm
entry:
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
%tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp
@@ -198,83 +198,83 @@ entry:
}
define void @test2_s_barrier_signal_var(i32 %arg) {
-; GCN-LABEL: test2_s_barrier_signal_var:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_wait_loadcnt_dscnt 0x0
-; GCN-NEXT: s_wait_expcnt 0x0
-; GCN-NEXT: s_wait_samplecnt 0x0
-; GCN-NEXT: s_wait_bvhcnt 0x0
-; GCN-NEXT: s_wait_kmcnt 0x0
-; GCN-NEXT: v_readfirstlane_b32 s0, v0
-; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GCN-NEXT: s_mov_b32 m0, s0
-; GCN-NEXT: s_wait_storecnt 0x0
-; GCN-NEXT: s_barrier_signal m0
-; GCN-NEXT: s_wait_alu 0xfffe
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; GFX12-SDAG-LABEL: test2_s_barrier_signal_var:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-NEXT: s_mov_b32 m0, s0
+; GFX12-SDAG-NEXT: s_wait_storecnt 0x0
+; GFX12-SDAG-NEXT: s_barrier_signal m0
+; GFX12-SDAG-NEXT: s_wait_alu 0xfffe
+; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GLOBAL-ISEL-LABEL: test2_s_barrier_signal_var:
-; GLOBAL-ISEL: ; %bb.0:
-; GLOBAL-ISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GLOBAL-ISEL-NEXT: s_wait_expcnt 0x0
-; GLOBAL-ISEL-NEXT: s_wait_samplecnt 0x0
-; GLOBAL-ISEL-NEXT: s_wait_bvhcnt 0x0
-; GLOBAL-ISEL-NEXT: s_wait_kmcnt 0x0
-; GLOBAL-ISEL-NEXT: v_readfirstlane_b32 m0, v0
-; GLOBAL-ISEL-NEXT: s_wait_storecnt 0x0
-; GLOBAL-ISEL-NEXT: s_barrier_signal m0
-; GLOBAL-ISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX12-GISEL-LABEL: test2_s_barrier_signal_var:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 m0, v0
+; GFX12-GISEL-NEXT: s_wait_storecnt 0x0
+; GFX12-GISEL-NEXT: s_barrier_signal m0
+; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
call void @llvm.amdgcn.s.barrier.signal.var(i32 %arg)
ret void
}
define amdgpu_kernel void @test1_s_barrier_signal_isfirst(ptr addrspace(1) %a, ptr addrspace(1) %b, ptr addrspace(1) %c, ptr addrspace(1) %out) #0 {
-; GCN-LABEL: test1_s_barrier_signal_isfirst:
-; GCN: ; %bb.0: ; %entry
-; GCN-NEXT: s_load_b256 s[0:7], s[2:3], 0x24
-; GCN-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
-; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GCN-NEXT: s_wait_kmcnt 0x0
-; GCN-NEXT: global_store_b32 v0, v1, s[6:7]
-; GCN-NEXT: s_wait_storecnt 0x0
-; GCN-NEXT: s_barrier_signal_isfirst -1
-; GCN-NEXT: s_cselect_b32 s3, s3, s5
-; GCN-NEXT: s_cselect_b32 s2, s2, s4
-; GCN-NEXT: s_clause 0x1
-; GCN-NEXT: global_load_b32 v2, v1, s[0:1]
-; GCN-NEXT: global_load_b32 v1, v1, s[2:3]
-; GCN-NEXT: s_wait_loadcnt 0x0
-; GCN-NEXT: v_mul_lo_u32 v1, v1, v2
-; GCN-NEXT: global_store_b32 v0, v1, s[6:7]
-; GCN-NEXT: s_nop 0
-; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GCN-NEXT: s_endpgm
+; GFX12-SDAG-LABEL: test1_s_barrier_signal_isfirst:
+; GFX12-SDAG: ; %bb.0: ; %entry
+; GFX12-SDAG-NEXT: s_load_b256 s[0:7], s[2:3], 0x24
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: global_store_b32 v0, v1, s[6:7]
+; GFX12-SDAG-NEXT: s_wait_storecnt 0x0
+; GFX12-SDAG-NEXT: s_barrier_signal_isfirst -1
+; GFX12-SDAG-NEXT: s_cselect_b32 s3, s3, s5
+; GFX12-SDAG-NEXT: s_cselect_b32 s2, s2, s4
+; GFX12-SDAG-NEXT: s_clause 0x1
+; GFX12-SDAG-NEXT: global_load_b32 v2, v1, s[0:1]
+; GFX12-SDAG-NEXT: global_load_b32 v1, v1, s[2:3]
+; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX12-SDAG-NEXT: v_mul_lo_u32 v1, v1, v2
+; GFX12-SDAG-NEXT: global_store_b32 v0, v1, s[6:7]
+; GFX12-SDAG-NEXT: s_nop 0
+; GFX12-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-SDAG-NEXT: s_endpgm
;
-; GLOBAL-ISEL-LABEL: test1_s_barrier_signal_isfirst:
-; GLOBAL-ISEL: ; %bb.0: ; %entry
-; GLOBAL-ISEL-NEXT: s_load_b256 s[0:7], s[2:3], 0x24
-; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
-; GLOBAL-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GLOBAL-ISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GLOBAL-ISEL-NEXT: s_wait_kmcnt 0x0
-; GLOBAL-ISEL-NEXT: global_store_b32 v0, v1, s[6:7]
-; GLOBAL-ISEL-NEXT: s_wait_storecnt 0x0
-; GLOBAL-ISEL-NEXT: s_barrier_signal_isfirst -1
-; GLOBAL-ISEL-NEXT: s_cselect_b32 s8, 1, 0
-; GLOBAL-ISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GLOBAL-ISEL-NEXT: s_and_b32 s8, s8, 1
-; GLOBAL-ISEL-NEXT: s_cmp_lg_u32 s8, 0
-; GLOBAL-ISEL-NEXT: s_cselect_b64 s[2:3], s[2:3], s[4:5]
-; GLOBAL-ISEL-NEXT: s_clause 0x1
-; GLOBAL-ISEL-NEXT: global_load_b32 v2, v1, s[0:1]
-; GLOBAL-ISEL-NEXT: global_load_b32 v1, v1, s[2:3]
-; GLOBAL-ISEL-NEXT: s_wait_loadcnt 0x0
-; GLOBAL-ISEL-NEXT: v_mul_lo_u32 v1, v1, v2
-; GLOBAL-ISEL-NEXT: global_store_b32 v0, v1, s[6:7]
-; GLOBAL-ISEL-NEXT: s_nop 0
-; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GLOBAL-ISEL-NEXT: s_endpgm
+; GFX12-GISEL-LABEL: test1_s_barrier_signal_isfirst:
+; GFX12-GISEL: ; %bb.0: ; %entry
+; GFX12-GISEL-NEXT: s_load_b256 s[0:7], s[2:3], 0x24
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: global_store_b32 v0, v1, s[6:7]
+; GFX12-GISEL-NEXT: s_wait_storecnt 0x0
+; GFX12-GISEL-NEXT: s_barrier_signal_isfirst -1
+; GFX12-GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX12-GISEL-NEXT: s_and_b32 s8, s8, 1
+; GFX12-GISEL-NEXT: s_cmp_lg_u32 s8, 0
+; GFX12-GISEL-NEXT: s_cselect_b64 s[2:3], s[2:3], s[4:5]
+; GFX12-GISEL-NEXT: s_clause 0x1
+; GFX12-GISEL-NEXT: global_load_b32 v2, v1, s[0:1]
+; GFX12-GISEL-NEXT: global_load_b32 v1, v1, s[2:3]
+; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX12-GISEL-NEXT: v_mul_lo_u32 v1, v1, v2
+; GFX12-GISEL-NEXT: global_store_b32 v0, v1, s[6:7]
+; GFX12-GISEL-NEXT: s_nop 0
+; GFX12-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-GISEL-NEXT: s_endpgm
entry:
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
%tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp
@@ -289,52 +289,52 @@ entry:
}
define amdgpu_kernel void @test2_s_barrier_signal_isfirst(ptr addrspace(1) %a, ptr addrspace(1) %b, ptr addrspace(1) %c, ptr addrspace(1) %out) #0 {
-; GCN-LABEL: test2_s_barrier_signal_isfirst:
-; GCN: ; %bb.0: ; %entry
-; GCN-NEXT: s_load_b256 s[0:7], s[2:3], 0x24
-; GCN-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
-; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GCN-NEXT: s_wait_kmcnt 0x0
-; GCN-NEXT: global_store_b32 v0, v1, s[6:7]
-; GCN-NEXT: s_wait_storecnt 0x0
-; GCN-NEXT: s_barrier_signal_isfirst 1
-; GCN-NEXT: s_cselect_b32 s3, s3, s5
-; GCN-NEXT: s_cselect_b32 s2, s2, s4
-; GCN-NEXT: s_clause 0x1
-; GCN-NEXT: global_load_b32 v2, v1, s[0:1]
-; GCN-NEXT: global_load_b32 v1, v1, s[2:3]
-; GCN-NEXT: s_wait_loadcnt 0x0
-; GCN-NEXT: v_mul_lo_u32 v1, v1, v2
-; GCN-NEXT: global_store_b32 v0, v1, s[6:7]
-; GCN-NEXT: s_nop 0
-; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GCN-NEXT: s_endpgm
+; GFX12-SDAG-LABEL: test2_s_barrier_signal_isfirst:
+; GFX12-SDAG: ; %bb.0: ; %entry
+; GFX12-SDAG-NEXT: s_load_b256 s[0:7], s[2:3], 0x24
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: global_store_b32 v0, v1, s[6:7]
+; GFX12-SDAG-NEXT: s_wait_storecnt 0x0
+; GFX12-SDAG-NEXT: s_barrier_signal_isfirst 1
+; GFX12-SDAG-NEXT: s_cselect_b32 s3, s3, s5
+; GFX12-SDAG-NEXT: s_cselect_b32 s2, s2, s4
+; GFX12-SDAG-NEXT: s_clause 0x1
+; GFX12-SDAG-NEXT: global_load_b32 v2, v1, s[0:1]
+; GFX12-SDAG-NEXT: global_load_b32 v1, v1, s[2:3]
+; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX12-SDAG-NEXT: v_mul_lo_u32 v1, v1, v2
+; GFX12-SDAG-NEXT: global_store_b32 v0, v1, s[6:7]
+; GFX12-SDAG-NEXT: s_nop 0
+; GFX12-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-SDAG-NEXT: s_endpgm
;
-; GLOBAL-ISEL-LABEL: test2_s_barrier_signal_isfirst:
-; GLOBAL-ISEL: ; %bb.0: ; %entry
-; GLOBAL-ISEL-NEXT: s_load_b256 s[0:7], s[2:3], 0x24
-; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
-; GLOBAL-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GLOBAL-ISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GLOBAL-ISEL-NEXT: s_wait_kmcnt 0x0
-; GLOBAL-ISEL-NEXT: global_store_b32 v0, v1, s[6:7]
-; GLOBAL-ISEL-NEXT: s_wait_storecnt 0x0
-; GLOBAL-ISEL-NEXT: s_barrier_signal_isfirst 1
-; GLOBAL-ISEL-NEXT: s_cselect_b32 s8, 1, 0
-; GLOBAL-ISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GLOBAL-ISEL-NEXT: s_and_b32 s8, s8, 1
-; GLOBAL-ISEL-NEXT: s_cmp_lg_u32 s8, 0
-; GLOBAL-ISEL-NEXT: s_cselect_b64 s[2:3], s[2:3], s[4:5]
-; GLOBAL-ISEL-NEXT: s_clause 0x1
-; GLOBAL-ISEL-NEXT: global_load_b32 v2, v1, s[0:1]
-; GLOBAL-ISEL-NEXT: global_load_b32 v1, v1, s[2:3]
-; GLOBAL-ISEL-NEXT: s_wait_loadcnt 0x0
-; GLOBAL-ISEL-NEXT: v_mul_lo_u32 v1, v1, v2
-; GLOBAL-ISEL-NEXT: global_store_b32 v0, v1, s[6:7]
-; GLOBAL-ISEL-NEXT: s_nop 0
-; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GLOBAL-ISEL-NEXT: s_endpgm
+; GFX12-GISEL-LABEL: test2_s_barrier_signal_isfirst:
+; GFX12-GISEL: ; %bb.0: ; %entry
+; GFX12-GISEL-NEXT: s_load_b256 s[0:7], s[2:3], 0x24
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: global_store_b32 v0, v1, s[6:7]
+; GFX12-GISEL-NEXT: s_wait_storecnt 0x0
+; GFX12-GISEL-NEXT: s_barrier_signal_isfirst 1
+; GFX12-GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX12-GISEL-NEXT: s_and_b32 s8, s8, 1
+; GFX12-GISEL-NEXT: s_cmp_lg_u32 s8, 0
+; GFX12-GISEL-NEXT: s_cselect_b64 s[2:3], s[2:3], s[4:5]
+; GFX12-GISEL-NEXT: s_clause 0x1
+; GFX12-GISEL-NEXT: global_load_b32 v2, v1, s[0:1]
+; GFX12-GISEL-NEXT: global_load_b32 v1, v1, s[2:3]
+; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX12-GISEL-NEXT: v_mul_lo_u32 v1, v1, v2
+; GFX12-GISEL-NEXT: global_store_b32 v0, v1, s[6:7]
+; GFX12-GISEL-NEXT: s_nop 0
+; GFX12-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-GISEL-NEXT: s_endpgm
entry:
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
%tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp
@@ -349,52 +349,52 @@ entry:
}
define amdgpu_kernel void @test3_s_barrier_signal_isfirst(ptr addrspace(1) %a, ptr addrspace(1) %b, ptr addrspace(1) %c, ptr addrspace(1) %out) #0 {
-; GCN-LABEL: test3_s_barrier_signal_isfirst:
-; GCN: ; %bb.0: ; %entry
-; GCN-NEXT: s_load_b256 s[0:7], s[2:3], 0x24
-; GCN-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
-; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GCN-NEXT: s_wait_kmcnt 0x0
-; GCN-NEXT: global_store_b32 v0, v1, s[6:7]
-; GCN-NEXT: s_wait_storecnt 0x0
-; GCN-NEXT: s_barrier_signal_isfirst 1
-; GCN-NEXT: s_cselect_b32 s3, s3, s5
-; GCN-NEXT: s_cselect_b32 s2, s2, s4
-; GCN-NEXT: s_clause 0x1
-; GCN-NEXT: global_load_b32 v2, v1, s[0:1]
-; GCN-NEXT: global_load_b32 v1, v1, s[2:3]
-; GCN-NEXT: s_wait_loadcnt 0x0
-; GCN-NEXT: v_mul_lo_u32 v1, v1, v2
-; GCN-NEXT: global_store_b32 v0, v1, s[6:7]
-; GCN-NEXT: s_nop 0
-; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GCN-NEXT: s_endpgm
+; GFX12-SDAG-LABEL: test3_s_barrier_signal_isfirst:
+; GFX12-SDAG: ; %bb.0: ; %entry
+; GFX12-SDAG-NEXT: s_load_b256 s[0:7], s[2:3], 0x24
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: global_store_b32 v0, v1, s[6:7]
+; GFX12-SDAG-NEXT: s_wait_storecnt 0x0
+; GFX12-SDAG-NEXT: s_barrier_signal_isfirst 1
+; GFX12-SDAG-NEXT: s_cselect_b32 s3, s3, s5
+; GFX12-SDAG-NEXT: s_cselect_b32 s2, s2, s4
+; GFX12-SDAG-NEXT: s_clause 0x1
+; GFX12-SDAG-NEXT: global_load_b32 v2, v1, s[0:1]
+; GFX12-SDAG-NEXT: global_load_b32 v1, v1, s[2:3]
+; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX12-SDAG-NEXT: v_mul_lo_u32 v1, v1, v2
+; GFX12-SDAG-NEXT: global_store_b32 v0, v1, s[6:7]
+; GFX12-SDAG-NEXT: s_nop 0
+; GFX12-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-SDAG-NEXT: s_endpgm
;
-; GLOBAL-ISEL-LABEL: test3_s_barrier_signal_isfirst:
-; GLOBAL-ISEL: ; %bb.0: ; %entry
-; GLOBAL-ISEL-NEXT: s_load_b256 s[0:7], s[2:3], 0x24
-; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
-; GLOBAL-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GLOBAL-ISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GLOBAL-ISEL-NEXT: s_wait_kmcnt 0x0
-; GLOBAL-ISEL-NEXT: global_store_b32 v0, v1, s[6:7]
-; GLOBAL-ISEL-NEXT: s_wait_storecnt 0x0
-; GLOBAL-ISEL-NEXT: s_barrier_signal_isfirst 1
-; GLOBAL-ISEL-NEXT: s_cselect_b32 s8, 1, 0
-; GLOBAL-ISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GLOBAL-ISEL-NEXT: s_and_b32 s8, s8, 1
-; GLOBAL-ISEL-NEXT: s_cmp_lg_u32 s8, 0
-; GLOBAL-ISEL-NEXT: s_cselect_b64 s[2:3], s[2:3], s[4:5]
-; GLOBAL-ISEL-NEXT: s_clause 0x1
-; GLOBAL-ISEL-NEXT: global_load_b32 v2, v1, s[0:1]
-; GLOBAL-ISEL-NEXT: global_load_b32 v1, v1, s[2:3]
-; GLOBAL-ISEL-NEXT: s_wait_loadcnt 0x0
-; GLOBAL-ISEL-NEXT: v_mul_lo_u32 v1, v1, v2
-; GLOBAL-ISEL-NEXT: global_store_b32 v0, v1, s[6:7]
-; GLOBAL-ISEL-NEXT: s_nop 0
-; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GLOBAL-ISEL-NEXT: s_endpgm
+; GFX12-GISEL-LABEL: test3_s_barrier_signal_isfirst:
+; GFX12-GISEL: ; %bb.0: ; %entry
+; GFX12-GISEL-NEXT: s_load_b256 s[0:7], s[2:3], 0x24
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: global_store_b32 v0, v1, s[6:7]
+; GFX12-GISEL-NEXT: s_wait_storecnt 0x0
+; GFX12-GISEL-NEXT: s_barrier_signal_isfirst 1
+; GFX12-GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX12-GISEL-NEXT: s_and_b32 s8, s8, 1
+; GFX12-GISEL-NEXT: s_cmp_lg_u32 s8, 0
+; GFX12-GISEL-NEXT: s_cselect_b64 s[2:3], s[2:3], s[4:5]
+; GFX12-GISEL-NEXT: s_clause 0x1
+; GFX12-GISEL-NEXT: global_load_b32 v2, v1, s[0:1]
+; GFX12-GISEL-NEXT: global_load_b32 v1, v1, s[2:3]
+; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX12-GISEL-NEXT: v_mul_lo_u32 v1, v1, v2
+; GFX12-GISEL-NEXT: global_store_b32 v0, v1, s[6:7]
+; GFX12-GISEL-NEXT: s_nop 0
+; GFX12-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-GISEL-NEXT: s_endpgm
entry:
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
%tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp
@@ -409,54 +409,54 @@ entry:
}
define amdgpu_kernel void @test1_s_barrier_signal_isfirst_var(ptr addrspace(1) %a, ptr addrspace(1) %b, ptr addrspace(1) %c, ptr addrspace(1) %out) #0 {
-; GCN-LABEL: test1_s_barrier_signal_isfirst_var:
-; GCN: ; %bb.0: ; %entry
-; GCN-NEXT: s_load_b256 s[0:7], s[2:3], 0x24
-; GCN-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
-; GCN-NEXT: s_mov_b32 m0, 1
-; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GCN-NEXT: s_wait_kmcnt 0x0
-; GCN-NEXT: global_store_b32 v0, v1, s[6:7]
-; GCN-NEXT: s_wait_storecnt 0x0
-; GCN-NEXT: s_barrier_signal_isfirst m0
-; GCN-NEXT: s_cselect_b32 s3, s3, s5
-; GCN-NEXT: s_cselect_b32 s2, s2, s4
-; GCN-NEXT: s_clause 0x1
-; GCN-NEXT: global_load_b32 v2, v1, s[0:1]
-; GCN-NEXT: global_load_b32 v1, v1, s[2:3]
-; GCN-NEXT: s_wait_loadcnt 0x0
-; GCN-NEXT: v_mul_lo_u32 v1, v1, v2
-; GCN-NEXT: global_store_b32 v0, v1, s[6:7]
-; GCN-NEXT: s_nop 0
-; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GCN-NEXT: s_endpgm
+; GFX12-SDAG-LABEL: test1_s_barrier_signal_isfirst_var:
+; GFX12-SDAG: ; %bb.0: ; %entry
+; GFX12-SDAG-NEXT: s_load_b256 s[0:7], s[2:3], 0x24
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
+; GFX12-SDAG-NEXT: s_mov_b32 m0, 1
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: global_store_b32 v0, v1, s[6:7]
+; GFX12-SDAG-NEXT: s_wait_storecnt 0x0
+; GFX12-SDAG-NEXT: s_barrier_signal_isfirst m0
+; GFX12-SDAG-NEXT: s_cselect_b32 s3, s3, s5
+; GFX12-SDAG-NEXT: s_cselect_b32 s2, s2, s4
+; GFX12-SDAG-NEXT: s_clause 0x1
+; GFX12-SDAG-NEXT: global_load_b32 v2, v1, s[0:1]
+; GFX12-SDAG-NEXT: global_load_b32 v1, v1, s[2:3]
+; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX12-SDAG-NEXT: v_mul_lo_u32 v1, v1, v2
+; GFX12-SDAG-NEXT: global_store_b32 v0, v1, s[6:7]
+; GFX12-SDAG-NEXT: s_nop 0
+; GFX12-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-SDAG-NEXT: s_endpgm
;
-; GLOBAL-ISEL-LABEL: test1_s_barrier_signal_isfirst_var:
-; GLOBAL-ISEL: ; %bb.0: ; %entry
-; GLOBAL-ISEL-NEXT: s_load_b256 s[0:7], s[2:3], 0x24
-; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
-; GLOBAL-ISEL-NEXT: s_mov_b32 m0, 1
-; GLOBAL-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GLOBAL-ISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GLOBAL-ISEL-NEXT: s_wait_kmcnt 0x0
-; GLOBAL-ISEL-NEXT: global_store_b32 v0, v1, s[6:7]
-; GLOBAL-ISEL-NEXT: s_wait_storecnt 0x0
-; GLOBAL-ISEL-NEXT: s_barrier_signal_isfirst m0
-; GLOBAL-ISEL-NEXT: s_cselect_b32 s8, 1, 0
-; GLOBAL-ISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GLOBAL-ISEL-NEXT: s_and_b32 s8, s8, 1
-; GLOBAL-ISEL-NEXT: s_cmp_lg_u32 s8, 0
-; GLOBAL-ISEL-NEXT: s_cselect_b64 s[2:3], s[2:3], s[4:5]
-; GLOBAL-ISEL-NEXT: s_clause 0x1
-; GLOBAL-ISEL-NEXT: global_load_b32 v2, v1, s[0:1]
-; GLOBAL-ISEL-NEXT: global_load_b32 v1, v1, s[2:3]
-; GLOBAL-ISEL-NEXT: s_wait_loadcnt 0x0
-; GLOBAL-ISEL-NEXT: v_mul_lo_u32 v1, v1, v2
-; GLOBAL-ISEL-NEXT: global_store_b32 v0, v1, s[6:7]
-; GLOBAL-ISEL-NEXT: s_nop 0
-; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GLOBAL-ISEL-NEXT: s_endpgm
+; GFX12-GISEL-LABEL: test1_s_barrier_signal_isfirst_var:
+; GFX12-GISEL: ; %bb.0: ; %entry
+; GFX12-GISEL-NEXT: s_load_b256 s[0:7], s[2:3], 0x24
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
+; GFX12-GISEL-NEXT: s_mov_b32 m0, 1
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: global_store_b32 v0, v1, s[6:7]
+; GFX12-GISEL-NEXT: s_wait_storecnt 0x0
+; GFX12-GISEL-NEXT: s_barrier_signal_isfirst m0
+; GFX12-GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX12-GISEL-NEXT: s_and_b32 s8, s8, 1
+; GFX12-GISEL-NEXT: s_cmp_lg_u32 s8, 0
+; GFX12-GISEL-NEXT: s_cselect_b64 s[2:3], s[2:3], s[4:5]
+; GFX12-GISEL-NEXT: s_clause 0x1
+; GFX12-GISEL-NEXT: global_load_b32 v2, v1, s[0:1]
+; GFX12-GISEL-NEXT: global_load_b32 v1, v1, s[2:3]
+; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX12-GISEL-NEXT: v_mul_lo_u32 v1, v1, v2
+; GFX12-GISEL-NEXT: global_store_b32 v0, v1, s[6:7]
+; GFX12-GISEL-NEXT: s_nop 0
+; GFX12-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-GISEL-NEXT: s_endpgm
entry:
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
%tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp
@@ -471,65 +471,65 @@ entry:
}
define void @test2_s_barrier_signal_isfirst_var(ptr addrspace(1) %a, ptr addrspace(1) %b, ptr addrspace(1) %c, i32 %arg, ptr addrspace(1) %out) {
-; GCN-LABEL: test2_s_barrier_signal_isfirst_var:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_wait_loadcnt_dscnt 0x0
-; GCN-NEXT: s_wait_expcnt 0x0
-; GCN-NEXT: s_wait_samplecnt 0x0
-; GCN-NEXT: s_wait_bvhcnt 0x0
-; GCN-NEXT: s_wait_kmcnt 0x0
-; GCN-NEXT: v_dual_mov_b32 v10, 0 :: v_dual_and_b32 v9, 0x3ff, v31
-; GCN-NEXT: v_readfirstlane_b32 s0, v6
-; GCN-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GCN-NEXT: v_lshlrev_b32_e32 v9, 2, v9
-; GCN-NEXT: s_mov_b32 m0, s0
-; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GCN-NEXT: v_add_co_u32 v7, vcc_lo, v7, v9
-; GCN-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
-; GCN-NEXT: global_store_b32 v[7:8], v10, off
-; GCN-NEXT: s_wait_storecnt 0x0
-; GCN-NEXT: s_barrier_signal_isfirst m0
-; GCN-NEXT: s_cselect_b32 vcc_lo, -1, 0
-; GCN-NEXT: s_wait_alu 0xfffe
-; GCN-NEXT: v_dual_cndmask_b32 v2, v4, v2 :: v_dual_cndmask_b32 v3, v5, v3
-; GCN-NEXT: global_load_b32 v0, v[0:1], off
-; GCN-NEXT: global_load_b32 v1, v[2:3], off
-; GCN-NEXT: s_wait_loadcnt 0x0
-; GCN-NEXT: v_mul_lo_u32 v0, v1, v0
-; GCN-NEXT: global_store_b32 v[7:8], v0, off
-; GCN-NEXT: s_wait_kmcnt 0x0
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; GFX12-SDAG-LABEL: test2_s_barrier_signal_isfirst_var:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v10, 0 :: v_dual_and_b32 v9, 0x3ff, v31
+; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v6
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-NEXT: v_lshlrev_b32_e32 v9, 2, v9
+; GFX12-SDAG-NEXT: s_mov_b32 m0, s0
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_add_co_u32 v7, vcc_lo, v7, v9
+; GFX12-SDAG-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
+; GFX12-SDAG-NEXT: global_store_b32 v[7:8], v10, off
+; GFX12-SDAG-NEXT: s_wait_storecnt 0x0
+; GFX12-SDAG-NEXT: s_barrier_signal_isfirst m0
+; GFX12-SDAG-NEXT: s_cselect_b32 vcc_lo, -1, 0
+; GFX12-SDAG-NEXT: s_wait_alu 0xfffe
+; GFX12-SDAG-NEXT: v_dual_cndmask_b32 v2, v4, v2 :: v_dual_cndmask_b32 v3, v5, v3
+; GFX12-SDAG-NEXT: global_load_b32 v0, v[0:1], off
+; GFX12-SDAG-NEXT: global_load_b32 v1, v[2:3], off
+; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX12-SDAG-NEXT: v_mul_lo_u32 v0, v1, v0
+; GFX12-SDAG-NEXT: global_store_b32 v[7:8], v0, off
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GLOBAL-ISEL-LABEL: test2_s_barrier_signal_isfirst_var:
-; GLOBAL-ISEL: ; %bb.0:
-; GLOBAL-ISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GLOBAL-ISEL-NEXT: s_wait_expcnt 0x0
-; GLOBAL-ISEL-NEXT: s_wait_samplecnt 0x0
-; GLOBAL-ISEL-NEXT: s_wait_bvhcnt 0x0
-; GLOBAL-ISEL-NEXT: s_wait_kmcnt 0x0
-; GLOBAL-ISEL-NEXT: v_and_b32_e32 v9, 0x3ff, v31
-; GLOBAL-ISEL-NEXT: v_readfirstlane_b32 m0, v6
-; GLOBAL-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GLOBAL-ISEL-NEXT: v_lshlrev_b32_e32 v9, 2, v9
-; GLOBAL-ISEL-NEXT: v_add_co_u32 v7, vcc_lo, v7, v9
-; GLOBAL-ISEL-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
-; GLOBAL-ISEL-NEXT: v_mov_b32_e32 v9, 0
-; GLOBAL-ISEL-NEXT: global_store_b32 v[7:8], v9, off
-; GLOBAL-ISEL-NEXT: s_wait_storecnt 0x0
-; GLOBAL-ISEL-NEXT: s_barrier_signal_isfirst m0
-; GLOBAL-ISEL-NEXT: s_cselect_b32 s0, 1, 0
-; GLOBAL-ISEL-NEXT: s_wait_alu 0xfffe
-; GLOBAL-ISEL-NEXT: s_and_b32 s0, 1, s0
-; GLOBAL-ISEL-NEXT: s_wait_alu 0xfffe
-; GLOBAL-ISEL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
-; GLOBAL-ISEL-NEXT: v_dual_cndmask_b32 v2, v4, v2 :: v_dual_cndmask_b32 v3, v5, v3
-; GLOBAL-ISEL-NEXT: global_load_b32 v0, v[0:1], off
-; GLOBAL-ISEL-NEXT: global_load_b32 v1, v[2:3], off
-; GLOBAL-ISEL-NEXT: s_wait_loadcnt 0x0
-; GLOBAL-ISEL-NEXT: v_mul_lo_u32 v0, v1, v0
-; GLOBAL-ISEL-NEXT: global_store_b32 v[7:8], v0, off
-; GLOBAL-ISEL-NEXT: s_wait_kmcnt 0x0
-; GLOBAL-ISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX12-GISEL-LABEL: test2_s_barrier_signal_isfirst_var:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_and_b32_e32 v9, 0x3ff, v31
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 m0, v6
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_lshlrev_b32_e32 v9, 2, v9
+; GFX12-GISEL-NEXT: v_add_co_u32 v7, vcc_lo, v7, v9
+; GFX12-GISEL-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v9, 0
+; GFX12-GISEL-NEXT: global_store_b32 v[7:8], v9, off
+; GFX12-GISEL-NEXT: s_wait_storecnt 0x0
+; GFX12-GISEL-NEXT: s_barrier_signal_isfirst m0
+; GFX12-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX12-GISEL-NEXT: s_wait_alu 0xfffe
+; GFX12-GISEL-NEXT: s_and_b32 s0, 1, s0
+; GFX12-GISEL-NEXT: s_wait_alu 0xfffe
+; GFX12-GISEL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
+; GFX12-GISEL-NEXT: v_dual_cndmask_b32 v2, v4, v2 :: v_dual_cndmask_b32 v3, v5, v3
+; GFX12-GISEL-NEXT: global_load_b32 v0, v[0:1], off
+; GFX12-GISEL-NEXT: global_load_b32 v1, v[2:3], off
+; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX12-GISEL-NEXT: v_mul_lo_u32 v0, v1, v0
+; GFX12-GISEL-NEXT: global_store_b32 v[7:8], v0, off
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
%tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp
store i32 0, ptr addrspace(1) %tmp1
@@ -543,40 +543,40 @@ define void @test2_s_barrier_signal_isfirst_var(ptr addrspace(1) %a, ptr addrspa
}
define amdgpu_kernel void @test1_s_barrier_init(ptr addrspace(1) %out, i32 %mbrCnt) #0 {
-; GCN-LABEL: test1_s_barrier_init:
-; GCN: ; %bb.0: ; %entry
-; GCN-NEXT: s_load_b96 s[0:2], s[2:3], 0x24
-; GCN-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GCN-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
-; GCN-NEXT: v_mul_u32_u24_e32 v1, v0, v0
-; GCN-NEXT: v_sub_nc_u32_e32 v0, v1, v0
-; GCN-NEXT: s_wait_kmcnt 0x0
-; GCN-NEXT: s_lshl_b32 s2, s2, 16
-; GCN-NEXT: global_store_b32 v3, v2, s[0:1]
-; GCN-NEXT: s_mov_b32 m0, s2
-; GCN-NEXT: s_barrier_init -1
-; GCN-NEXT: global_store_b32 v3, v0, s[0:1]
-; GCN-NEXT: s_nop 0
-; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GCN-NEXT: s_endpgm
+; GFX12-SDAG-LABEL: test1_s_barrier_init:
+; GFX12-SDAG: ; %bb.0: ; %entry
+; GFX12-SDAG-NEXT: s_load_b96 s[0:2], s[2:3], 0x24
+; GFX12-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
+; GFX12-SDAG-NEXT: v_mul_u32_u24_e32 v1, v0, v0
+; GFX12-SDAG-NEXT: v_sub_nc_u32_e32 v0, v1, v0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: s_lshl_b32 s2, s2, 16
+; GFX12-SDAG-NEXT: global_store_b32 v3, v2, s[0:1]
+; GFX12-SDAG-NEXT: s_mov_b32 m0, s2
+; GFX12-SDAG-NEXT: s_barrier_init -1
+; GFX12-SDAG-NEXT: global_store_b32 v3, v0, s[0:1]
+; GFX12-SDAG-NEXT: s_nop 0
+; GFX12-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-SDAG-NEXT: s_endpgm
;
-; GLOBAL-ISEL-LABEL: test1_s_barrier_init:
-; GLOBAL-ISEL: ; %bb.0: ; %entry
-; GLOBAL-ISEL-NEXT: s_load_b96 s[0:2], s[2:3], 0x24
-; GLOBAL-ISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GLOBAL-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
-; GLOBAL-ISEL-NEXT: v_mul_lo_u32 v1, v0, v0
-; GLOBAL-ISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0
-; GLOBAL-ISEL-NEXT: s_wait_kmcnt 0x0
-; GLOBAL-ISEL-NEXT: s_lshl_b32 m0, 16, s2
-; GLOBAL-ISEL-NEXT: global_store_b32 v3, v2, s[0:1]
-; GLOBAL-ISEL-NEXT: s_barrier_init -1
-; GLOBAL-ISEL-NEXT: global_store_b32 v3, v0, s[0:1]
-; GLOBAL-ISEL-NEXT: s_nop 0
-; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GLOBAL-ISEL-NEXT: s_endpgm
+; GFX12-GISEL-LABEL: test1_s_barrier_init:
+; GFX12-GISEL: ; %bb.0: ; %entry
+; GFX12-GISEL-NEXT: s_load_b96 s[0:2], s[2:3], 0x24
+; GFX12-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
+; GFX12-GISEL-NEXT: v_mul_lo_u32 v1, v0, v0
+; GFX12-GISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: s_lshl_b32 m0, 16, s2
+; GFX12-GISEL-NEXT: global_store_b32 v3, v2, s[0:1]
+; GFX12-GISEL-NEXT: s_barrier_init -1
+; GFX12-GISEL-NEXT: global_store_b32 v3, v0, s[0:1]
+; GFX12-GISEL-NEXT: s_nop 0
+; GFX12-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-GISEL-NEXT: s_endpgm
entry:
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
%tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp
@@ -589,40 +589,40 @@ entry:
}
define amdgpu_kernel void @test2_s_barrier_init(ptr addrspace(1) %out, i32 %mbrCnt) #0 {
-; GCN-LABEL: test2_s_barrier_init:
-; GCN: ; %bb.0: ; %entry
-; GCN-NEXT: s_load_b96 s[0:2], s[2:3], 0x24
-; GCN-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GCN-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
-; GCN-NEXT: v_mul_u32_u24_e32 v1, v0, v0
-; GCN-NEXT: v_sub_nc_u32_e32 v0, v1, v0
-; GCN-NEXT: s_wait_kmcnt 0x0
-; GCN-NEXT: s_lshl_b32 s2, s2, 16
-; GCN-NEXT: global_store_b32 v3, v2, s[0:1]
-; GCN-NEXT: s_mov_b32 m0, s2
-; GCN-NEXT: s_barrier_init 1
-; GCN-NEXT: global_store_b32 v3, v0, s[0:1]
-; GCN-NEXT: s_nop 0
-; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GCN-NEXT: s_endpgm
+; GFX12-SDAG-LABEL: test2_s_barrier_init:
+; GFX12-SDAG: ; %bb.0: ; %entry
+; GFX12-SDAG-NEXT: s_load_b96 s[0:2], s[2:3], 0x24
+; GFX12-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
+; GFX12-SDAG-NEXT: v_mul_u32_u24_e32 v1, v0, v0
+; GFX12-SDAG-NEXT: v_sub_nc_u32_e32 v0, v1, v0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: s_lshl_b32 s2, s2, 16
+; GFX12-SDAG-NEXT: global_store_b32 v3, v2, s[0:1]
+; GFX12-SDAG-NEXT: s_mov_b32 m0, s2
+; GFX12-SDAG-NEXT: s_barrier_init 1
+; GFX12-SDAG-NEXT: global_store_b32 v3, v0, s[0:1]
+; GFX12-SDAG-NEXT: s_nop 0
+; GFX12-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-SDAG-NEXT: s_endpgm
;
-; GLOBAL-ISEL-LABEL: test2_s_barrier_init:
-; GLOBAL-ISEL: ; %bb.0: ; %entry
-; GLOBAL-ISEL-NEXT: s_load_b96 s[0:2], s[2:3], 0x24
-; GLOBAL-ISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GLOBAL-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
-; GLOBAL-ISEL-NEXT: v_mul_lo_u32 v1, v0, v0
-; GLOBAL-ISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0
-; GLOBAL-ISEL-NEXT: s_wait_kmcnt 0x0
-; GLOBAL-ISEL-NEXT: s_lshl_b32 m0, 16, s2
-; GLOBAL-ISEL-NEXT: global_store_b32 v3, v2, s[0:1]
-; GLOBAL-ISEL-NEXT: s_barrier_init 1
-; GLOBAL-ISEL-NEXT: global_store_b32 v3, v0, s[0:1]
-; GLOBAL-ISEL-NEXT: s_nop 0
-; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GLOBAL-ISEL-NEXT: s_endpgm
+; GFX12-GISEL-LABEL: test2_s_barrier_init:
+; GFX12-GISEL: ; %bb.0: ; %entry
+; GFX12-GISEL-NEXT: s_load_b96 s[0:2], s[2:3], 0x24
+; GFX12-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
+; GFX12-GISEL-NEXT: v_mul_lo_u32 v1, v0, v0
+; GFX12-GISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: s_lshl_b32 m0, 16, s2
+; GFX12-GISEL-NEXT: global_store_b32 v3, v2, s[0:1]
+; GFX12-GISEL-NEXT: s_barrier_init 1
+; GFX12-GISEL-NEXT: global_store_b32 v3, v0, s[0:1]
+; GFX12-GISEL-NEXT: s_nop 0
+; GFX12-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-GISEL-NEXT: s_endpgm
entry:
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
%tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp
@@ -635,40 +635,40 @@ entry:
}
define amdgpu_kernel void @test3_s_barrier_init(ptr addrspace(1) %out, i32 %mbrCnt) #0 {
-; GCN-LABEL: test3_s_barrier_init:
-; GCN: ; %bb.0: ; %entry
-; GCN-NEXT: s_load_b96 s[0:2], s[2:3], 0x24
-; GCN-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GCN-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
-; GCN-NEXT: v_mul_u32_u24_e32 v1, v0, v0
-; GCN-NEXT: v_sub_nc_u32_e32 v0, v1, v0
-; GCN-NEXT: s_wait_kmcnt 0x0
-; GCN-NEXT: s_lshl_b32 s2, s2, 16
-; GCN-NEXT: global_store_b32 v3, v2, s[0:1]
-; GCN-NEXT: s_mov_b32 m0, s2
-; GCN-NEXT: s_barrier_init 0
-; GCN-NEXT: global_store_b32 v3, v0, s[0:1]
-; GCN-NEXT: s_nop 0
-; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GCN-NEXT: s_endpgm
+; GFX12-SDAG-LABEL: test3_s_barrier_init:
+; GFX12-SDAG: ; %bb.0: ; %entry
+; GFX12-SDAG-NEXT: s_load_b96 s[0:2], s[2:3], 0x24
+; GFX12-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
+; GFX12-SDAG-NEXT: v_mul_u32_u24_e32 v1, v0, v0
+; GFX12-SDAG-NEXT: v_sub_nc_u32_e32 v0, v1, v0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: s_lshl_b32 s2, s2, 16
+; GFX12-SDAG-NEXT: global_store_b32 v3, v2, s[0:1]
+; GFX12-SDAG-NEXT: s_mov_b32 m0, s2
+; GFX12-SDAG-NEXT: s_barrier_init 0
+; GFX12-SDAG-NEXT: global_store_b32 v3, v0, s[0:1]
+; GFX12-SDAG-NEXT: s_nop 0
+; GFX12-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-SDAG-NEXT: s_endpgm
;
-; GLOBAL-ISEL-LABEL: test3_s_barrier_init:
-; GLOBAL-ISEL: ; %bb.0: ; %entry
-; GLOBAL-ISEL-NEXT: s_load_b96 s[0:2], s[2:3], 0x24
-; GLOBAL-ISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GLOBAL-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
-; GLOBAL-ISEL-NEXT: v_mul_lo_u32 v1, v0, v0
-; GLOBAL-ISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0
-; GLOBAL-ISEL-NEXT: s_wait_kmcnt 0x0
-; GLOBAL-ISEL-NEXT: s_lshl_b32 m0, 16, s2
-; GLOBAL-ISEL-NEXT: global_store_b32 v3, v2, s[0:1]
-; GLOBAL-ISEL-NEXT: s_barrier_init 0
-; GLOBAL-ISEL-NEXT: global_store_b32 v3, v0, s[0:1]
-; GLOBAL-ISEL-NEXT: s_nop 0
-; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GLOBAL-ISEL-NEXT: s_endpgm
+; GFX12-GISEL-LABEL: test3_s_barrier_init:
+; GFX12-GISEL: ; %bb.0: ; %entry
+; GFX12-GISEL-NEXT: s_load_b96 s[0:2], s[2:3], 0x24
+; GFX12-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
+; GFX12-GISEL-NEXT: v_mul_lo_u32 v1, v0, v0
+; GFX12-GISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: s_lshl_b32 m0, 16, s2
+; GFX12-GISEL-NEXT: global_store_b32 v3, v2, s[0:1]
+; GFX12-GISEL-NEXT: s_barrier_init 0
+; GFX12-GISEL-NEXT: global_store_b32 v3, v0, s[0:1]
+; GFX12-GISEL-NEXT: s_nop 0
+; GFX12-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-GISEL-NEXT: s_endpgm
entry:
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
%tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp
@@ -681,43 +681,43 @@ entry:
}
define amdgpu_kernel void @test4_s_barrier_init(ptr addrspace(1) %out, i32 %bar, i32 %mbrCnt) #0 {
-; GCN-LABEL: test4_s_barrier_init:
-; GCN: ; %bb.0: ; %entry
-; GCN-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
-; GCN-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GCN-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
-; GCN-NEXT: v_mul_u32_u24_e32 v1, v0, v0
-; GCN-NEXT: v_sub_nc_u32_e32 v0, v1, v0
-; GCN-NEXT: s_wait_kmcnt 0x0
-; GCN-NEXT: s_lshl_b32 s3, s3, 16
-; GCN-NEXT: global_store_b32 v3, v2, s[0:1]
-; GCN-NEXT: s_or_b32 s2, s2, s3
-; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GCN-NEXT: s_mov_b32 m0, s2
-; GCN-NEXT: s_barrier_init m0
-; GCN-NEXT: global_store_b32 v3, v0, s[0:1]
-; GCN-NEXT: s_nop 0
-; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GCN-NEXT: s_endpgm
+; GFX12-SDAG-LABEL: test4_s_barrier_init:
+; GFX12-SDAG: ; %bb.0: ; %entry
+; GFX12-SDAG-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
+; GFX12-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
+; GFX12-SDAG-NEXT: v_mul_u32_u24_e32 v1, v0, v0
+; GFX12-SDAG-NEXT: v_sub_nc_u32_e32 v0, v1, v0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: s_lshl_b32 s3, s3, 16
+; GFX12-SDAG-NEXT: global_store_b32 v3, v2, s[0:1]
+; GFX12-SDAG-NEXT: s_or_b32 s2, s2, s3
+; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-SDAG-NEXT: s_mov_b32 m0, s2
+; GFX12-SDAG-NEXT: s_barrier_init m0
+; GFX12-SDAG-NEXT: global_store_b32 v3, v0, s[0:1]
+; GFX12-SDAG-NEXT: s_nop 0
+; GFX12-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-SDAG-NEXT: s_endpgm
;
-; GLOBAL-ISEL-LABEL: test4_s_barrier_init:
-; GLOBAL-ISEL: ; %bb.0: ; %entry
-; GLOBAL-ISEL-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
-; GLOBAL-ISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GLOBAL-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
-; GLOBAL-ISEL-NEXT: v_mul_lo_u32 v1, v0, v0
-; GLOBAL-ISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0
-; GLOBAL-ISEL-NEXT: s_wait_kmcnt 0x0
-; GLOBAL-ISEL-NEXT: s_lshl_b32 s3, 16, s3
-; GLOBAL-ISEL-NEXT: global_store_b32 v3, v2, s[0:1]
-; GLOBAL-ISEL-NEXT: s_or_b32 m0, s2, s3
-; GLOBAL-ISEL-NEXT: s_barrier_init m0
-; GLOBAL-ISEL-NEXT: global_store_b32 v3, v0, s[0:1]
-; GLOBAL-ISEL-NEXT: s_nop 0
-; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GLOBAL-ISEL-NEXT: s_endpgm
+; GFX12-GISEL-LABEL: test4_s_barrier_init:
+; GFX12-GISEL: ; %bb.0: ; %entry
+; GFX12-GISEL-NEXT: s_load_b128 s[0:3], s[2:3], 0x24
+; GFX12-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
+; GFX12-GISEL-NEXT: v_mul_lo_u32 v1, v0, v0
+; GFX12-GISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: s_lshl_b32 s3, 16, s3
+; GFX12-GISEL-NEXT: global_store_b32 v3, v2, s[0:1]
+; GFX12-GISEL-NEXT: s_or_b32 m0, s2, s3
+; GFX12-GISEL-NEXT: s_barrier_init m0
+; GFX12-GISEL-NEXT: global_store_b32 v3, v0, s[0:1]
+; GFX12-GISEL-NEXT: s_nop 0
+; GFX12-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-GISEL-NEXT: s_endpgm
entry:
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
%tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp
@@ -730,74 +730,74 @@ entry:
}
define void @test5_s_barrier_init_m0(i32 %arg1 ,i32 %arg2) {
-; GCN-LABEL: test5_s_barrier_init_m0:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_wait_loadcnt_dscnt 0x0
-; GCN-NEXT: s_wait_expcnt 0x0
-; GCN-NEXT: s_wait_samplecnt 0x0
-; GCN-NEXT: s_wait_bvhcnt 0x0
-; GCN-NEXT: s_wait_kmcnt 0x0
-; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GCN-NEXT: v_or_b32_e32 v0, v0, v1
-; GCN-NEXT: v_readfirstlane_b32 s0, v0
-; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GCN-NEXT: s_mov_b32 m0, s0
-; GCN-NEXT: s_barrier_init m0
-; GCN-NEXT: s_wait_alu 0xfffe
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; GFX12-SDAG-LABEL: test5_s_barrier_init_m0:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-NEXT: s_mov_b32 m0, s0
+; GFX12-SDAG-NEXT: s_barrier_init m0
+; GFX12-SDAG-NEXT: s_wait_alu 0xfffe
+; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GLOBAL-ISEL-LABEL: test5_s_barrier_init_m0:
-; GLOBAL-ISEL: ; %bb.0:
-; GLOBAL-ISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GLOBAL-ISEL-NEXT: s_wait_expcnt 0x0
-; GLOBAL-ISEL-NEXT: s_wait_samplecnt 0x0
-; GLOBAL-ISEL-NEXT: s_wait_bvhcnt 0x0
-; GLOBAL-ISEL-NEXT: s_wait_kmcnt 0x0
-; GLOBAL-ISEL-NEXT: v_readfirstlane_b32 s0, v1
-; GLOBAL-ISEL-NEXT: v_readfirstlane_b32 s1, v0
-; GLOBAL-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GLOBAL-ISEL-NEXT: s_lshl_b32 s0, 16, s0
-; GLOBAL-ISEL-NEXT: s_wait_alu 0xfffe
-; GLOBAL-ISEL-NEXT: s_or_b32 m0, s1, s0
-; GLOBAL-ISEL-NEXT: s_barrier_init m0
-; GLOBAL-ISEL-NEXT: s_wait_alu 0xfffe
-; GLOBAL-ISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX12-GISEL-LABEL: test5_s_barrier_init_m0:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v1
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v0
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-GISEL-NEXT: s_lshl_b32 s0, 16, s0
+; GFX12-GISEL-NEXT: s_wait_alu 0xfffe
+; GFX12-GISEL-NEXT: s_or_b32 m0, s1, s0
+; GFX12-GISEL-NEXT: s_barrier_init m0
+; GFX12-GISEL-NEXT: s_wait_alu 0xfffe
+; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
call void @llvm.amdgcn.s.barrier.init(i32 %arg1, i32 %arg2)
ret void
}
define amdgpu_kernel void @test1_s_barrier_join(ptr addrspace(1) %out) #0 {
-; GCN-LABEL: test1_s_barrier_join:
-; GCN: ; %bb.0: ; %entry
-; GCN-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
-; GCN-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GCN-NEXT: s_barrier_join -1
-; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GCN-NEXT: v_mul_u32_u24_e32 v1, v0, v0
-; GCN-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; GCN-NEXT: v_sub_nc_u32_e32 v0, v1, v0
-; GCN-NEXT: s_wait_kmcnt 0x0
-; GCN-NEXT: global_store_b32 v2, v0, s[0:1]
-; GCN-NEXT: s_nop 0
-; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GCN-NEXT: s_endpgm
+; GFX12-SDAG-LABEL: test1_s_barrier_join:
+; GFX12-SDAG: ; %bb.0: ; %entry
+; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
+; GFX12-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX12-SDAG-NEXT: s_barrier_join -1
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-NEXT: v_mul_u32_u24_e32 v1, v0, v0
+; GFX12-SDAG-NEXT: v_lshlrev_b32_e32 v2, 2, v0
+; GFX12-SDAG-NEXT: v_sub_nc_u32_e32 v0, v1, v0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: global_store_b32 v2, v0, s[0:1]
+; GFX12-SDAG-NEXT: s_nop 0
+; GFX12-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-SDAG-NEXT: s_endpgm
;
-; GLOBAL-ISEL-LABEL: test1_s_barrier_join:
-; GLOBAL-ISEL: ; %bb.0: ; %entry
-; GLOBAL-ISEL-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
-; GLOBAL-ISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GLOBAL-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
-; GLOBAL-ISEL-NEXT: v_mul_lo_u32 v1, v0, v0
-; GLOBAL-ISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0
-; GLOBAL-ISEL-NEXT: s_wait_kmcnt 0x0
-; GLOBAL-ISEL-NEXT: global_store_b32 v3, v2, s[0:1]
-; GLOBAL-ISEL-NEXT: s_barrier_join -1
-; GLOBAL-ISEL-NEXT: global_store_b32 v3, v0, s[0:1]
-; GLOBAL-ISEL-NEXT: s_nop 0
-; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GLOBAL-ISEL-NEXT: s_endpgm
+; GFX12-GISEL-LABEL: test1_s_barrier_join:
+; GFX12-GISEL: ; %bb.0: ; %entry
+; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
+; GFX12-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
+; GFX12-GISEL-NEXT: v_mul_lo_u32 v1, v0, v0
+; GFX12-GISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: global_store_b32 v3, v2, s[0:1]
+; GFX12-GISEL-NEXT: s_barrier_join -1
+; GFX12-GISEL-NEXT: global_store_b32 v3, v0, s[0:1]
+; GFX12-GISEL-NEXT: s_nop 0
+; GFX12-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-GISEL-NEXT: s_endpgm
entry:
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
%tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp
@@ -810,36 +810,36 @@ entry:
}
define amdgpu_kernel void @test2_s_barrier_join(ptr addrspace(1) %out) #0 {
-; GCN-LABEL: test2_s_barrier_join:
-; GCN: ; %bb.0: ; %entry
-; GCN-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
-; GCN-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GCN-NEXT: s_barrier_join 1
-; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GCN-NEXT: v_mul_u32_u24_e32 v1, v0, v0
-; GCN-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; GCN-NEXT: v_sub_nc_u32_e32 v0, v1, v0
-; GCN-NEXT: s_wait_kmcnt 0x0
-; GCN-NEXT: global_store_b32 v2, v0, s[0:1]
-; GCN-NEXT: s_nop 0
-; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GCN-NEXT: s_endpgm
+; GFX12-SDAG-LABEL: test2_s_barrier_join:
+; GFX12-SDAG: ; %bb.0: ; %entry
+; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
+; GFX12-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX12-SDAG-NEXT: s_barrier_join 1
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-NEXT: v_mul_u32_u24_e32 v1, v0, v0
+; GFX12-SDAG-NEXT: v_lshlrev_b32_e32 v2, 2, v0
+; GFX12-SDAG-NEXT: v_sub_nc_u32_e32 v0, v1, v0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: global_store_b32 v2, v0, s[0:1]
+; GFX12-SDAG-NEXT: s_nop 0
+; GFX12-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-SDAG-NEXT: s_endpgm
;
-; GLOBAL-ISEL-LABEL: test2_s_barrier_join:
-; GLOBAL-ISEL: ; %bb.0: ; %entry
-; GLOBAL-ISEL-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
-; GLOBAL-ISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GLOBAL-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
-; GLOBAL-ISEL-NEXT: v_mul_lo_u32 v1, v0, v0
-; GLOBAL-ISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0
-; GLOBAL-ISEL-NEXT: s_wait_kmcnt 0x0
-; GLOBAL-ISEL-NEXT: global_store_b32 v3, v2, s[0:1]
-; GLOBAL-ISEL-NEXT: s_barrier_join 1
-; GLOBAL-ISEL-NEXT: global_store_b32 v3, v0, s[0:1]
-; GLOBAL-ISEL-NEXT: s_nop 0
-; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GLOBAL-ISEL-NEXT: s_endpgm
+; GFX12-GISEL-LABEL: test2_s_barrier_join:
+; GFX12-GISEL: ; %bb.0: ; %entry
+; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
+; GFX12-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
+; GFX12-GISEL-NEXT: v_mul_lo_u32 v1, v0, v0
+; GFX12-GISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: global_store_b32 v3, v2, s[0:1]
+; GFX12-GISEL-NEXT: s_barrier_join 1
+; GFX12-GISEL-NEXT: global_store_b32 v3, v0, s[0:1]
+; GFX12-GISEL-NEXT: s_nop 0
+; GFX12-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-GISEL-NEXT: s_endpgm
entry:
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
%tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp
@@ -852,36 +852,36 @@ entry:
}
define amdgpu_kernel void @test3_s_barrier_join(ptr addrspace(1) %out) #0 {
-; GCN-LABEL: test3_s_barrier_join:
-; GCN: ; %bb.0: ; %entry
-; GCN-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
-; GCN-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GCN-NEXT: s_barrier_join 0
-; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GCN-NEXT: v_mul_u32_u24_e32 v1, v0, v0
-; GCN-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; GCN-NEXT: v_sub_nc_u32_e32 v0, v1, v0
-; GCN-NEXT: s_wait_kmcnt 0x0
-; GCN-NEXT: global_store_b32 v2, v0, s[0:1]
-; GCN-NEXT: s_nop 0
-; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GCN-NEXT: s_endpgm
+; GFX12-SDAG-LABEL: test3_s_barrier_join:
+; GFX12-SDAG: ; %bb.0: ; %entry
+; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
+; GFX12-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX12-SDAG-NEXT: s_barrier_join 0
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-NEXT: v_mul_u32_u24_e32 v1, v0, v0
+; GFX12-SDAG-NEXT: v_lshlrev_b32_e32 v2, 2, v0
+; GFX12-SDAG-NEXT: v_sub_nc_u32_e32 v0, v1, v0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: global_store_b32 v2, v0, s[0:1]
+; GFX12-SDAG-NEXT: s_nop 0
+; GFX12-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-SDAG-NEXT: s_endpgm
;
-; GLOBAL-ISEL-LABEL: test3_s_barrier_join:
-; GLOBAL-ISEL: ; %bb.0: ; %entry
-; GLOBAL-ISEL-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
-; GLOBAL-ISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GLOBAL-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
-; GLOBAL-ISEL-NEXT: v_mul_lo_u32 v1, v0, v0
-; GLOBAL-ISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0
-; GLOBAL-ISEL-NEXT: s_wait_kmcnt 0x0
-; GLOBAL-ISEL-NEXT: global_store_b32 v3, v2, s[0:1]
-; GLOBAL-ISEL-NEXT: s_barrier_join 0
-; GLOBAL-ISEL-NEXT: global_store_b32 v3, v0, s[0:1]
-; GLOBAL-ISEL-NEXT: s_nop 0
-; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GLOBAL-ISEL-NEXT: s_endpgm
+; GFX12-GISEL-LABEL: test3_s_barrier_join:
+; GFX12-GISEL: ; %bb.0: ; %entry
+; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
+; GFX12-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
+; GFX12-GISEL-NEXT: v_mul_lo_u32 v1, v0, v0
+; GFX12-GISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: global_store_b32 v3, v2, s[0:1]
+; GFX12-GISEL-NEXT: s_barrier_join 0
+; GFX12-GISEL-NEXT: global_store_b32 v3, v0, s[0:1]
+; GFX12-GISEL-NEXT: s_nop 0
+; GFX12-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-GISEL-NEXT: s_endpgm
entry:
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
%tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp
@@ -894,39 +894,39 @@ entry:
}
define amdgpu_kernel void @test4_s_barrier_join_m0(ptr addrspace(1) %out, i32 %bar) #0 {
-; GCN-LABEL: test4_s_barrier_join_m0:
-; GCN: ; %bb.0: ; %entry
-; GCN-NEXT: s_load_b96 s[0:2], s[2:3], 0x24
-; GCN-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
-; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GCN-NEXT: v_mul_u32_u24_e32 v2, v0, v0
-; GCN-NEXT: v_lshlrev_b32_e32 v3, 2, v0
-; GCN-NEXT: v_sub_nc_u32_e32 v0, v2, v0
-; GCN-NEXT: s_wait_kmcnt 0x0
-; GCN-NEXT: s_mov_b32 m0, s2
-; GCN-NEXT: global_store_b32 v3, v1, s[0:1]
-; GCN-NEXT: s_barrier_join m0
-; GCN-NEXT: global_store_b32 v3, v0, s[0:1]
-; GCN-NEXT: s_nop 0
-; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GCN-NEXT: s_endpgm
+; GFX12-SDAG-LABEL: test4_s_barrier_join_m0:
+; GFX12-SDAG: ; %bb.0: ; %entry
+; GFX12-SDAG-NEXT: s_load_b96 s[0:2], s[2:3], 0x24
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-NEXT: v_mul_u32_u24_e32 v2, v0, v0
+; GFX12-SDAG-NEXT: v_lshlrev_b32_e32 v3, 2, v0
+; GFX12-SDAG-NEXT: v_sub_nc_u32_e32 v0, v2, v0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: s_mov_b32 m0, s2
+; GFX12-SDAG-NEXT: global_store_b32 v3, v1, s[0:1]
+; GFX12-SDAG-NEXT: s_barrier_join m0
+; GFX12-SDAG-NEXT: global_store_b32 v3, v0, s[0:1]
+; GFX12-SDAG-NEXT: s_nop 0
+; GFX12-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-SDAG-NEXT: s_endpgm
;
-; GLOBAL-ISEL-LABEL: test4_s_barrier_join_m0:
-; GLOBAL-ISEL: ; %bb.0: ; %entry
-; GLOBAL-ISEL-NEXT: s_load_b96 s[0:2], s[2:3], 0x24
-; GLOBAL-ISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GLOBAL-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
-; GLOBAL-ISEL-NEXT: v_mul_lo_u32 v1, v0, v0
-; GLOBAL-ISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0
-; GLOBAL-ISEL-NEXT: s_wait_kmcnt 0x0
-; GLOBAL-ISEL-NEXT: s_mov_b32 m0, s2
-; GLOBAL-ISEL-NEXT: global_store_b32 v3, v2, s[0:1]
-; GLOBAL-ISEL-NEXT: s_barrier_join m0
-; GLOBAL-ISEL-NEXT: global_store_b32 v3, v0, s[0:1]
-; GLOBAL-ISEL-NEXT: s_nop 0
-; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GLOBAL-ISEL-NEXT: s_endpgm
+; GFX12-GISEL-LABEL: test4_s_barrier_join_m0:
+; GFX12-GISEL: ; %bb.0: ; %entry
+; GFX12-GISEL-NEXT: s_load_b96 s[0:2], s[2:3], 0x24
+; GFX12-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
+; GFX12-GISEL-NEXT: v_mul_lo_u32 v1, v0, v0
+; GFX12-GISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: s_mov_b32 m0, s2
+; GFX12-GISEL-NEXT: global_store_b32 v3, v2, s[0:1]
+; GFX12-GISEL-NEXT: s_barrier_join m0
+; GFX12-GISEL-NEXT: global_store_b32 v3, v0, s[0:1]
+; GFX12-GISEL-NEXT: s_nop 0
+; GFX12-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-GISEL-NEXT: s_endpgm
entry:
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
%tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp
@@ -939,79 +939,79 @@ entry:
}
define void @test5_s_barrier_join_m0(i32 %arg) {
-; GCN-LABEL: test5_s_barrier_join_m0:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_wait_loadcnt_dscnt 0x0
-; GCN-NEXT: s_wait_expcnt 0x0
-; GCN-NEXT: s_wait_samplecnt 0x0
-; GCN-NEXT: s_wait_bvhcnt 0x0
-; GCN-NEXT: s_wait_kmcnt 0x0
-; GCN-NEXT: v_readfirstlane_b32 s0, v0
-; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GCN-NEXT: s_mov_b32 m0, s0
-; GCN-NEXT: s_barrier_join m0
-; GCN-NEXT: s_wait_alu 0xfffe
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; GFX12-SDAG-LABEL: test5_s_barrier_join_m0:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-NEXT: s_mov_b32 m0, s0
+; GFX12-SDAG-NEXT: s_barrier_join m0
+; GFX12-SDAG-NEXT: s_wait_alu 0xfffe
+; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GLOBAL-ISEL-LABEL: test5_s_barrier_join_m0:
-; GLOBAL-ISEL: ; %bb.0:
-; GLOBAL-ISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GLOBAL-ISEL-NEXT: s_wait_expcnt 0x0
-; GLOBAL-ISEL-NEXT: s_wait_samplecnt 0x0
-; GLOBAL-ISEL-NEXT: s_wait_bvhcnt 0x0
-; GLOBAL-ISEL-NEXT: s_wait_kmcnt 0x0
-; GLOBAL-ISEL-NEXT: v_readfirstlane_b32 m0, v0
-; GLOBAL-ISEL-NEXT: s_barrier_join m0
-; GLOBAL-ISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX12-GISEL-LABEL: test5_s_barrier_join_m0:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 m0, v0
+; GFX12-GISEL-NEXT: s_barrier_join m0
+; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
call void @llvm.amdgcn.s.barrier.join(i32 %arg)
ret void
}
define amdgpu_kernel void @test1_s_barrier_leave(ptr addrspace(1) %a, ptr addrspace(1) %b, ptr addrspace(1) %c, ptr addrspace(1) %out) #0 {
-; GCN-LABEL: test1_s_barrier_leave:
-; GCN: ; %bb.0: ; %entry
-; GCN-NEXT: s_load_b256 s[0:7], s[2:3], 0x24
-; GCN-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
-; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GCN-NEXT: s_wait_kmcnt 0x0
-; GCN-NEXT: global_store_b32 v0, v1, s[6:7]
-; GCN-NEXT: s_barrier_leave
-; GCN-NEXT: s_cselect_b32 s3, s3, s5
-; GCN-NEXT: s_cselect_b32 s2, s2, s4
-; GCN-NEXT: s_clause 0x1
-; GCN-NEXT: global_load_b32 v2, v1, s[0:1]
-; GCN-NEXT: global_load_b32 v1, v1, s[2:3]
-; GCN-NEXT: s_wait_loadcnt 0x0
-; GCN-NEXT: v_mul_lo_u32 v1, v1, v2
-; GCN-NEXT: global_store_b32 v0, v1, s[6:7]
-; GCN-NEXT: s_nop 0
-; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GCN-NEXT: s_endpgm
+; GFX12-SDAG-LABEL: test1_s_barrier_leave:
+; GFX12-SDAG: ; %bb.0: ; %entry
+; GFX12-SDAG-NEXT: s_load_b256 s[0:7], s[2:3], 0x24
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: global_store_b32 v0, v1, s[6:7]
+; GFX12-SDAG-NEXT: s_barrier_leave
+; GFX12-SDAG-NEXT: s_cselect_b32 s3, s3, s5
+; GFX12-SDAG-NEXT: s_cselect_b32 s2, s2, s4
+; GFX12-SDAG-NEXT: s_clause 0x1
+; GFX12-SDAG-NEXT: global_load_b32 v2, v1, s[0:1]
+; GFX12-SDAG-NEXT: global_load_b32 v1, v1, s[2:3]
+; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX12-SDAG-NEXT: v_mul_lo_u32 v1, v1, v2
+; GFX12-SDAG-NEXT: global_store_b32 v0, v1, s[6:7]
+; GFX12-SDAG-NEXT: s_nop 0
+; GFX12-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-SDAG-NEXT: s_endpgm
;
-; GLOBAL-ISEL-LABEL: test1_s_barrier_leave:
-; GLOBAL-ISEL: ; %bb.0: ; %entry
-; GLOBAL-ISEL-NEXT: s_load_b256 s[0:7], s[2:3], 0x24
-; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
-; GLOBAL-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
-; GLOBAL-ISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GLOBAL-ISEL-NEXT: s_wait_kmcnt 0x0
-; GLOBAL-ISEL-NEXT: global_store_b32 v0, v1, s[6:7]
-; GLOBAL-ISEL-NEXT: s_barrier_leave
-; GLOBAL-ISEL-NEXT: s_cselect_b32 s8, 1, 0
-; GLOBAL-ISEL-NEXT: s_and_b32 s8, s8, 1
-; GLOBAL-ISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GLOBAL-ISEL-NEXT: s_cmp_lg_u32 s8, 0
-; GLOBAL-ISEL-NEXT: s_cselect_b64 s[2:3], s[2:3], s[4:5]
-; GLOBAL-ISEL-NEXT: s_clause 0x1
-; GLOBAL-ISEL-NEXT: global_load_b32 v2, v1, s[0:1]
-; GLOBAL-ISEL-NEXT: global_load_b32 v1, v1, s[2:3]
-; GLOBAL-ISEL-NEXT: s_wait_loadcnt 0x0
-; GLOBAL-ISEL-NEXT: v_mul_lo_u32 v1, v1, v2
-; GLOBAL-ISEL-NEXT: global_store_b32 v0, v1, s[6:7]
-; GLOBAL-ISEL-NEXT: s_nop 0
-; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GLOBAL-ISEL-NEXT: s_endpgm
+; GFX12-GISEL-LABEL: test1_s_barrier_leave:
+; GFX12-GISEL: ; %bb.0: ; %entry
+; GFX12-GISEL-NEXT: s_load_b256 s[0:7], s[2:3], 0x24
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
+; GFX12-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: global_store_b32 v0, v1, s[6:7]
+; GFX12-GISEL-NEXT: s_barrier_leave
+; GFX12-GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; GFX12-GISEL-NEXT: s_and_b32 s8, s8, 1
+; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-GISEL-NEXT: s_cmp_lg_u32 s8, 0
+; GFX12-GISEL-NEXT: s_cselect_b64 s[2:3], s[2:3], s[4:5]
+; GFX12-GISEL-NEXT: s_clause 0x1
+; GFX12-GISEL-NEXT: global_load_b32 v2, v1, s[0:1]
+; GFX12-GISEL-NEXT: global_load_b32 v1, v1, s[2:3]
+; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX12-GISEL-NEXT: v_mul_lo_u32 v1, v1, v2
+; GFX12-GISEL-NEXT: global_store_b32 v0, v1, s[6:7]
+; GFX12-GISEL-NEXT: s_nop 0
+; GFX12-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-GISEL-NEXT: s_endpgm
entry:
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
%tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp
@@ -1026,36 +1026,36 @@ entry:
}
define amdgpu_kernel void @test1_s_wakeup_barrier(ptr addrspace(1) %out) #0 {
-; GCN-LABEL: test1_s_wakeup_barrier:
-; GCN: ; %bb.0: ; %entry
-; GCN-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
-; GCN-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GCN-NEXT: s_wakeup_barrier -1
-; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GCN-NEXT: v_mul_u32_u24_e32 v1, v0, v0
-; GCN-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; GCN-NEXT: v_sub_nc_u32_e32 v0, v1, v0
-; GCN-NEXT: s_wait_kmcnt 0x0
-; GCN-NEXT: global_store_b32 v2, v0, s[0:1]
-; GCN-NEXT: s_nop 0
-; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GCN-NEXT: s_endpgm
+; GFX12-SDAG-LABEL: test1_s_wakeup_barrier:
+; GFX12-SDAG: ; %bb.0: ; %entry
+; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
+; GFX12-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX12-SDAG-NEXT: s_wakeup_barrier -1
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-NEXT: v_mul_u32_u24_e32 v1, v0, v0
+; GFX12-SDAG-NEXT: v_lshlrev_b32_e32 v2, 2, v0
+; GFX12-SDAG-NEXT: v_sub_nc_u32_e32 v0, v1, v0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: global_store_b32 v2, v0, s[0:1]
+; GFX12-SDAG-NEXT: s_nop 0
+; GFX12-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-SDAG-NEXT: s_endpgm
;
-; GLOBAL-ISEL-LABEL: test1_s_wakeup_barrier:
-; GLOBAL-ISEL: ; %bb.0: ; %entry
-; GLOBAL-ISEL-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
-; GLOBAL-ISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GLOBAL-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
-; GLOBAL-ISEL-NEXT: v_mul_lo_u32 v1, v0, v0
-; GLOBAL-ISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0
-; GLOBAL-ISEL-NEXT: s_wait_kmcnt 0x0
-; GLOBAL-ISEL-NEXT: global_store_b32 v3, v2, s[0:1]
-; GLOBAL-ISEL-NEXT: s_wakeup_barrier -1
-; GLOBAL-ISEL-NEXT: global_store_b32 v3, v0, s[0:1]
-; GLOBAL-ISEL-NEXT: s_nop 0
-; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GLOBAL-ISEL-NEXT: s_endpgm
+; GFX12-GISEL-LABEL: test1_s_wakeup_barrier:
+; GFX12-GISEL: ; %bb.0: ; %entry
+; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
+; GFX12-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
+; GFX12-GISEL-NEXT: v_mul_lo_u32 v1, v0, v0
+; GFX12-GISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: global_store_b32 v3, v2, s[0:1]
+; GFX12-GISEL-NEXT: s_wakeup_barrier -1
+; GFX12-GISEL-NEXT: global_store_b32 v3, v0, s[0:1]
+; GFX12-GISEL-NEXT: s_nop 0
+; GFX12-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-GISEL-NEXT: s_endpgm
entry:
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
%tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp
@@ -1068,36 +1068,36 @@ entry:
}
define amdgpu_kernel void @test2_s_wakeup_barrier(ptr addrspace(1) %out) #0 {
-; GCN-LABEL: test2_s_wakeup_barrier:
-; GCN: ; %bb.0: ; %entry
-; GCN-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
-; GCN-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GCN-NEXT: s_wakeup_barrier 1
-; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GCN-NEXT: v_mul_u32_u24_e32 v1, v0, v0
-; GCN-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; GCN-NEXT: v_sub_nc_u32_e32 v0, v1, v0
-; GCN-NEXT: s_wait_kmcnt 0x0
-; GCN-NEXT: global_store_b32 v2, v0, s[0:1]
-; GCN-NEXT: s_nop 0
-; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GCN-NEXT: s_endpgm
+; GFX12-SDAG-LABEL: test2_s_wakeup_barrier:
+; GFX12-SDAG: ; %bb.0: ; %entry
+; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
+; GFX12-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX12-SDAG-NEXT: s_wakeup_barrier 1
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-NEXT: v_mul_u32_u24_e32 v1, v0, v0
+; GFX12-SDAG-NEXT: v_lshlrev_b32_e32 v2, 2, v0
+; GFX12-SDAG-NEXT: v_sub_nc_u32_e32 v0, v1, v0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: global_store_b32 v2, v0, s[0:1]
+; GFX12-SDAG-NEXT: s_nop 0
+; GFX12-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-SDAG-NEXT: s_endpgm
;
-; GLOBAL-ISEL-LABEL: test2_s_wakeup_barrier:
-; GLOBAL-ISEL: ; %bb.0: ; %entry
-; GLOBAL-ISEL-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
-; GLOBAL-ISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GLOBAL-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
-; GLOBAL-ISEL-NEXT: v_mul_lo_u32 v1, v0, v0
-; GLOBAL-ISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0
-; GLOBAL-ISEL-NEXT: s_wait_kmcnt 0x0
-; GLOBAL-ISEL-NEXT: global_store_b32 v3, v2, s[0:1]
-; GLOBAL-ISEL-NEXT: s_wakeup_barrier 1
-; GLOBAL-ISEL-NEXT: global_store_b32 v3, v0, s[0:1]
-; GLOBAL-ISEL-NEXT: s_nop 0
-; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GLOBAL-ISEL-NEXT: s_endpgm
+; GFX12-GISEL-LABEL: test2_s_wakeup_barrier:
+; GFX12-GISEL: ; %bb.0: ; %entry
+; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
+; GFX12-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
+; GFX12-GISEL-NEXT: v_mul_lo_u32 v1, v0, v0
+; GFX12-GISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: global_store_b32 v3, v2, s[0:1]
+; GFX12-GISEL-NEXT: s_wakeup_barrier 1
+; GFX12-GISEL-NEXT: global_store_b32 v3, v0, s[0:1]
+; GFX12-GISEL-NEXT: s_nop 0
+; GFX12-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-GISEL-NEXT: s_endpgm
entry:
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
%tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp
@@ -1110,36 +1110,36 @@ entry:
}
define amdgpu_kernel void @test3_s_wakeup_barrier(ptr addrspace(1) %out) #0 {
-; GCN-LABEL: test3_s_wakeup_barrier:
-; GCN: ; %bb.0: ; %entry
-; GCN-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
-; GCN-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GCN-NEXT: s_wakeup_barrier 0
-; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GCN-NEXT: v_mul_u32_u24_e32 v1, v0, v0
-; GCN-NEXT: v_lshlrev_b32_e32 v2, 2, v0
-; GCN-NEXT: v_sub_nc_u32_e32 v0, v1, v0
-; GCN-NEXT: s_wait_kmcnt 0x0
-; GCN-NEXT: global_store_b32 v2, v0, s[0:1]
-; GCN-NEXT: s_nop 0
-; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GCN-NEXT: s_endpgm
+; GFX12-SDAG-LABEL: test3_s_wakeup_barrier:
+; GFX12-SDAG: ; %bb.0: ; %entry
+; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
+; GFX12-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX12-SDAG-NEXT: s_wakeup_barrier 0
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-NEXT: v_mul_u32_u24_e32 v1, v0, v0
+; GFX12-SDAG-NEXT: v_lshlrev_b32_e32 v2, 2, v0
+; GFX12-SDAG-NEXT: v_sub_nc_u32_e32 v0, v1, v0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: global_store_b32 v2, v0, s[0:1]
+; GFX12-SDAG-NEXT: s_nop 0
+; GFX12-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-SDAG-NEXT: s_endpgm
;
-; GLOBAL-ISEL-LABEL: test3_s_wakeup_barrier:
-; GLOBAL-ISEL: ; %bb.0: ; %entry
-; GLOBAL-ISEL-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
-; GLOBAL-ISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GLOBAL-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
-; GLOBAL-ISEL-NEXT: v_mul_lo_u32 v1, v0, v0
-; GLOBAL-ISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0
-; GLOBAL-ISEL-NEXT: s_wait_kmcnt 0x0
-; GLOBAL-ISEL-NEXT: global_store_b32 v3, v2, s[0:1]
-; GLOBAL-ISEL-NEXT: s_wakeup_barrier 0
-; GLOBAL-ISEL-NEXT: global_store_b32 v3, v0, s[0:1]
-; GLOBAL-ISEL-NEXT: s_nop 0
-; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GLOBAL-ISEL-NEXT: s_endpgm
+; GFX12-GISEL-LABEL: test3_s_wakeup_barrier:
+; GFX12-GISEL: ; %bb.0: ; %entry
+; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
+; GFX12-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
+; GFX12-GISEL-NEXT: v_mul_lo_u32 v1, v0, v0
+; GFX12-GISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: global_store_b32 v3, v2, s[0:1]
+; GFX12-GISEL-NEXT: s_wakeup_barrier 0
+; GFX12-GISEL-NEXT: global_store_b32 v3, v0, s[0:1]
+; GFX12-GISEL-NEXT: s_nop 0
+; GFX12-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-GISEL-NEXT: s_endpgm
entry:
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
%tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp
@@ -1152,39 +1152,39 @@ entry:
}
define amdgpu_kernel void @test4_s_wakeup_barrier_m0(ptr addrspace(1) %out, i32 %bar) #0 {
-; GCN-LABEL: test4_s_wakeup_barrier_m0:
-; GCN: ; %bb.0: ; %entry
-; GCN-NEXT: s_load_b96 s[0:2], s[2:3], 0x24
-; GCN-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
-; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GCN-NEXT: v_mul_u32_u24_e32 v2, v0, v0
-; GCN-NEXT: v_lshlrev_b32_e32 v3, 2, v0
-; GCN-NEXT: v_sub_nc_u32_e32 v0, v2, v0
-; GCN-NEXT: s_wait_kmcnt 0x0
-; GCN-NEXT: s_mov_b32 m0, s2
-; GCN-NEXT: global_store_b32 v3, v1, s[0:1]
-; GCN-NEXT: s_wakeup_barrier m0
-; GCN-NEXT: global_store_b32 v3, v0, s[0:1]
-; GCN-NEXT: s_nop 0
-; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GCN-NEXT: s_endpgm
+; GFX12-SDAG-LABEL: test4_s_wakeup_barrier_m0:
+; GFX12-SDAG: ; %bb.0: ; %entry
+; GFX12-SDAG-NEXT: s_load_b96 s[0:2], s[2:3], 0x24
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX12-SDAG-NEXT: v_mul_u32_u24_e32 v2, v0, v0
+; GFX12-SDAG-NEXT: v_lshlrev_b32_e32 v3, 2, v0
+; GFX12-SDAG-NEXT: v_sub_nc_u32_e32 v0, v2, v0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: s_mov_b32 m0, s2
+; GFX12-SDAG-NEXT: global_store_b32 v3, v1, s[0:1]
+; GFX12-SDAG-NEXT: s_wakeup_barrier m0
+; GFX12-SDAG-NEXT: global_store_b32 v3, v0, s[0:1]
+; GFX12-SDAG-NEXT: s_nop 0
+; GFX12-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-SDAG-NEXT: s_endpgm
;
-; GLOBAL-ISEL-LABEL: test4_s_wakeup_barrier_m0:
-; GLOBAL-ISEL: ; %bb.0: ; %entry
-; GLOBAL-ISEL-NEXT: s_load_b96 s[0:2], s[2:3], 0x24
-; GLOBAL-ISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GLOBAL-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
-; GLOBAL-ISEL-NEXT: v_mul_lo_u32 v1, v0, v0
-; GLOBAL-ISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0
-; GLOBAL-ISEL-NEXT: s_wait_kmcnt 0x0
-; GLOBAL-ISEL-NEXT: s_mov_b32 m0, s2
-; GLOBAL-ISEL-NEXT: global_store_b32 v3, v2, s[0:1]
-; GLOBAL-ISEL-NEXT: s_wakeup_barrier m0
-; GLOBAL-ISEL-NEXT: global_store_b32 v3, v0, s[0:1]
-; GLOBAL-ISEL-NEXT: s_nop 0
-; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GLOBAL-ISEL-NEXT: s_endpgm
+; GFX12-GISEL-LABEL: test4_s_wakeup_barrier_m0:
+; GFX12-GISEL: ; %bb.0: ; %entry
+; GFX12-GISEL-NEXT: s_load_b96 s[0:2], s[2:3], 0x24
+; GFX12-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
+; GFX12-GISEL-NEXT: v_mul_lo_u32 v1, v0, v0
+; GFX12-GISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: s_mov_b32 m0, s2
+; GFX12-GISEL-NEXT: global_store_b32 v3, v2, s[0:1]
+; GFX12-GISEL-NEXT: s_wakeup_barrier m0
+; GFX12-GISEL-NEXT: global_store_b32 v3, v0, s[0:1]
+; GFX12-GISEL-NEXT: s_nop 0
+; GFX12-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-GISEL-NEXT: s_endpgm
entry:
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
%tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp
@@ -1197,63 +1197,63 @@ entry:
}
define void @test5_s_wakeup_barrier_m0(i32 %arg) {
-; GCN-LABEL: test5_s_wakeup_barrier_m0:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_wait_loadcnt_dscnt 0x0
-; GCN-NEXT: s_wait_expcnt 0x0
-; GCN-NEXT: s_wait_samplecnt 0x0
-; GCN-NEXT: s_wait_bvhcnt 0x0
-; GCN-NEXT: s_wait_kmcnt 0x0
-; GCN-NEXT: v_readfirstlane_b32 s0, v0
-; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GCN-NEXT: s_mov_b32 m0, s0
-; GCN-NEXT: s_wakeup_barrier m0
-; GCN-NEXT: s_wait_alu 0xfffe
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; GFX12-SDAG-LABEL: test5_s_wakeup_barrier_m0:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-NEXT: s_mov_b32 m0, s0
+; GFX12-SDAG-NEXT: s_wakeup_barrier m0
+; GFX12-SDAG-NEXT: s_wait_alu 0xfffe
+; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GLOBAL-ISEL-LABEL: test5_s_wakeup_barrier_m0:
-; GLOBAL-ISEL: ; %bb.0:
-; GLOBAL-ISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GLOBAL-ISEL-NEXT: s_wait_expcnt 0x0
-; GLOBAL-ISEL-NEXT: s_wait_samplecnt 0x0
-; GLOBAL-ISEL-NEXT: s_wait_bvhcnt 0x0
-; GLOBAL-ISEL-NEXT: s_wait_kmcnt 0x0
-; GLOBAL-ISEL-NEXT: v_readfirstlane_b32 m0, v0
-; GLOBAL-ISEL-NEXT: s_wakeup_barrier m0
-; GLOBAL-ISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX12-GISEL-LABEL: test5_s_wakeup_barrier_m0:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 m0, v0
+; GFX12-GISEL-NEXT: s_wakeup_barrier m0
+; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
call void @llvm.amdgcn.s.wakeup.barrier(i32 %arg)
ret void
}
define amdgpu_kernel void @test1_s_get_barrier_state(ptr addrspace(1) %out) #0 {
-; GCN-LABEL: test1_s_get_barrier_state:
-; GCN: ; %bb.0: ; %entry
-; GCN-NEXT: s_get_barrier_state s4, -1
-; GCN-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
-; GCN-NEXT: s_wait_kmcnt 0x0
-; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GCN-NEXT: v_dual_mov_b32 v1, s4 :: v_dual_and_b32 v0, 0x3ff, v0
-; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GCN-NEXT: global_store_b32 v0, v1, s[0:1]
-; GCN-NEXT: s_nop 0
-; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GCN-NEXT: s_endpgm
+; GFX12-SDAG-LABEL: test1_s_get_barrier_state:
+; GFX12-SDAG: ; %bb.0: ; %entry
+; GFX12-SDAG-NEXT: s_get_barrier_state s4, -1
+; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v1, s4 :: v_dual_and_b32 v0, 0x3ff, v0
+; GFX12-SDAG-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX12-SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX12-SDAG-NEXT: s_nop 0
+; GFX12-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-SDAG-NEXT: s_endpgm
;
-; GLOBAL-ISEL-LABEL: test1_s_get_barrier_state:
-; GLOBAL-ISEL: ; %bb.0: ; %entry
-; GLOBAL-ISEL-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
-; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
-; GLOBAL-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_2)
-; GLOBAL-ISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GLOBAL-ISEL-NEXT: s_wait_kmcnt 0x0
-; GLOBAL-ISEL-NEXT: global_store_b32 v0, v1, s[0:1]
-; GLOBAL-ISEL-NEXT: s_get_barrier_state s2, -1
-; GLOBAL-ISEL-NEXT: s_wait_kmcnt 0x0
-; GLOBAL-ISEL-NEXT: v_mov_b32_e32 v1, s2
-; GLOBAL-ISEL-NEXT: global_store_b32 v0, v1, s[0:1]
-; GLOBAL-ISEL-NEXT: s_nop 0
-; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GLOBAL-ISEL-NEXT: s_endpgm
+; GFX12-GISEL-LABEL: test1_s_get_barrier_state:
+; GFX12-GISEL: ; %bb.0: ; %entry
+; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_2)
+; GFX12-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX12-GISEL-NEXT: s_get_barrier_state s2, -1
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v1, s2
+; GFX12-GISEL-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX12-GISEL-NEXT: s_nop 0
+; GFX12-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-GISEL-NEXT: s_endpgm
entry:
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
%tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp
@@ -1264,34 +1264,34 @@ entry:
}
define amdgpu_kernel void @test2_s_get_barrier_state(ptr addrspace(1) %out) #0 {
-; GCN-LABEL: test2_s_get_barrier_state:
-; GCN: ; %bb.0: ; %entry
-; GCN-NEXT: s_get_barrier_state s4, 1
-; GCN-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
-; GCN-NEXT: s_wait_kmcnt 0x0
-; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GCN-NEXT: v_dual_mov_b32 v1, s4 :: v_dual_and_b32 v0, 0x3ff, v0
-; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GCN-NEXT: global_store_b32 v0, v1, s[0:1]
-; GCN-NEXT: s_nop 0
-; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GCN-NEXT: s_endpgm
+; GFX12-SDAG-LABEL: test2_s_get_barrier_state:
+; GFX12-SDAG: ; %bb.0: ; %entry
+; GFX12-SDAG-NEXT: s_get_barrier_state s4, 1
+; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v1, s4 :: v_dual_and_b32 v0, 0x3ff, v0
+; GFX12-SDAG-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX12-SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX12-SDAG-NEXT: s_nop 0
+; GFX12-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-SDAG-NEXT: s_endpgm
;
-; GLOBAL-ISEL-LABEL: test2_s_get_barrier_state:
-; GLOBAL-ISEL: ; %bb.0: ; %entry
-; GLOBAL-ISEL-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
-; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
-; GLOBAL-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_2)
-; GLOBAL-ISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GLOBAL-ISEL-NEXT: s_wait_kmcnt 0x0
-; GLOBAL-ISEL-NEXT: global_store_b32 v0, v1, s[0:1]
-; GLOBAL-ISEL-NEXT: s_get_barrier_state s2, 1
-; GLOBAL-ISEL-NEXT: s_wait_kmcnt 0x0
-; GLOBAL-ISEL-NEXT: v_mov_b32_e32 v1, s2
-; GLOBAL-ISEL-NEXT: global_store_b32 v0, v1, s[0:1]
-; GLOBAL-ISEL-NEXT: s_nop 0
-; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GLOBAL-ISEL-NEXT: s_endpgm
+; GFX12-GISEL-LABEL: test2_s_get_barrier_state:
+; GFX12-GISEL: ; %bb.0: ; %entry
+; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_2)
+; GFX12-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX12-GISEL-NEXT: s_get_barrier_state s2, 1
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v1, s2
+; GFX12-GISEL-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX12-GISEL-NEXT: s_nop 0
+; GFX12-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-GISEL-NEXT: s_endpgm
entry:
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
%tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp
@@ -1302,34 +1302,34 @@ entry:
}
define amdgpu_kernel void @test3_s_get_barrier_state(ptr addrspace(1) %out) #0 {
-; GCN-LABEL: test3_s_get_barrier_state:
-; GCN: ; %bb.0: ; %entry
-; GCN-NEXT: s_get_barrier_state s4, 0
-; GCN-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
-; GCN-NEXT: s_wait_kmcnt 0x0
-; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GCN-NEXT: v_dual_mov_b32 v1, s4 :: v_dual_and_b32 v0, 0x3ff, v0
-; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GCN-NEXT: global_store_b32 v0, v1, s[0:1]
-; GCN-NEXT: s_nop 0
-; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GCN-NEXT: s_endpgm
+; GFX12-SDAG-LABEL: test3_s_get_barrier_state:
+; GFX12-SDAG: ; %bb.0: ; %entry
+; GFX12-SDAG-NEXT: s_get_barrier_state s4, 0
+; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v1, s4 :: v_dual_and_b32 v0, 0x3ff, v0
+; GFX12-SDAG-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX12-SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX12-SDAG-NEXT: s_nop 0
+; GFX12-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-SDAG-NEXT: s_endpgm
;
-; GLOBAL-ISEL-LABEL: test3_s_get_barrier_state:
-; GLOBAL-ISEL: ; %bb.0: ; %entry
-; GLOBAL-ISEL-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
-; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
-; GLOBAL-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_2)
-; GLOBAL-ISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GLOBAL-ISEL-NEXT: s_wait_kmcnt 0x0
-; GLOBAL-ISEL-NEXT: global_store_b32 v0, v1, s[0:1]
-; GLOBAL-ISEL-NEXT: s_get_barrier_state s2, 0
-; GLOBAL-ISEL-NEXT: s_wait_kmcnt 0x0
-; GLOBAL-ISEL-NEXT: v_mov_b32_e32 v1, s2
-; GLOBAL-ISEL-NEXT: global_store_b32 v0, v1, s[0:1]
-; GLOBAL-ISEL-NEXT: s_nop 0
-; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GLOBAL-ISEL-NEXT: s_endpgm
+; GFX12-GISEL-LABEL: test3_s_get_barrier_state:
+; GFX12-GISEL: ; %bb.0: ; %entry
+; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_2)
+; GFX12-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX12-GISEL-NEXT: s_get_barrier_state s2, 0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v1, s2
+; GFX12-GISEL-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX12-GISEL-NEXT: s_nop 0
+; GFX12-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-GISEL-NEXT: s_endpgm
entry:
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
%tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp
@@ -1340,41 +1340,23 @@ entry:
}
define amdgpu_kernel void @test4_s_get_barrier_state_m0(ptr addrspace(1) %out, i32 %bar) #0 {
-; GCN-LABEL: test4_s_get_barrier_state_m0:
-; GCN: ; %bb.0: ; %entry
-; GCN-NEXT: s_load_b96 s[0:2], s[2:3], 0x24
-; GCN-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
-; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GCN-NEXT: s_wait_kmcnt 0x0
-; GCN-NEXT: s_mov_b32 m0, s2
-; GCN-NEXT: global_store_b32 v0, v1, s[0:1]
-; GCN-NEXT: s_get_barrier_state s2, m0
-; GCN-NEXT: s_wait_kmcnt 0x0
-; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
-; GCN-NEXT: v_mov_b32_e32 v1, s2
-; GCN-NEXT: global_store_b32 v0, v1, s[0:1]
-; GCN-NEXT: s_nop 0
-; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GCN-NEXT: s_endpgm
-;
-; GLOBAL-ISEL-LABEL: test4_s_get_barrier_state_m0:
-; GLOBAL-ISEL: ; %bb.0: ; %entry
-; GLOBAL-ISEL-NEXT: s_load_b96 s[0:2], s[2:3], 0x24
-; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
-; GLOBAL-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GLOBAL-ISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GLOBAL-ISEL-NEXT: s_wait_kmcnt 0x0
-; GLOBAL-ISEL-NEXT: s_mov_b32 m0, s2
-; GLOBAL-ISEL-NEXT: global_store_b32 v0, v1, s[0:1]
-; GLOBAL-ISEL-NEXT: s_get_barrier_state s2, m0
-; GLOBAL-ISEL-NEXT: s_wait_kmcnt 0x0
-; GLOBAL-ISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
-; GLOBAL-ISEL-NEXT: v_mov_b32_e32 v1, s2
-; GLOBAL-ISEL-NEXT: global_store_b32 v0, v1, s[0:1]
-; GLOBAL-ISEL-NEXT: s_nop 0
-; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GLOBAL-ISEL-NEXT: s_endpgm
+; GFX12-LABEL: test4_s_get_barrier_state_m0:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_load_b96 s[0:2], s[2:3], 0x24
+; GFX12-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3ff, v0
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_mov_b32 m0, s2
+; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX12-NEXT: s_get_barrier_state s2, m0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
+; GFX12-NEXT: v_mov_b32_e32 v1, s2
+; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX12-NEXT: s_nop 0
+; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-NEXT: s_endpgm
entry:
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
%tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp
@@ -1385,76 +1367,76 @@ entry:
}
define i32 @test5_s_get_barrier_state_m0(i32 %arg) {
-; GCN-LABEL: test5_s_get_barrier_state_m0:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_wait_loadcnt_dscnt 0x0
-; GCN-NEXT: s_wait_expcnt 0x0
-; GCN-NEXT: s_wait_samplecnt 0x0
-; GCN-NEXT: s_wait_bvhcnt 0x0
-; GCN-NEXT: s_wait_kmcnt 0x0
-; GCN-NEXT: v_readfirstlane_b32 s0, v0
-; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
-; GCN-NEXT: s_mov_b32 m0, s0
-; GCN-NEXT: s_get_barrier_state s0, m0
-; GCN-NEXT: s_wait_kmcnt 0x0
-; GCN-NEXT: s_wait_alu 0xfffe
-; GCN-NEXT: v_mov_b32_e32 v0, s0
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; GFX12-SDAG-LABEL: test5_s_get_barrier_state_m0:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
+; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
+; GFX12-SDAG-NEXT: s_mov_b32 m0, s0
+; GFX12-SDAG-NEXT: s_get_barrier_state s0, m0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: s_wait_alu 0xfffe
+; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GLOBAL-ISEL-LABEL: test5_s_get_barrier_state_m0:
-; GLOBAL-ISEL: ; %bb.0:
-; GLOBAL-ISEL-NEXT: s_wait_loadcnt_dscnt 0x0
-; GLOBAL-ISEL-NEXT: s_wait_expcnt 0x0
-; GLOBAL-ISEL-NEXT: s_wait_samplecnt 0x0
-; GLOBAL-ISEL-NEXT: s_wait_bvhcnt 0x0
-; GLOBAL-ISEL-NEXT: s_wait_kmcnt 0x0
-; GLOBAL-ISEL-NEXT: v_readfirstlane_b32 m0, v0
-; GLOBAL-ISEL-NEXT: s_get_barrier_state s0, m0
-; GLOBAL-ISEL-NEXT: s_wait_kmcnt 0x0
-; GLOBAL-ISEL-NEXT: s_wait_alu 0xfffe
-; GLOBAL-ISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GLOBAL-ISEL-NEXT: v_mov_b32_e32 v0, s0
-; GLOBAL-ISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX12-GISEL-LABEL: test5_s_get_barrier_state_m0:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
+; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 m0, v0
+; GFX12-GISEL-NEXT: s_get_barrier_state s0, m0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: s_wait_alu 0xfffe
+; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
%state = call i32 @llvm.amdgcn.s.get.barrier.state(i32 %arg)
ret i32 %state
}
define amdgpu_kernel void @test_barrier_convert(ptr addrspace(1) %out) #0 {
-; GCN-LABEL: test_barrier_convert:
-; GCN: ; %bb.0: ; %entry
-; GCN-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
-; GCN-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GCN-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
-; GCN-NEXT: v_mul_u32_u24_e32 v1, v0, v0
-; GCN-NEXT: v_sub_nc_u32_e32 v0, v1, v0
-; GCN-NEXT: s_wait_kmcnt 0x0
-; GCN-NEXT: global_store_b32 v3, v2, s[0:1]
-; GCN-NEXT: s_wait_storecnt 0x0
-; GCN-NEXT: s_barrier_signal -1
-; GCN-NEXT: s_barrier_wait -1
-; GCN-NEXT: global_store_b32 v3, v0, s[0:1]
-; GCN-NEXT: s_nop 0
-; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GCN-NEXT: s_endpgm
+; GFX12-SDAG-LABEL: test_barrier_convert:
+; GFX12-SDAG: ; %bb.0: ; %entry
+; GFX12-SDAG-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
+; GFX12-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
+; GFX12-SDAG-NEXT: v_mul_u32_u24_e32 v1, v0, v0
+; GFX12-SDAG-NEXT: v_sub_nc_u32_e32 v0, v1, v0
+; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
+; GFX12-SDAG-NEXT: global_store_b32 v3, v2, s[0:1]
+; GFX12-SDAG-NEXT: s_wait_storecnt 0x0
+; GFX12-SDAG-NEXT: s_barrier_signal -1
+; GFX12-SDAG-NEXT: s_barrier_wait -1
+; GFX12-SDAG-NEXT: global_store_b32 v3, v0, s[0:1]
+; GFX12-SDAG-NEXT: s_nop 0
+; GFX12-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-SDAG-NEXT: s_endpgm
;
-; GLOBAL-ISEL-LABEL: test_barrier_convert:
-; GLOBAL-ISEL: ; %bb.0: ; %entry
-; GLOBAL-ISEL-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
-; GLOBAL-ISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; GLOBAL-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
-; GLOBAL-ISEL-NEXT: v_mul_lo_u32 v1, v0, v0
-; GLOBAL-ISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0
-; GLOBAL-ISEL-NEXT: s_wait_kmcnt 0x0
-; GLOBAL-ISEL-NEXT: global_store_b32 v3, v2, s[0:1]
-; GLOBAL-ISEL-NEXT: s_wait_storecnt 0x0
-; GLOBAL-ISEL-NEXT: s_barrier_signal -1
-; GLOBAL-ISEL-NEXT: s_barrier_wait -1
-; GLOBAL-ISEL-NEXT: global_store_b32 v3, v0, s[0:1]
-; GLOBAL-ISEL-NEXT: s_nop 0
-; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
-; GLOBAL-ISEL-NEXT: s_endpgm
+; GFX12-GISEL-LABEL: test_barrier_convert:
+; GFX12-GISEL: ; %bb.0: ; %entry
+; GFX12-GISEL-NEXT: s_load_b64 s[0:1], s[2:3], 0x24
+; GFX12-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
+; GFX12-GISEL-NEXT: v_mul_lo_u32 v1, v0, v0
+; GFX12-GISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0
+; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12-GISEL-NEXT: global_store_b32 v3, v2, s[0:1]
+; GFX12-GISEL-NEXT: s_wait_storecnt 0x0
+; GFX12-GISEL-NEXT: s_barrier_signal -1
+; GFX12-GISEL-NEXT: s_barrier_wait -1
+; GFX12-GISEL-NEXT: global_store_b32 v3, v0, s[0:1]
+; GFX12-GISEL-NEXT: s_nop 0
+; GFX12-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX12-GISEL-NEXT: s_endpgm
entry:
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
%tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp
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