[llvm] [RISC-V][GISEL] Select G_BITCAST for scalable vectors (PR #101486)
Jiahan Xie via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 24 06:08:10 PDT 2024
https://github.com/jiahanxie353 updated https://github.com/llvm/llvm-project/pull/101486
>From cea2c3e277e90cb4528706240b0573cefb127e9a Mon Sep 17 00:00:00 2001
From: Jiahan Xie <jx353 at cornell.edu>
Date: Thu, 1 Aug 2024 09:27:30 -0400
Subject: [PATCH 1/5] bitcast as copy?
---
llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 92d00c26bd219c..16b0e7e0a56072 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -559,6 +559,7 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
case TargetOpcode::G_INTTOPTR:
case TargetOpcode::G_TRUNC:
case TargetOpcode::G_FREEZE:
+ case TargetOpcode::G_BITCAST:
return selectCopy(MI, MRI);
case TargetOpcode::G_CONSTANT: {
Register DstReg = MI.getOperand(0).getReg();
>From 7d9d4f211cbd0cabeb9b3ffa9f2656558818253c Mon Sep 17 00:00:00 2001
From: Jiahan Xie <jx353 at cornell.edu>
Date: Mon, 23 Sep 2024 16:48:11 -0400
Subject: [PATCH 2/5] add instr select tests for load and store
---
.../instruction-select/rvv/load.mir | 869 ++++++++++++++++++
.../instruction-select/rvv/store.mir | 869 ++++++++++++++++++
2 files changed, 1738 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/load.mir
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/store.mir
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/load.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/load.mir
new file mode 100644
index 00000000000000..55b210879e66ee
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/load.mir
@@ -0,0 +1,869 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV32I %s
+# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV64I %s
+--- |
+
+ define <vscale x 1 x i8> @vload_nx1i8(ptr %pa) #0 {
+ %va = load <vscale x 1 x i8>, ptr %pa, align 1
+ ret <vscale x 1 x i8> %va
+ }
+
+ define <vscale x 2 x i8> @vload_nx2i8(ptr %pa) #0 {
+ %va = load <vscale x 2 x i8>, ptr %pa, align 2
+ ret <vscale x 2 x i8> %va
+ }
+
+ define <vscale x 4 x i8> @vload_nx4i8(ptr %pa) #0 {
+ %va = load <vscale x 4 x i8>, ptr %pa, align 4
+ ret <vscale x 4 x i8> %va
+ }
+
+ define <vscale x 8 x i8> @vload_nx8i8(ptr %pa) #0 {
+ %va = load <vscale x 8 x i8>, ptr %pa, align 8
+ ret <vscale x 8 x i8> %va
+ }
+
+ define <vscale x 16 x i8> @vload_nx16i8(ptr %pa) #0 {
+ %va = load <vscale x 16 x i8>, ptr %pa, align 16
+ ret <vscale x 16 x i8> %va
+ }
+
+ define <vscale x 32 x i8> @vload_nx32i8(ptr %pa) #0 {
+ %va = load <vscale x 32 x i8>, ptr %pa, align 32
+ ret <vscale x 32 x i8> %va
+ }
+
+ define <vscale x 64 x i8> @vload_nx64i8(ptr %pa) #0 {
+ %va = load <vscale x 64 x i8>, ptr %pa, align 64
+ ret <vscale x 64 x i8> %va
+ }
+
+ define <vscale x 1 x i16> @vload_nx1i16(ptr %pa) #0 {
+ %va = load <vscale x 1 x i16>, ptr %pa, align 2
+ ret <vscale x 1 x i16> %va
+ }
+
+ define <vscale x 2 x i16> @vload_nx2i16(ptr %pa) #0 {
+ %va = load <vscale x 2 x i16>, ptr %pa, align 4
+ ret <vscale x 2 x i16> %va
+ }
+
+ define <vscale x 4 x i16> @vload_nx4i16(ptr %pa) #0 {
+ %va = load <vscale x 4 x i16>, ptr %pa, align 8
+ ret <vscale x 4 x i16> %va
+ }
+
+ define <vscale x 8 x i16> @vload_nx8i16(ptr %pa) #0 {
+ %va = load <vscale x 8 x i16>, ptr %pa, align 16
+ ret <vscale x 8 x i16> %va
+ }
+
+ define <vscale x 16 x i16> @vload_nx16i16(ptr %pa) #0 {
+ %va = load <vscale x 16 x i16>, ptr %pa, align 32
+ ret <vscale x 16 x i16> %va
+ }
+
+ define <vscale x 32 x i16> @vload_nx32i16(ptr %pa) #0 {
+ %va = load <vscale x 32 x i16>, ptr %pa, align 64
+ ret <vscale x 32 x i16> %va
+ }
+
+ define <vscale x 1 x i32> @vload_nx1i32(ptr %pa) #0 {
+ %va = load <vscale x 1 x i32>, ptr %pa, align 4
+ ret <vscale x 1 x i32> %va
+ }
+
+ define <vscale x 2 x i32> @vload_nx2i32(ptr %pa) #0 {
+ %va = load <vscale x 2 x i32>, ptr %pa, align 8
+ ret <vscale x 2 x i32> %va
+ }
+
+ define <vscale x 4 x i32> @vload_nx4i32(ptr %pa) #0 {
+ %va = load <vscale x 4 x i32>, ptr %pa, align 16
+ ret <vscale x 4 x i32> %va
+ }
+
+ define <vscale x 8 x i32> @vload_nx8i32(ptr %pa) #0 {
+ %va = load <vscale x 8 x i32>, ptr %pa, align 32
+ ret <vscale x 8 x i32> %va
+ }
+
+ define <vscale x 16 x i32> @vload_nx16i32(ptr %pa) #0 {
+ %va = load <vscale x 16 x i32>, ptr %pa, align 64
+ ret <vscale x 16 x i32> %va
+ }
+
+ define <vscale x 1 x i64> @vload_nx1i64(ptr %pa) #0 {
+ %va = load <vscale x 1 x i64>, ptr %pa, align 8
+ ret <vscale x 1 x i64> %va
+ }
+
+ define <vscale x 2 x i64> @vload_nx2i64(ptr %pa) #0 {
+ %va = load <vscale x 2 x i64>, ptr %pa, align 16
+ ret <vscale x 2 x i64> %va
+ }
+
+ define <vscale x 4 x i64> @vload_nx4i64(ptr %pa) #0 {
+ %va = load <vscale x 4 x i64>, ptr %pa, align 32
+ ret <vscale x 4 x i64> %va
+ }
+
+ define <vscale x 8 x i64> @vload_nx8i64(ptr %pa) #0 {
+ %va = load <vscale x 8 x i64>, ptr %pa, align 64
+ ret <vscale x 8 x i64> %va
+ }
+
+ define <vscale x 16 x i8> @vload_nx16i8_align1(ptr %pa) #0 {
+ %va = load <vscale x 16 x i8>, ptr %pa, align 1
+ ret <vscale x 16 x i8> %va
+ }
+
+ define <vscale x 16 x i8> @vload_nx16i8_align2(ptr %pa) #0 {
+ %va = load <vscale x 16 x i8>, ptr %pa, align 2
+ ret <vscale x 16 x i8> %va
+ }
+
+ define <vscale x 16 x i8> @vload_nx16i8_align16(ptr %pa) #0 {
+ %va = load <vscale x 16 x i8>, ptr %pa, align 16
+ ret <vscale x 16 x i8> %va
+ }
+
+ define <vscale x 16 x i8> @vload_nx16i8_align64(ptr %pa) #0 {
+ %va = load <vscale x 16 x i8>, ptr %pa, align 64
+ ret <vscale x 16 x i8> %va
+ }
+
+ define <vscale x 4 x i16> @vload_nx4i16_align1(ptr %pa) #0 {
+ %va = load <vscale x 4 x i16>, ptr %pa, align 1
+ ret <vscale x 4 x i16> %va
+ }
+
+ define <vscale x 4 x i16> @vload_nx4i16_align2(ptr %pa) #0 {
+ %va = load <vscale x 4 x i16>, ptr %pa, align 2
+ ret <vscale x 4 x i16> %va
+ }
+
+ define <vscale x 4 x i16> @vload_nx4i16_align4(ptr %pa) #0 {
+ %va = load <vscale x 4 x i16>, ptr %pa, align 4
+ ret <vscale x 4 x i16> %va
+ }
+
+ define <vscale x 4 x i16> @vload_nx4i16_align8(ptr %pa) #0 {
+ %va = load <vscale x 4 x i16>, ptr %pa, align 8
+ ret <vscale x 4 x i16> %va
+ }
+
+ define <vscale x 4 x i16> @vload_nx4i16_align16(ptr %pa) #0 {
+ %va = load <vscale x 4 x i16>, ptr %pa, align 16
+ ret <vscale x 4 x i16> %va
+ }
+
+ define <vscale x 2 x i32> @vload_nx2i32_align2(ptr %pa) #0 {
+ %va = load <vscale x 2 x i32>, ptr %pa, align 2
+ ret <vscale x 2 x i32> %va
+ }
+
+ define <vscale x 2 x i32> @vload_nx2i32_align4(ptr %pa) #0 {
+ %va = load <vscale x 2 x i32>, ptr %pa, align 4
+ ret <vscale x 2 x i32> %va
+ }
+
+ define <vscale x 2 x i32> @vload_nx2i32_align8(ptr %pa) #0 {
+ %va = load <vscale x 2 x i32>, ptr %pa, align 8
+ ret <vscale x 2 x i32> %va
+ }
+
+ define <vscale x 2 x i32> @vload_nx2i32_align16(ptr %pa) #0 {
+ %va = load <vscale x 2 x i32>, ptr %pa, align 16
+ ret <vscale x 2 x i32> %va
+ }
+
+ define <vscale x 2 x i32> @vload_nx2i32_align256(ptr %pa) #0 {
+ %va = load <vscale x 2 x i32>, ptr %pa, align 256
+ ret <vscale x 2 x i32> %va
+ }
+
+ define <vscale x 2 x i64> @vload_nx2i64_align4(ptr %pa) #0 {
+ %va = load <vscale x 2 x i64>, ptr %pa, align 4
+ ret <vscale x 2 x i64> %va
+ }
+
+ define <vscale x 2 x i64> @vload_nx2i64_align8(ptr %pa) #0 {
+ %va = load <vscale x 2 x i64>, ptr %pa, align 8
+ ret <vscale x 2 x i64> %va
+ }
+
+ define <vscale x 2 x i64> @vload_nx2i64_align16(ptr %pa) #0 {
+ %va = load <vscale x 2 x i64>, ptr %pa, align 16
+ ret <vscale x 2 x i64> %va
+ }
+
+ define <vscale x 2 x i64> @vload_nx2i64_align32(ptr %pa) #0 {
+ %va = load <vscale x 2 x i64>, ptr %pa, align 32
+ ret <vscale x 2 x i64> %va
+ }
+
+ define <vscale x 1 x ptr> @vload_nx1ptr(ptr %pa) #0 {
+ %va = load <vscale x 1 x ptr>, ptr %pa, align 4
+ ret <vscale x 1 x ptr> %va
+ }
+
+ define <vscale x 2 x ptr> @vload_nx2ptr(ptr %pa) #0 {
+ %va = load <vscale x 2 x ptr>, ptr %pa, align 8
+ ret <vscale x 2 x ptr> %va
+ }
+
+ define <vscale x 8 x ptr> @vload_nx8ptr(ptr %pa) #0 {
+ %va = load <vscale x 8 x ptr>, ptr %pa, align 32
+ ret <vscale x 8 x ptr> %va
+ }
+
+...
+---
+name: vload_nx1i8
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 1 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 1 x s8>) from %ir.pa)
+ $v8 = COPY %1(<vscale x 1 x s8>)
+ PseudoRET implicit $v8
+
+...
+---
+name: vload_nx2i8
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 2 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s8>) from %ir.pa)
+ $v8 = COPY %1(<vscale x 2 x s8>)
+ PseudoRET implicit $v8
+
+...
+---
+name: vload_nx4i8
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 4 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 4 x s8>) from %ir.pa)
+ $v8 = COPY %1(<vscale x 4 x s8>)
+ PseudoRET implicit $v8
+
+...
+---
+name: vload_nx8i8
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 8 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 8 x s8>) from %ir.pa)
+ $v8 = COPY %1(<vscale x 8 x s8>)
+ PseudoRET implicit $v8
+
+...
+---
+name: vload_nx16i8
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 16 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 16 x s8>) from %ir.pa)
+ $v8m2 = COPY %1(<vscale x 16 x s8>)
+ PseudoRET implicit $v8m2
+
+...
+---
+name: vload_nx32i8
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 32 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 32 x s8>) from %ir.pa)
+ $v8m4 = COPY %1(<vscale x 32 x s8>)
+ PseudoRET implicit $v8m4
+
+...
+---
+name: vload_nx64i8
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 64 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 64 x s8>) from %ir.pa)
+ $v8m8 = COPY %1(<vscale x 64 x s8>)
+ PseudoRET implicit $v8m8
+
+...
+---
+name: vload_nx1i16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 1 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 1 x s16>) from %ir.pa)
+ $v8 = COPY %1(<vscale x 1 x s16>)
+ PseudoRET implicit $v8
+
+...
+---
+name: vload_nx2i16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 2 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s16>) from %ir.pa)
+ $v8 = COPY %1(<vscale x 2 x s16>)
+ PseudoRET implicit $v8
+
+...
+---
+name: vload_nx4i16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 4 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 4 x s16>) from %ir.pa)
+ $v8 = COPY %1(<vscale x 4 x s16>)
+ PseudoRET implicit $v8
+
+...
+---
+name: vload_nx8i16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 8 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 8 x s16>) from %ir.pa)
+ $v8m2 = COPY %1(<vscale x 8 x s16>)
+ PseudoRET implicit $v8m2
+
+...
+---
+name: vload_nx16i16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 16 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 16 x s16>) from %ir.pa)
+ $v8m4 = COPY %1(<vscale x 16 x s16>)
+ PseudoRET implicit $v8m4
+
+...
+---
+name: vload_nx32i16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 32 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 32 x s16>) from %ir.pa)
+ $v8m8 = COPY %1(<vscale x 32 x s16>)
+ PseudoRET implicit $v8m8
+
+...
+---
+name: vload_nx1i32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 1 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 1 x s32>) from %ir.pa)
+ $v8 = COPY %1(<vscale x 1 x s32>)
+ PseudoRET implicit $v8
+
+...
+---
+name: vload_nx2i32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 2 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s32>) from %ir.pa)
+ $v8 = COPY %1(<vscale x 2 x s32>)
+ PseudoRET implicit $v8
+
+...
+---
+name: vload_nx4i32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 4 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 4 x s32>) from %ir.pa)
+ $v8m2 = COPY %1(<vscale x 4 x s32>)
+ PseudoRET implicit $v8m2
+
+...
+---
+name: vload_nx8i32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 8 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 8 x s32>) from %ir.pa)
+ $v8m4 = COPY %1(<vscale x 8 x s32>)
+ PseudoRET implicit $v8m4
+
+...
+---
+name: vload_nx16i32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 16 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 16 x s32>) from %ir.pa)
+ $v8m8 = COPY %1(<vscale x 16 x s32>)
+ PseudoRET implicit $v8m8
+
+...
+---
+name: vload_nx1i64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 1 x s64>) = G_LOAD %0(p0) :: (load (<vscale x 1 x s64>) from %ir.pa)
+ $v8 = COPY %1(<vscale x 1 x s64>)
+ PseudoRET implicit $v8
+
+...
+---
+name: vload_nx2i64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 2 x s64>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s64>) from %ir.pa)
+ $v8m2 = COPY %1(<vscale x 2 x s64>)
+ PseudoRET implicit $v8m2
+
+...
+---
+name: vload_nx4i64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 4 x s64>) = G_LOAD %0(p0) :: (load (<vscale x 4 x s64>) from %ir.pa)
+ $v8m4 = COPY %1(<vscale x 4 x s64>)
+ PseudoRET implicit $v8m4
+
+...
+---
+name: vload_nx8i64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 8 x s64>) = G_LOAD %0(p0) :: (load (<vscale x 8 x s64>) from %ir.pa)
+ $v8m8 = COPY %1(<vscale x 8 x s64>)
+ PseudoRET implicit $v8m8
+
+...
+---
+name: vload_nx16i8_align1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 16 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 16 x s8>) from %ir.pa, align 1)
+ $v8m2 = COPY %1(<vscale x 16 x s8>)
+ PseudoRET implicit $v8m2
+
+...
+---
+name: vload_nx16i8_align2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 16 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 16 x s8>) from %ir.pa, align 2)
+ $v8m2 = COPY %1(<vscale x 16 x s8>)
+ PseudoRET implicit $v8m2
+
+...
+---
+name: vload_nx16i8_align16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 16 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 16 x s8>) from %ir.pa)
+ $v8m2 = COPY %1(<vscale x 16 x s8>)
+ PseudoRET implicit $v8m2
+
+...
+---
+name: vload_nx16i8_align64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 16 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 16 x s8>) from %ir.pa, align 64)
+ $v8m2 = COPY %1(<vscale x 16 x s8>)
+ PseudoRET implicit $v8m2
+
+...
+---
+name: vload_nx4i16_align1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10
+
+ %0:gprb(p0) = COPY $x10
+ %2:vrb(<vscale x 8 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 8 x s8>) from %ir.pa, align 1)
+ %1:vrb(<vscale x 4 x s16>) = G_BITCAST %2(<vscale x 8 x s8>)
+ $v8 = COPY %1(<vscale x 4 x s16>)
+ PseudoRET implicit $v8
+
+...
+---
+name: vload_nx4i16_align2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 4 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 4 x s16>) from %ir.pa, align 2)
+ $v8 = COPY %1(<vscale x 4 x s16>)
+ PseudoRET implicit $v8
+
+...
+---
+name: vload_nx4i16_align4
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 4 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 4 x s16>) from %ir.pa, align 4)
+ $v8 = COPY %1(<vscale x 4 x s16>)
+ PseudoRET implicit $v8
+
+...
+---
+name: vload_nx4i16_align8
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 4 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 4 x s16>) from %ir.pa)
+ $v8 = COPY %1(<vscale x 4 x s16>)
+ PseudoRET implicit $v8
+
+...
+---
+name: vload_nx4i16_align16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 4 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 4 x s16>) from %ir.pa, align 16)
+ $v8 = COPY %1(<vscale x 4 x s16>)
+ PseudoRET implicit $v8
+
+...
+---
+name: vload_nx2i32_align2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10
+
+ %0:gprb(p0) = COPY $x10
+ %2:vrb(<vscale x 8 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 8 x s8>) from %ir.pa, align 2)
+ %1:vrb(<vscale x 2 x s32>) = G_BITCAST %2(<vscale x 8 x s8>)
+ $v8 = COPY %1(<vscale x 2 x s32>)
+ PseudoRET implicit $v8
+
+...
+---
+name: vload_nx2i32_align4
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 2 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s32>) from %ir.pa, align 4)
+ $v8 = COPY %1(<vscale x 2 x s32>)
+ PseudoRET implicit $v8
+
+...
+---
+name: vload_nx2i32_align8
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 2 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s32>) from %ir.pa)
+ $v8 = COPY %1(<vscale x 2 x s32>)
+ PseudoRET implicit $v8
+
+...
+---
+name: vload_nx2i32_align16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 2 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s32>) from %ir.pa, align 16)
+ $v8 = COPY %1(<vscale x 2 x s32>)
+ PseudoRET implicit $v8
+
+...
+---
+name: vload_nx2i32_align256
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 2 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s32>) from %ir.pa, align 256)
+ $v8 = COPY %1(<vscale x 2 x s32>)
+ PseudoRET implicit $v8
+
+...
+---
+name: vload_nx2i64_align4
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10
+
+ %0:gprb(p0) = COPY $x10
+ %2:vrb(<vscale x 16 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 16 x s8>) from %ir.pa, align 4)
+ %1:vrb(<vscale x 2 x s64>) = G_BITCAST %2(<vscale x 16 x s8>)
+ $v8m2 = COPY %1(<vscale x 2 x s64>)
+ PseudoRET implicit $v8m2
+
+...
+---
+name: vload_nx2i64_align8
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 2 x s64>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s64>) from %ir.pa, align 8)
+ $v8m2 = COPY %1(<vscale x 2 x s64>)
+ PseudoRET implicit $v8m2
+
+...
+---
+name: vload_nx2i64_align16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 2 x s64>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s64>) from %ir.pa)
+ $v8m2 = COPY %1(<vscale x 2 x s64>)
+ PseudoRET implicit $v8m2
+
+...
+---
+name: vload_nx2i64_align32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 2 x s64>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s64>) from %ir.pa, align 32)
+ $v8m2 = COPY %1(<vscale x 2 x s64>)
+ PseudoRET implicit $v8m2
+
+...
+---
+name: vload_nx1ptr
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 1 x p0>) = G_LOAD %0(p0) :: (load (<vscale x 1 x p0>) from %ir.pa)
+ $v8 = COPY %1(<vscale x 1 x p0>)
+ PseudoRET implicit $v8
+
+...
+---
+name: vload_nx2ptr
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 2 x p0>) = G_LOAD %0(p0) :: (load (<vscale x 2 x p0>) from %ir.pa)
+ $v8 = COPY %1(<vscale x 2 x p0>)
+ PseudoRET implicit $v8
+
+...
+---
+name: vload_nx8ptr
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 8 x p0>) = G_LOAD %0(p0) :: (load (<vscale x 8 x p0>) from %ir.pa)
+ $v8m4 = COPY %1(<vscale x 8 x p0>)
+ PseudoRET implicit $v8m4
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/store.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/store.mir
new file mode 100644
index 00000000000000..05c00f672dea37
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/store.mir
@@ -0,0 +1,869 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV32I %s
+# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV64I %s
+--- |
+
+ define void @vstore_nx1i8(ptr %pa, <vscale x 1 x i8> %b) #0 {
+ store <vscale x 1 x i8> %b, ptr %pa, align 1
+ ret void
+ }
+
+ define void @vstore_nx2i8(ptr %pa, <vscale x 2 x i8> %b) #0 {
+ store <vscale x 2 x i8> %b, ptr %pa, align 2
+ ret void
+ }
+
+ define void @vstore_nx4i8(ptr %pa, <vscale x 4 x i8> %b) #0 {
+ store <vscale x 4 x i8> %b, ptr %pa, align 4
+ ret void
+ }
+
+ define void @vstore_nx8i8(ptr %pa, <vscale x 8 x i8> %b) #0 {
+ store <vscale x 8 x i8> %b, ptr %pa, align 8
+ ret void
+ }
+
+ define void @vstore_nx16i8(ptr %pa, <vscale x 16 x i8> %b) #0 {
+ store <vscale x 16 x i8> %b, ptr %pa, align 16
+ ret void
+ }
+
+ define void @vstore_nx32i8(ptr %pa, <vscale x 32 x i8> %b) #0 {
+ store <vscale x 32 x i8> %b, ptr %pa, align 32
+ ret void
+ }
+
+ define void @vstore_nx64i8(ptr %pa, <vscale x 64 x i8> %b) #0 {
+ store <vscale x 64 x i8> %b, ptr %pa, align 64
+ ret void
+ }
+
+ define void @vstore_nx1i16(ptr %pa, <vscale x 1 x i16> %b) #0 {
+ store <vscale x 1 x i16> %b, ptr %pa, align 2
+ ret void
+ }
+
+ define void @vstore_nx2i16(ptr %pa, <vscale x 2 x i16> %b) #0 {
+ store <vscale x 2 x i16> %b, ptr %pa, align 4
+ ret void
+ }
+
+ define void @vstore_nx4i16(ptr %pa, <vscale x 4 x i16> %b) #0 {
+ store <vscale x 4 x i16> %b, ptr %pa, align 8
+ ret void
+ }
+
+ define void @vstore_nx8i16(ptr %pa, <vscale x 8 x i16> %b) #0 {
+ store <vscale x 8 x i16> %b, ptr %pa, align 16
+ ret void
+ }
+
+ define void @vstore_nx16i16(ptr %pa, <vscale x 16 x i16> %b) #0 {
+ store <vscale x 16 x i16> %b, ptr %pa, align 32
+ ret void
+ }
+
+ define void @vstore_nx32i16(ptr %pa, <vscale x 32 x i16> %b) #0 {
+ store <vscale x 32 x i16> %b, ptr %pa, align 64
+ ret void
+ }
+
+ define void @vstore_nx1i32(ptr %pa, <vscale x 1 x i32> %b) #0 {
+ store <vscale x 1 x i32> %b, ptr %pa, align 4
+ ret void
+ }
+
+ define void @vstore_nx2i32(ptr %pa, <vscale x 2 x i32> %b) #0 {
+ store <vscale x 2 x i32> %b, ptr %pa, align 8
+ ret void
+ }
+
+ define void @vstore_nx4i32(ptr %pa, <vscale x 4 x i32> %b) #0 {
+ store <vscale x 4 x i32> %b, ptr %pa, align 16
+ ret void
+ }
+
+ define void @vstore_nx8i32(ptr %pa, <vscale x 8 x i32> %b) #0 {
+ store <vscale x 8 x i32> %b, ptr %pa, align 32
+ ret void
+ }
+
+ define void @vstore_nx16i32(ptr %pa, <vscale x 16 x i32> %b) #0 {
+ store <vscale x 16 x i32> %b, ptr %pa, align 64
+ ret void
+ }
+
+ define void @vstore_nx1i64(ptr %pa, <vscale x 1 x i64> %b) #0 {
+ store <vscale x 1 x i64> %b, ptr %pa, align 8
+ ret void
+ }
+
+ define void @vstore_nx2i64(ptr %pa, <vscale x 2 x i64> %b) #0 {
+ store <vscale x 2 x i64> %b, ptr %pa, align 16
+ ret void
+ }
+
+ define void @vstore_nx4i64(ptr %pa, <vscale x 4 x i64> %b) #0 {
+ store <vscale x 4 x i64> %b, ptr %pa, align 32
+ ret void
+ }
+
+ define void @vstore_nx8i64(ptr %pa, <vscale x 8 x i64> %b) #0 {
+ store <vscale x 8 x i64> %b, ptr %pa, align 64
+ ret void
+ }
+
+ define void @vstore_nx16i8_align1(ptr %pa, <vscale x 16 x i8> %b) #0 {
+ store <vscale x 16 x i8> %b, ptr %pa, align 1
+ ret void
+ }
+
+ define void @vstore_nx16i8_align2(ptr %pa, <vscale x 16 x i8> %b) #0 {
+ store <vscale x 16 x i8> %b, ptr %pa, align 2
+ ret void
+ }
+
+ define void @vstore_nx16i8_align16(ptr %pa, <vscale x 16 x i8> %b) #0 {
+ store <vscale x 16 x i8> %b, ptr %pa, align 16
+ ret void
+ }
+
+ define void @vstore_nx16i8_align64(ptr %pa, <vscale x 16 x i8> %b) #0 {
+ store <vscale x 16 x i8> %b, ptr %pa, align 64
+ ret void
+ }
+
+ define void @vstore_nx4i16_align1(ptr %pa, <vscale x 4 x i16> %b) #0 {
+ store <vscale x 4 x i16> %b, ptr %pa, align 1
+ ret void
+ }
+
+ define void @vstore_nx4i16_align2(ptr %pa, <vscale x 4 x i16> %b) #0 {
+ store <vscale x 4 x i16> %b, ptr %pa, align 2
+ ret void
+ }
+
+ define void @vstore_nx4i16_align4(ptr %pa, <vscale x 4 x i16> %b) #0 {
+ store <vscale x 4 x i16> %b, ptr %pa, align 4
+ ret void
+ }
+
+ define void @vstore_nx4i16_align8(ptr %pa, <vscale x 4 x i16> %b) #0 {
+ store <vscale x 4 x i16> %b, ptr %pa, align 8
+ ret void
+ }
+
+ define void @vstore_nx4i16_align16(ptr %pa, <vscale x 4 x i16> %b) #0 {
+ store <vscale x 4 x i16> %b, ptr %pa, align 16
+ ret void
+ }
+
+ define void @vstore_nx2i32_align2(ptr %pa, <vscale x 2 x i32> %b) #0 {
+ store <vscale x 2 x i32> %b, ptr %pa, align 2
+ ret void
+ }
+
+ define void @vstore_nx2i32_align4(ptr %pa, <vscale x 2 x i32> %b) #0 {
+ store <vscale x 2 x i32> %b, ptr %pa, align 4
+ ret void
+ }
+
+ define void @vstore_nx2i32_align8(ptr %pa, <vscale x 2 x i32> %b) #0 {
+ store <vscale x 2 x i32> %b, ptr %pa, align 8
+ ret void
+ }
+
+ define void @vstore_nx2i32_align16(ptr %pa, <vscale x 2 x i32> %b) #0 {
+ store <vscale x 2 x i32> %b, ptr %pa, align 16
+ ret void
+ }
+
+ define void @vstore_nx2i32_align256(ptr %pa, <vscale x 2 x i32> %b) #0 {
+ store <vscale x 2 x i32> %b, ptr %pa, align 256
+ ret void
+ }
+
+ define void @vstore_nx2i64_align4(ptr %pa, <vscale x 2 x i64> %b) #0 {
+ store <vscale x 2 x i64> %b, ptr %pa, align 4
+ ret void
+ }
+
+ define void @vstore_nx2i64_align8(ptr %pa, <vscale x 2 x i64> %b) #0 {
+ store <vscale x 2 x i64> %b, ptr %pa, align 8
+ ret void
+ }
+
+ define void @vstore_nx2i64_align16(ptr %pa, <vscale x 2 x i64> %b) #0 {
+ store <vscale x 2 x i64> %b, ptr %pa, align 16
+ ret void
+ }
+
+ define void @vstore_nx2i64_align32(ptr %pa, <vscale x 2 x i64> %b) #0 {
+ store <vscale x 2 x i64> %b, ptr %pa, align 32
+ ret void
+ }
+
+ define void @vstore_nx1ptr(ptr %pa, <vscale x 1 x ptr> %b) #0 {
+ store <vscale x 1 x ptr> %b, ptr %pa, align 4
+ ret void
+ }
+
+ define void @vstore_nx2ptr(ptr %pa, <vscale x 2 x ptr> %b) #0 {
+ store <vscale x 2 x ptr> %b, ptr %pa, align 8
+ ret void
+ }
+
+ define void @vstore_nx8ptr(ptr %pa, <vscale x 8 x ptr> %b) #0 {
+ store <vscale x 8 x ptr> %b, ptr %pa, align 32
+ ret void
+ }
+
+...
+---
+name: vstore_nx1i8
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $v8, $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 1 x s8>) = COPY $v8
+ G_STORE %1(<vscale x 1 x s8>), %0(p0) :: (store (<vscale x 1 x s8>) into %ir.pa)
+ PseudoRET
+
+...
+---
+name: vstore_nx2i8
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $v8, $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 2 x s8>) = COPY $v8
+ G_STORE %1(<vscale x 2 x s8>), %0(p0) :: (store (<vscale x 2 x s8>) into %ir.pa)
+ PseudoRET
+
+...
+---
+name: vstore_nx4i8
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $v8, $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 4 x s8>) = COPY $v8
+ G_STORE %1(<vscale x 4 x s8>), %0(p0) :: (store (<vscale x 4 x s8>) into %ir.pa)
+ PseudoRET
+
+...
+---
+name: vstore_nx8i8
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $v8, $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 8 x s8>) = COPY $v8
+ G_STORE %1(<vscale x 8 x s8>), %0(p0) :: (store (<vscale x 8 x s8>) into %ir.pa)
+ PseudoRET
+
+...
+---
+name: vstore_nx16i8
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10, $v8m2
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 16 x s8>) = COPY $v8m2
+ G_STORE %1(<vscale x 16 x s8>), %0(p0) :: (store (<vscale x 16 x s8>) into %ir.pa)
+ PseudoRET
+
+...
+---
+name: vstore_nx32i8
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10, $v8m4
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 32 x s8>) = COPY $v8m4
+ G_STORE %1(<vscale x 32 x s8>), %0(p0) :: (store (<vscale x 32 x s8>) into %ir.pa)
+ PseudoRET
+
+...
+---
+name: vstore_nx64i8
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10, $v8m8
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 64 x s8>) = COPY $v8m8
+ G_STORE %1(<vscale x 64 x s8>), %0(p0) :: (store (<vscale x 64 x s8>) into %ir.pa)
+ PseudoRET
+
+...
+---
+name: vstore_nx1i16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $v8, $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 1 x s16>) = COPY $v8
+ G_STORE %1(<vscale x 1 x s16>), %0(p0) :: (store (<vscale x 1 x s16>) into %ir.pa)
+ PseudoRET
+
+...
+---
+name: vstore_nx2i16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $v8, $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 2 x s16>) = COPY $v8
+ G_STORE %1(<vscale x 2 x s16>), %0(p0) :: (store (<vscale x 2 x s16>) into %ir.pa)
+ PseudoRET
+
+...
+---
+name: vstore_nx4i16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $v8, $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 4 x s16>) = COPY $v8
+ G_STORE %1(<vscale x 4 x s16>), %0(p0) :: (store (<vscale x 4 x s16>) into %ir.pa)
+ PseudoRET
+
+...
+---
+name: vstore_nx8i16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10, $v8m2
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 8 x s16>) = COPY $v8m2
+ G_STORE %1(<vscale x 8 x s16>), %0(p0) :: (store (<vscale x 8 x s16>) into %ir.pa)
+ PseudoRET
+
+...
+---
+name: vstore_nx16i16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10, $v8m4
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 16 x s16>) = COPY $v8m4
+ G_STORE %1(<vscale x 16 x s16>), %0(p0) :: (store (<vscale x 16 x s16>) into %ir.pa)
+ PseudoRET
+
+...
+---
+name: vstore_nx32i16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10, $v8m8
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 32 x s16>) = COPY $v8m8
+ G_STORE %1(<vscale x 32 x s16>), %0(p0) :: (store (<vscale x 32 x s16>) into %ir.pa)
+ PseudoRET
+
+...
+---
+name: vstore_nx1i32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $v8, $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 1 x s32>) = COPY $v8
+ G_STORE %1(<vscale x 1 x s32>), %0(p0) :: (store (<vscale x 1 x s32>) into %ir.pa)
+ PseudoRET
+
+...
+---
+name: vstore_nx2i32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $v8, $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 2 x s32>) = COPY $v8
+ G_STORE %1(<vscale x 2 x s32>), %0(p0) :: (store (<vscale x 2 x s32>) into %ir.pa)
+ PseudoRET
+
+...
+---
+name: vstore_nx4i32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10, $v8m2
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 4 x s32>) = COPY $v8m2
+ G_STORE %1(<vscale x 4 x s32>), %0(p0) :: (store (<vscale x 4 x s32>) into %ir.pa)
+ PseudoRET
+
+...
+---
+name: vstore_nx8i32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10, $v8m4
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 8 x s32>) = COPY $v8m4
+ G_STORE %1(<vscale x 8 x s32>), %0(p0) :: (store (<vscale x 8 x s32>) into %ir.pa)
+ PseudoRET
+
+...
+---
+name: vstore_nx16i32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10, $v8m8
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 16 x s32>) = COPY $v8m8
+ G_STORE %1(<vscale x 16 x s32>), %0(p0) :: (store (<vscale x 16 x s32>) into %ir.pa)
+ PseudoRET
+
+...
+---
+name: vstore_nx1i64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $v8, $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 1 x s64>) = COPY $v8
+ G_STORE %1(<vscale x 1 x s64>), %0(p0) :: (store (<vscale x 1 x s64>) into %ir.pa)
+ PseudoRET
+
+...
+---
+name: vstore_nx2i64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10, $v8m2
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 2 x s64>) = COPY $v8m2
+ G_STORE %1(<vscale x 2 x s64>), %0(p0) :: (store (<vscale x 2 x s64>) into %ir.pa)
+ PseudoRET
+
+...
+---
+name: vstore_nx4i64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10, $v8m4
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 4 x s64>) = COPY $v8m4
+ G_STORE %1(<vscale x 4 x s64>), %0(p0) :: (store (<vscale x 4 x s64>) into %ir.pa)
+ PseudoRET
+
+...
+---
+name: vstore_nx8i64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10, $v8m8
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 8 x s64>) = COPY $v8m8
+ G_STORE %1(<vscale x 8 x s64>), %0(p0) :: (store (<vscale x 8 x s64>) into %ir.pa)
+ PseudoRET
+
+...
+---
+name: vstore_nx16i8_align1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10, $v8m2
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 16 x s8>) = COPY $v8m2
+ G_STORE %1(<vscale x 16 x s8>), %0(p0) :: (store (<vscale x 16 x s8>) into %ir.pa, align 1)
+ PseudoRET
+
+...
+---
+name: vstore_nx16i8_align2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10, $v8m2
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 16 x s8>) = COPY $v8m2
+ G_STORE %1(<vscale x 16 x s8>), %0(p0) :: (store (<vscale x 16 x s8>) into %ir.pa, align 2)
+ PseudoRET
+
+...
+---
+name: vstore_nx16i8_align16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10, $v8m2
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 16 x s8>) = COPY $v8m2
+ G_STORE %1(<vscale x 16 x s8>), %0(p0) :: (store (<vscale x 16 x s8>) into %ir.pa)
+ PseudoRET
+
+...
+---
+name: vstore_nx16i8_align64
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10, $v8m2
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 16 x s8>) = COPY $v8m2
+ G_STORE %1(<vscale x 16 x s8>), %0(p0) :: (store (<vscale x 16 x s8>) into %ir.pa, align 64)
+ PseudoRET
+
+...
+---
+name: vstore_nx4i16_align1
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $v8, $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 4 x s16>) = COPY $v8
+ %2:vrb(<vscale x 8 x s8>) = G_BITCAST %1(<vscale x 4 x s16>)
+ G_STORE %2(<vscale x 8 x s8>), %0(p0) :: (store (<vscale x 8 x s8>) into %ir.pa, align 1)
+ PseudoRET
+
+...
+---
+name: vstore_nx4i16_align2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $v8, $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 4 x s16>) = COPY $v8
+ G_STORE %1(<vscale x 4 x s16>), %0(p0) :: (store (<vscale x 4 x s16>) into %ir.pa, align 2)
+ PseudoRET
+
+...
+---
+name: vstore_nx4i16_align4
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $v8, $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 4 x s16>) = COPY $v8
+ G_STORE %1(<vscale x 4 x s16>), %0(p0) :: (store (<vscale x 4 x s16>) into %ir.pa, align 4)
+ PseudoRET
+
+...
+---
+name: vstore_nx4i16_align8
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $v8, $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 4 x s16>) = COPY $v8
+ G_STORE %1(<vscale x 4 x s16>), %0(p0) :: (store (<vscale x 4 x s16>) into %ir.pa)
+ PseudoRET
+
+...
+---
+name: vstore_nx4i16_align16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $v8, $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 4 x s16>) = COPY $v8
+ G_STORE %1(<vscale x 4 x s16>), %0(p0) :: (store (<vscale x 4 x s16>) into %ir.pa, align 16)
+ PseudoRET
+
+...
+---
+name: vstore_nx2i32_align2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $v8, $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 2 x s32>) = COPY $v8
+ %2:vrb(<vscale x 8 x s8>) = G_BITCAST %1(<vscale x 2 x s32>)
+ G_STORE %2(<vscale x 8 x s8>), %0(p0) :: (store (<vscale x 8 x s8>) into %ir.pa, align 2)
+ PseudoRET
+
+...
+---
+name: vstore_nx2i32_align4
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $v8, $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 2 x s32>) = COPY $v8
+ G_STORE %1(<vscale x 2 x s32>), %0(p0) :: (store (<vscale x 2 x s32>) into %ir.pa, align 4)
+ PseudoRET
+
+...
+---
+name: vstore_nx2i32_align8
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $v8, $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 2 x s32>) = COPY $v8
+ G_STORE %1(<vscale x 2 x s32>), %0(p0) :: (store (<vscale x 2 x s32>) into %ir.pa)
+ PseudoRET
+
+...
+---
+name: vstore_nx2i32_align16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $v8, $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 2 x s32>) = COPY $v8
+ G_STORE %1(<vscale x 2 x s32>), %0(p0) :: (store (<vscale x 2 x s32>) into %ir.pa, align 16)
+ PseudoRET
+
+...
+---
+name: vstore_nx2i32_align256
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $v8, $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 2 x s32>) = COPY $v8
+ G_STORE %1(<vscale x 2 x s32>), %0(p0) :: (store (<vscale x 2 x s32>) into %ir.pa, align 256)
+ PseudoRET
+
+...
+---
+name: vstore_nx2i64_align4
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10, $v8m2
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 2 x s64>) = COPY $v8m2
+ %2:vrb(<vscale x 16 x s8>) = G_BITCAST %1(<vscale x 2 x s64>)
+ G_STORE %2(<vscale x 16 x s8>), %0(p0) :: (store (<vscale x 16 x s8>) into %ir.pa, align 4)
+ PseudoRET
+
+...
+---
+name: vstore_nx2i64_align8
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10, $v8m2
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 2 x s64>) = COPY $v8m2
+ G_STORE %1(<vscale x 2 x s64>), %0(p0) :: (store (<vscale x 2 x s64>) into %ir.pa, align 8)
+ PseudoRET
+
+...
+---
+name: vstore_nx2i64_align16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10, $v8m2
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 2 x s64>) = COPY $v8m2
+ G_STORE %1(<vscale x 2 x s64>), %0(p0) :: (store (<vscale x 2 x s64>) into %ir.pa)
+ PseudoRET
+
+...
+---
+name: vstore_nx2i64_align32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10, $v8m2
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 2 x s64>) = COPY $v8m2
+ G_STORE %1(<vscale x 2 x s64>), %0(p0) :: (store (<vscale x 2 x s64>) into %ir.pa, align 32)
+ PseudoRET
+
+...
+---
+name: vstore_nx1ptr
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $v8, $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 1 x p0>) = COPY $v8
+ G_STORE %1(<vscale x 1 x p0>), %0(p0) :: (store (<vscale x 1 x p0>) into %ir.pa)
+ PseudoRET
+
+...
+---
+name: vstore_nx2ptr
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $v8, $x10
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 2 x p0>) = COPY $v8
+ G_STORE %1(<vscale x 2 x p0>), %0(p0) :: (store (<vscale x 2 x p0>) into %ir.pa)
+ PseudoRET
+
+...
+---
+name: vstore_nx8ptr
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x10, $v8m4
+
+ %0:gprb(p0) = COPY $x10
+ %1:vrb(<vscale x 8 x p0>) = COPY $v8m4
+ G_STORE %1(<vscale x 8 x p0>), %0(p0) :: (store (<vscale x 8 x p0>) into %ir.pa)
+ PseudoRET
+
+...
>From 907dbb3d9c8dc28590abdf1ff9a808ea64789fae Mon Sep 17 00:00:00 2001
From: Jiahan Xie <jx353 at cornell.edu>
Date: Mon, 23 Sep 2024 16:48:48 -0400
Subject: [PATCH 3/5] pre instr select lower to force load/store of pointers to
xlen integers
---
.../RISCV/GISel/RISCVInstructionSelector.cpp | 20 +++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 16b0e7e0a56072..1b55d03947d31b 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -786,6 +786,26 @@ void RISCVInstructionSelector::preISelLower(MachineInstr &MI,
replacePtrWithInt(MI.getOperand(1), MIB, MRI);
MI.setDesc(TII.get(TargetOpcode::G_AND));
MRI.setType(DstReg, sXLen);
+ break;
+ }
+ case TargetOpcode::G_LOAD: {
+ Register DstReg = MI.getOperand(0).getReg();
+ const LLT DstTy = MRI.getType(DstReg);
+ if (!(DstTy.isVector() && DstTy.getElementType().isPointer()))
+ break;
+ const LLT sXLen = LLT::scalar(STI.getXLen());
+ MRI.setType(DstReg, LLT::scalable_vector(DstTy.getElementCount().getKnownMinValue(), sXLen));
+ break;
+ }
+ case TargetOpcode::G_STORE: {
+ MachineOperand &SrcOp = MI.getOperand(0);
+ const LLT SrcTy = MRI.getType(SrcOp.getReg());
+ if (!(SrcTy.isVector() && SrcTy.getElementType().isPointer()))
+ break;
+ const LLT sXLen = LLT::scalar(STI.getXLen());
+ auto Copy = MIB.buildCopy(LLT::scalable_vector(SrcTy.getElementCount().getKnownMinValue(), sXLen), SrcOp);
+ Register NewSrc = Copy.getReg(0);
+ SrcOp.setReg(NewSrc);
}
}
}
>From 96e23b403c153285023c5f120438bd5489d0ba23 Mon Sep 17 00:00:00 2001
From: Jiahan Xie <jx353 at cornell.edu>
Date: Tue, 24 Sep 2024 08:20:06 -0400
Subject: [PATCH 4/5] update tests to remove llvm ir and update test checks
---
.../instruction-select/rvv/load.mir | 1208 ++++++++++++-----
.../instruction-select/rvv/store.mir | 1121 ++++++++++-----
2 files changed, 1634 insertions(+), 695 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/load.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/load.mir
index 55b210879e66ee..da728c62350107 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/load.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/load.mir
@@ -1,238 +1,36 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV32I %s
# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV64I %s
---- |
-
- define <vscale x 1 x i8> @vload_nx1i8(ptr %pa) #0 {
- %va = load <vscale x 1 x i8>, ptr %pa, align 1
- ret <vscale x 1 x i8> %va
- }
-
- define <vscale x 2 x i8> @vload_nx2i8(ptr %pa) #0 {
- %va = load <vscale x 2 x i8>, ptr %pa, align 2
- ret <vscale x 2 x i8> %va
- }
-
- define <vscale x 4 x i8> @vload_nx4i8(ptr %pa) #0 {
- %va = load <vscale x 4 x i8>, ptr %pa, align 4
- ret <vscale x 4 x i8> %va
- }
-
- define <vscale x 8 x i8> @vload_nx8i8(ptr %pa) #0 {
- %va = load <vscale x 8 x i8>, ptr %pa, align 8
- ret <vscale x 8 x i8> %va
- }
-
- define <vscale x 16 x i8> @vload_nx16i8(ptr %pa) #0 {
- %va = load <vscale x 16 x i8>, ptr %pa, align 16
- ret <vscale x 16 x i8> %va
- }
-
- define <vscale x 32 x i8> @vload_nx32i8(ptr %pa) #0 {
- %va = load <vscale x 32 x i8>, ptr %pa, align 32
- ret <vscale x 32 x i8> %va
- }
-
- define <vscale x 64 x i8> @vload_nx64i8(ptr %pa) #0 {
- %va = load <vscale x 64 x i8>, ptr %pa, align 64
- ret <vscale x 64 x i8> %va
- }
-
- define <vscale x 1 x i16> @vload_nx1i16(ptr %pa) #0 {
- %va = load <vscale x 1 x i16>, ptr %pa, align 2
- ret <vscale x 1 x i16> %va
- }
-
- define <vscale x 2 x i16> @vload_nx2i16(ptr %pa) #0 {
- %va = load <vscale x 2 x i16>, ptr %pa, align 4
- ret <vscale x 2 x i16> %va
- }
-
- define <vscale x 4 x i16> @vload_nx4i16(ptr %pa) #0 {
- %va = load <vscale x 4 x i16>, ptr %pa, align 8
- ret <vscale x 4 x i16> %va
- }
-
- define <vscale x 8 x i16> @vload_nx8i16(ptr %pa) #0 {
- %va = load <vscale x 8 x i16>, ptr %pa, align 16
- ret <vscale x 8 x i16> %va
- }
-
- define <vscale x 16 x i16> @vload_nx16i16(ptr %pa) #0 {
- %va = load <vscale x 16 x i16>, ptr %pa, align 32
- ret <vscale x 16 x i16> %va
- }
-
- define <vscale x 32 x i16> @vload_nx32i16(ptr %pa) #0 {
- %va = load <vscale x 32 x i16>, ptr %pa, align 64
- ret <vscale x 32 x i16> %va
- }
-
- define <vscale x 1 x i32> @vload_nx1i32(ptr %pa) #0 {
- %va = load <vscale x 1 x i32>, ptr %pa, align 4
- ret <vscale x 1 x i32> %va
- }
-
- define <vscale x 2 x i32> @vload_nx2i32(ptr %pa) #0 {
- %va = load <vscale x 2 x i32>, ptr %pa, align 8
- ret <vscale x 2 x i32> %va
- }
-
- define <vscale x 4 x i32> @vload_nx4i32(ptr %pa) #0 {
- %va = load <vscale x 4 x i32>, ptr %pa, align 16
- ret <vscale x 4 x i32> %va
- }
-
- define <vscale x 8 x i32> @vload_nx8i32(ptr %pa) #0 {
- %va = load <vscale x 8 x i32>, ptr %pa, align 32
- ret <vscale x 8 x i32> %va
- }
-
- define <vscale x 16 x i32> @vload_nx16i32(ptr %pa) #0 {
- %va = load <vscale x 16 x i32>, ptr %pa, align 64
- ret <vscale x 16 x i32> %va
- }
-
- define <vscale x 1 x i64> @vload_nx1i64(ptr %pa) #0 {
- %va = load <vscale x 1 x i64>, ptr %pa, align 8
- ret <vscale x 1 x i64> %va
- }
-
- define <vscale x 2 x i64> @vload_nx2i64(ptr %pa) #0 {
- %va = load <vscale x 2 x i64>, ptr %pa, align 16
- ret <vscale x 2 x i64> %va
- }
-
- define <vscale x 4 x i64> @vload_nx4i64(ptr %pa) #0 {
- %va = load <vscale x 4 x i64>, ptr %pa, align 32
- ret <vscale x 4 x i64> %va
- }
-
- define <vscale x 8 x i64> @vload_nx8i64(ptr %pa) #0 {
- %va = load <vscale x 8 x i64>, ptr %pa, align 64
- ret <vscale x 8 x i64> %va
- }
-
- define <vscale x 16 x i8> @vload_nx16i8_align1(ptr %pa) #0 {
- %va = load <vscale x 16 x i8>, ptr %pa, align 1
- ret <vscale x 16 x i8> %va
- }
-
- define <vscale x 16 x i8> @vload_nx16i8_align2(ptr %pa) #0 {
- %va = load <vscale x 16 x i8>, ptr %pa, align 2
- ret <vscale x 16 x i8> %va
- }
-
- define <vscale x 16 x i8> @vload_nx16i8_align16(ptr %pa) #0 {
- %va = load <vscale x 16 x i8>, ptr %pa, align 16
- ret <vscale x 16 x i8> %va
- }
-
- define <vscale x 16 x i8> @vload_nx16i8_align64(ptr %pa) #0 {
- %va = load <vscale x 16 x i8>, ptr %pa, align 64
- ret <vscale x 16 x i8> %va
- }
-
- define <vscale x 4 x i16> @vload_nx4i16_align1(ptr %pa) #0 {
- %va = load <vscale x 4 x i16>, ptr %pa, align 1
- ret <vscale x 4 x i16> %va
- }
-
- define <vscale x 4 x i16> @vload_nx4i16_align2(ptr %pa) #0 {
- %va = load <vscale x 4 x i16>, ptr %pa, align 2
- ret <vscale x 4 x i16> %va
- }
-
- define <vscale x 4 x i16> @vload_nx4i16_align4(ptr %pa) #0 {
- %va = load <vscale x 4 x i16>, ptr %pa, align 4
- ret <vscale x 4 x i16> %va
- }
-
- define <vscale x 4 x i16> @vload_nx4i16_align8(ptr %pa) #0 {
- %va = load <vscale x 4 x i16>, ptr %pa, align 8
- ret <vscale x 4 x i16> %va
- }
-
- define <vscale x 4 x i16> @vload_nx4i16_align16(ptr %pa) #0 {
- %va = load <vscale x 4 x i16>, ptr %pa, align 16
- ret <vscale x 4 x i16> %va
- }
-
- define <vscale x 2 x i32> @vload_nx2i32_align2(ptr %pa) #0 {
- %va = load <vscale x 2 x i32>, ptr %pa, align 2
- ret <vscale x 2 x i32> %va
- }
-
- define <vscale x 2 x i32> @vload_nx2i32_align4(ptr %pa) #0 {
- %va = load <vscale x 2 x i32>, ptr %pa, align 4
- ret <vscale x 2 x i32> %va
- }
-
- define <vscale x 2 x i32> @vload_nx2i32_align8(ptr %pa) #0 {
- %va = load <vscale x 2 x i32>, ptr %pa, align 8
- ret <vscale x 2 x i32> %va
- }
-
- define <vscale x 2 x i32> @vload_nx2i32_align16(ptr %pa) #0 {
- %va = load <vscale x 2 x i32>, ptr %pa, align 16
- ret <vscale x 2 x i32> %va
- }
-
- define <vscale x 2 x i32> @vload_nx2i32_align256(ptr %pa) #0 {
- %va = load <vscale x 2 x i32>, ptr %pa, align 256
- ret <vscale x 2 x i32> %va
- }
-
- define <vscale x 2 x i64> @vload_nx2i64_align4(ptr %pa) #0 {
- %va = load <vscale x 2 x i64>, ptr %pa, align 4
- ret <vscale x 2 x i64> %va
- }
-
- define <vscale x 2 x i64> @vload_nx2i64_align8(ptr %pa) #0 {
- %va = load <vscale x 2 x i64>, ptr %pa, align 8
- ret <vscale x 2 x i64> %va
- }
-
- define <vscale x 2 x i64> @vload_nx2i64_align16(ptr %pa) #0 {
- %va = load <vscale x 2 x i64>, ptr %pa, align 16
- ret <vscale x 2 x i64> %va
- }
-
- define <vscale x 2 x i64> @vload_nx2i64_align32(ptr %pa) #0 {
- %va = load <vscale x 2 x i64>, ptr %pa, align 32
- ret <vscale x 2 x i64> %va
- }
-
- define <vscale x 1 x ptr> @vload_nx1ptr(ptr %pa) #0 {
- %va = load <vscale x 1 x ptr>, ptr %pa, align 4
- ret <vscale x 1 x ptr> %va
- }
-
- define <vscale x 2 x ptr> @vload_nx2ptr(ptr %pa) #0 {
- %va = load <vscale x 2 x ptr>, ptr %pa, align 8
- ret <vscale x 2 x ptr> %va
- }
-
- define <vscale x 8 x ptr> @vload_nx8ptr(ptr %pa) #0 {
- %va = load <vscale x 8 x ptr>, ptr %pa, align 32
- ret <vscale x 8 x ptr> %va
- }
-
-...
---
name: vload_nx1i8
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10
-
+
+ ; RV32I-LABEL: name: vload_nx1i8
+ ; RV32I: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
+ ; RV32I-NEXT: [[PseudoVLE8_V_MF8_:%[0-9]+]]:vr = PseudoVLE8_V_MF8 [[DEF]], [[COPY]], -1, 3 /* e8 */, 3 /* ta, ma */ :: (load (<vscale x 1 x s8>))
+ ; RV32I-NEXT: $v8 = COPY [[PseudoVLE8_V_MF8_]]
+ ; RV32I-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64I-LABEL: name: vload_nx1i8
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
+ ; RV64I-NEXT: [[PseudoVLE8_V_MF8_:%[0-9]+]]:vr = PseudoVLE8_V_MF8 [[DEF]], [[COPY]], -1, 3 /* e8 */, 3 /* ta, ma */ :: (load (<vscale x 1 x s8>))
+ ; RV64I-NEXT: $v8 = COPY [[PseudoVLE8_V_MF8_]]
+ ; RV64I-NEXT: PseudoRET implicit $v8
%0:gprb(p0) = COPY $x10
- %1:vrb(<vscale x 1 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 1 x s8>) from %ir.pa)
+ %1:vrb(<vscale x 1 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 1 x s8>))
$v8 = COPY %1(<vscale x 1 x s8>)
PseudoRET implicit $v8
-
...
---
name: vload_nx2i8
@@ -240,11 +38,28 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10
-
+
+ ; RV32I-LABEL: name: vload_nx2i8
+ ; RV32I: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
+ ; RV32I-NEXT: [[PseudoVLE8_V_MF4_:%[0-9]+]]:vr = PseudoVLE8_V_MF4 [[DEF]], [[COPY]], -1, 3 /* e8 */, 3 /* ta, ma */ :: (load (<vscale x 2 x s8>))
+ ; RV32I-NEXT: $v8 = COPY [[PseudoVLE8_V_MF4_]]
+ ; RV32I-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64I-LABEL: name: vload_nx2i8
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
+ ; RV64I-NEXT: [[PseudoVLE8_V_MF4_:%[0-9]+]]:vr = PseudoVLE8_V_MF4 [[DEF]], [[COPY]], -1, 3 /* e8 */, 3 /* ta, ma */ :: (load (<vscale x 2 x s8>))
+ ; RV64I-NEXT: $v8 = COPY [[PseudoVLE8_V_MF4_]]
+ ; RV64I-NEXT: PseudoRET implicit $v8
%0:gprb(p0) = COPY $x10
- %1:vrb(<vscale x 2 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s8>) from %ir.pa)
+ %1:vrb(<vscale x 2 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s8>))
$v8 = COPY %1(<vscale x 2 x s8>)
PseudoRET implicit $v8
@@ -255,11 +70,28 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10
-
+
+ ; RV32I-LABEL: name: vload_nx4i8
+ ; RV32I: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
+ ; RV32I-NEXT: [[PseudoVLE8_V_MF2_:%[0-9]+]]:vr = PseudoVLE8_V_MF2 [[DEF]], [[COPY]], -1, 3 /* e8 */, 3 /* ta, ma */ :: (load (<vscale x 4 x s8>))
+ ; RV32I-NEXT: $v8 = COPY [[PseudoVLE8_V_MF2_]]
+ ; RV32I-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64I-LABEL: name: vload_nx4i8
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
+ ; RV64I-NEXT: [[PseudoVLE8_V_MF2_:%[0-9]+]]:vr = PseudoVLE8_V_MF2 [[DEF]], [[COPY]], -1, 3 /* e8 */, 3 /* ta, ma */ :: (load (<vscale x 4 x s8>))
+ ; RV64I-NEXT: $v8 = COPY [[PseudoVLE8_V_MF2_]]
+ ; RV64I-NEXT: PseudoRET implicit $v8
%0:gprb(p0) = COPY $x10
- %1:vrb(<vscale x 4 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 4 x s8>) from %ir.pa)
+ %1:vrb(<vscale x 4 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 4 x s8>))
$v8 = COPY %1(<vscale x 4 x s8>)
PseudoRET implicit $v8
@@ -270,11 +102,28 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10
-
+
+ ; RV32I-LABEL: name: vload_nx8i8
+ ; RV32I: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
+ ; RV32I-NEXT: [[PseudoVLE8_V_M1_:%[0-9]+]]:vr = PseudoVLE8_V_M1 [[DEF]], [[COPY]], -1, 3 /* e8 */, 3 /* ta, ma */ :: (load (<vscale x 8 x s8>))
+ ; RV32I-NEXT: $v8 = COPY [[PseudoVLE8_V_M1_]]
+ ; RV32I-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64I-LABEL: name: vload_nx8i8
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
+ ; RV64I-NEXT: [[PseudoVLE8_V_M1_:%[0-9]+]]:vr = PseudoVLE8_V_M1 [[DEF]], [[COPY]], -1, 3 /* e8 */, 3 /* ta, ma */ :: (load (<vscale x 8 x s8>))
+ ; RV64I-NEXT: $v8 = COPY [[PseudoVLE8_V_M1_]]
+ ; RV64I-NEXT: PseudoRET implicit $v8
%0:gprb(p0) = COPY $x10
- %1:vrb(<vscale x 8 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 8 x s8>) from %ir.pa)
+ %1:vrb(<vscale x 8 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 8 x s8>))
$v8 = COPY %1(<vscale x 8 x s8>)
PseudoRET implicit $v8
@@ -285,11 +134,28 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10
-
+
+ ; RV32I-LABEL: name: vload_nx16i8
+ ; RV32I: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF
+ ; RV32I-NEXT: [[PseudoVLE8_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE8_V_M2 [[DEF]], [[COPY]], -1, 3 /* e8 */, 3 /* ta, ma */ :: (load (<vscale x 16 x s8>))
+ ; RV32I-NEXT: $v8m2 = COPY [[PseudoVLE8_V_M2_]]
+ ; RV32I-NEXT: PseudoRET implicit $v8m2
+ ;
+ ; RV64I-LABEL: name: vload_nx16i8
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF
+ ; RV64I-NEXT: [[PseudoVLE8_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE8_V_M2 [[DEF]], [[COPY]], -1, 3 /* e8 */, 3 /* ta, ma */ :: (load (<vscale x 16 x s8>))
+ ; RV64I-NEXT: $v8m2 = COPY [[PseudoVLE8_V_M2_]]
+ ; RV64I-NEXT: PseudoRET implicit $v8m2
%0:gprb(p0) = COPY $x10
- %1:vrb(<vscale x 16 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 16 x s8>) from %ir.pa)
+ %1:vrb(<vscale x 16 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 16 x s8>))
$v8m2 = COPY %1(<vscale x 16 x s8>)
PseudoRET implicit $v8m2
@@ -300,11 +166,28 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10
-
+
+ ; RV32I-LABEL: name: vload_nx32i8
+ ; RV32I: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
+ ; RV32I-NEXT: [[PseudoVLE8_V_M4_:%[0-9]+]]:vrm4 = PseudoVLE8_V_M4 [[DEF]], [[COPY]], -1, 3 /* e8 */, 3 /* ta, ma */ :: (load (<vscale x 32 x s8>))
+ ; RV32I-NEXT: $v8m4 = COPY [[PseudoVLE8_V_M4_]]
+ ; RV32I-NEXT: PseudoRET implicit $v8m4
+ ;
+ ; RV64I-LABEL: name: vload_nx32i8
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
+ ; RV64I-NEXT: [[PseudoVLE8_V_M4_:%[0-9]+]]:vrm4 = PseudoVLE8_V_M4 [[DEF]], [[COPY]], -1, 3 /* e8 */, 3 /* ta, ma */ :: (load (<vscale x 32 x s8>))
+ ; RV64I-NEXT: $v8m4 = COPY [[PseudoVLE8_V_M4_]]
+ ; RV64I-NEXT: PseudoRET implicit $v8m4
%0:gprb(p0) = COPY $x10
- %1:vrb(<vscale x 32 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 32 x s8>) from %ir.pa)
+ %1:vrb(<vscale x 32 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 32 x s8>))
$v8m4 = COPY %1(<vscale x 32 x s8>)
PseudoRET implicit $v8m4
@@ -315,11 +198,28 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10
-
+
+ ; RV32I-LABEL: name: vload_nx64i8
+ ; RV32I: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
+ ; RV32I-NEXT: [[PseudoVLE8_V_M8_:%[0-9]+]]:vrm8 = PseudoVLE8_V_M8 [[DEF]], [[COPY]], -1, 3 /* e8 */, 3 /* ta, ma */ :: (load (<vscale x 64 x s8>))
+ ; RV32I-NEXT: $v8m8 = COPY [[PseudoVLE8_V_M8_]]
+ ; RV32I-NEXT: PseudoRET implicit $v8m8
+ ;
+ ; RV64I-LABEL: name: vload_nx64i8
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
+ ; RV64I-NEXT: [[PseudoVLE8_V_M8_:%[0-9]+]]:vrm8 = PseudoVLE8_V_M8 [[DEF]], [[COPY]], -1, 3 /* e8 */, 3 /* ta, ma */ :: (load (<vscale x 64 x s8>))
+ ; RV64I-NEXT: $v8m8 = COPY [[PseudoVLE8_V_M8_]]
+ ; RV64I-NEXT: PseudoRET implicit $v8m8
%0:gprb(p0) = COPY $x10
- %1:vrb(<vscale x 64 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 64 x s8>) from %ir.pa)
+ %1:vrb(<vscale x 64 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 64 x s8>))
$v8m8 = COPY %1(<vscale x 64 x s8>)
PseudoRET implicit $v8m8
@@ -330,11 +230,28 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10
-
+
+ ; RV32I-LABEL: name: vload_nx1i16
+ ; RV32I: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
+ ; RV32I-NEXT: [[PseudoVLE16_V_MF4_:%[0-9]+]]:vr = PseudoVLE16_V_MF4 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ :: (load (<vscale x 1 x s16>))
+ ; RV32I-NEXT: $v8 = COPY [[PseudoVLE16_V_MF4_]]
+ ; RV32I-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64I-LABEL: name: vload_nx1i16
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
+ ; RV64I-NEXT: [[PseudoVLE16_V_MF4_:%[0-9]+]]:vr = PseudoVLE16_V_MF4 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ :: (load (<vscale x 1 x s16>))
+ ; RV64I-NEXT: $v8 = COPY [[PseudoVLE16_V_MF4_]]
+ ; RV64I-NEXT: PseudoRET implicit $v8
%0:gprb(p0) = COPY $x10
- %1:vrb(<vscale x 1 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 1 x s16>) from %ir.pa)
+ %1:vrb(<vscale x 1 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 1 x s16>))
$v8 = COPY %1(<vscale x 1 x s16>)
PseudoRET implicit $v8
@@ -345,11 +262,28 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10
-
+
+ ; RV32I-LABEL: name: vload_nx2i16
+ ; RV32I: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
+ ; RV32I-NEXT: [[PseudoVLE16_V_MF2_:%[0-9]+]]:vr = PseudoVLE16_V_MF2 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ :: (load (<vscale x 2 x s16>))
+ ; RV32I-NEXT: $v8 = COPY [[PseudoVLE16_V_MF2_]]
+ ; RV32I-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64I-LABEL: name: vload_nx2i16
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
+ ; RV64I-NEXT: [[PseudoVLE16_V_MF2_:%[0-9]+]]:vr = PseudoVLE16_V_MF2 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ :: (load (<vscale x 2 x s16>))
+ ; RV64I-NEXT: $v8 = COPY [[PseudoVLE16_V_MF2_]]
+ ; RV64I-NEXT: PseudoRET implicit $v8
%0:gprb(p0) = COPY $x10
- %1:vrb(<vscale x 2 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s16>) from %ir.pa)
+ %1:vrb(<vscale x 2 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s16>))
$v8 = COPY %1(<vscale x 2 x s16>)
PseudoRET implicit $v8
@@ -360,11 +294,28 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10
-
+
+ ; RV32I-LABEL: name: vload_nx4i16
+ ; RV32I: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
+ ; RV32I-NEXT: [[PseudoVLE16_V_M1_:%[0-9]+]]:vr = PseudoVLE16_V_M1 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ :: (load (<vscale x 4 x s16>))
+ ; RV32I-NEXT: $v8 = COPY [[PseudoVLE16_V_M1_]]
+ ; RV32I-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64I-LABEL: name: vload_nx4i16
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
+ ; RV64I-NEXT: [[PseudoVLE16_V_M1_:%[0-9]+]]:vr = PseudoVLE16_V_M1 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ :: (load (<vscale x 4 x s16>))
+ ; RV64I-NEXT: $v8 = COPY [[PseudoVLE16_V_M1_]]
+ ; RV64I-NEXT: PseudoRET implicit $v8
%0:gprb(p0) = COPY $x10
- %1:vrb(<vscale x 4 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 4 x s16>) from %ir.pa)
+ %1:vrb(<vscale x 4 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 4 x s16>))
$v8 = COPY %1(<vscale x 4 x s16>)
PseudoRET implicit $v8
@@ -375,11 +326,28 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10
-
+
+ ; RV32I-LABEL: name: vload_nx8i16
+ ; RV32I: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF
+ ; RV32I-NEXT: [[PseudoVLE16_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE16_V_M2 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ :: (load (<vscale x 8 x s16>))
+ ; RV32I-NEXT: $v8m2 = COPY [[PseudoVLE16_V_M2_]]
+ ; RV32I-NEXT: PseudoRET implicit $v8m2
+ ;
+ ; RV64I-LABEL: name: vload_nx8i16
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF
+ ; RV64I-NEXT: [[PseudoVLE16_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE16_V_M2 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ :: (load (<vscale x 8 x s16>))
+ ; RV64I-NEXT: $v8m2 = COPY [[PseudoVLE16_V_M2_]]
+ ; RV64I-NEXT: PseudoRET implicit $v8m2
%0:gprb(p0) = COPY $x10
- %1:vrb(<vscale x 8 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 8 x s16>) from %ir.pa)
+ %1:vrb(<vscale x 8 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 8 x s16>))
$v8m2 = COPY %1(<vscale x 8 x s16>)
PseudoRET implicit $v8m2
@@ -390,11 +358,28 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10
-
+
+ ; RV32I-LABEL: name: vload_nx16i16
+ ; RV32I: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
+ ; RV32I-NEXT: [[PseudoVLE16_V_M4_:%[0-9]+]]:vrm4 = PseudoVLE16_V_M4 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ :: (load (<vscale x 16 x s16>))
+ ; RV32I-NEXT: $v8m4 = COPY [[PseudoVLE16_V_M4_]]
+ ; RV32I-NEXT: PseudoRET implicit $v8m4
+ ;
+ ; RV64I-LABEL: name: vload_nx16i16
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
+ ; RV64I-NEXT: [[PseudoVLE16_V_M4_:%[0-9]+]]:vrm4 = PseudoVLE16_V_M4 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ :: (load (<vscale x 16 x s16>))
+ ; RV64I-NEXT: $v8m4 = COPY [[PseudoVLE16_V_M4_]]
+ ; RV64I-NEXT: PseudoRET implicit $v8m4
%0:gprb(p0) = COPY $x10
- %1:vrb(<vscale x 16 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 16 x s16>) from %ir.pa)
+ %1:vrb(<vscale x 16 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 16 x s16>))
$v8m4 = COPY %1(<vscale x 16 x s16>)
PseudoRET implicit $v8m4
@@ -405,11 +390,28 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10
-
+
+ ; RV32I-LABEL: name: vload_nx32i16
+ ; RV32I: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
+ ; RV32I-NEXT: [[PseudoVLE16_V_M8_:%[0-9]+]]:vrm8 = PseudoVLE16_V_M8 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ :: (load (<vscale x 32 x s16>))
+ ; RV32I-NEXT: $v8m8 = COPY [[PseudoVLE16_V_M8_]]
+ ; RV32I-NEXT: PseudoRET implicit $v8m8
+ ;
+ ; RV64I-LABEL: name: vload_nx32i16
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
+ ; RV64I-NEXT: [[PseudoVLE16_V_M8_:%[0-9]+]]:vrm8 = PseudoVLE16_V_M8 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ :: (load (<vscale x 32 x s16>))
+ ; RV64I-NEXT: $v8m8 = COPY [[PseudoVLE16_V_M8_]]
+ ; RV64I-NEXT: PseudoRET implicit $v8m8
%0:gprb(p0) = COPY $x10
- %1:vrb(<vscale x 32 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 32 x s16>) from %ir.pa)
+ %1:vrb(<vscale x 32 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 32 x s16>))
$v8m8 = COPY %1(<vscale x 32 x s16>)
PseudoRET implicit $v8m8
@@ -420,11 +422,28 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10
-
+
+ ; RV32I-LABEL: name: vload_nx1i32
+ ; RV32I: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
+ ; RV32I-NEXT: [[PseudoVLE32_V_MF2_:%[0-9]+]]:vr = PseudoVLE32_V_MF2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ :: (load (<vscale x 1 x s32>))
+ ; RV32I-NEXT: $v8 = COPY [[PseudoVLE32_V_MF2_]]
+ ; RV32I-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64I-LABEL: name: vload_nx1i32
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
+ ; RV64I-NEXT: [[PseudoVLE32_V_MF2_:%[0-9]+]]:vr = PseudoVLE32_V_MF2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ :: (load (<vscale x 1 x s32>))
+ ; RV64I-NEXT: $v8 = COPY [[PseudoVLE32_V_MF2_]]
+ ; RV64I-NEXT: PseudoRET implicit $v8
%0:gprb(p0) = COPY $x10
- %1:vrb(<vscale x 1 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 1 x s32>) from %ir.pa)
+ %1:vrb(<vscale x 1 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 1 x s32>))
$v8 = COPY %1(<vscale x 1 x s32>)
PseudoRET implicit $v8
@@ -435,11 +454,28 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10
-
+
+ ; RV32I-LABEL: name: vload_nx2i32
+ ; RV32I: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
+ ; RV32I-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ :: (load (<vscale x 2 x s32>))
+ ; RV32I-NEXT: $v8 = COPY [[PseudoVLE32_V_M1_]]
+ ; RV32I-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64I-LABEL: name: vload_nx2i32
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
+ ; RV64I-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ :: (load (<vscale x 2 x s32>))
+ ; RV64I-NEXT: $v8 = COPY [[PseudoVLE32_V_M1_]]
+ ; RV64I-NEXT: PseudoRET implicit $v8
%0:gprb(p0) = COPY $x10
- %1:vrb(<vscale x 2 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s32>) from %ir.pa)
+ %1:vrb(<vscale x 2 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s32>))
$v8 = COPY %1(<vscale x 2 x s32>)
PseudoRET implicit $v8
@@ -450,11 +486,28 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10
-
+
+ ; RV32I-LABEL: name: vload_nx4i32
+ ; RV32I: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF
+ ; RV32I-NEXT: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ :: (load (<vscale x 4 x s32>))
+ ; RV32I-NEXT: $v8m2 = COPY [[PseudoVLE32_V_M2_]]
+ ; RV32I-NEXT: PseudoRET implicit $v8m2
+ ;
+ ; RV64I-LABEL: name: vload_nx4i32
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF
+ ; RV64I-NEXT: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ :: (load (<vscale x 4 x s32>))
+ ; RV64I-NEXT: $v8m2 = COPY [[PseudoVLE32_V_M2_]]
+ ; RV64I-NEXT: PseudoRET implicit $v8m2
%0:gprb(p0) = COPY $x10
- %1:vrb(<vscale x 4 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 4 x s32>) from %ir.pa)
+ %1:vrb(<vscale x 4 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 4 x s32>))
$v8m2 = COPY %1(<vscale x 4 x s32>)
PseudoRET implicit $v8m2
@@ -465,11 +518,28 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10
-
+
+ ; RV32I-LABEL: name: vload_nx8i32
+ ; RV32I: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
+ ; RV32I-NEXT: [[PseudoVLE32_V_M4_:%[0-9]+]]:vrm4 = PseudoVLE32_V_M4 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ :: (load (<vscale x 8 x s32>))
+ ; RV32I-NEXT: $v8m4 = COPY [[PseudoVLE32_V_M4_]]
+ ; RV32I-NEXT: PseudoRET implicit $v8m4
+ ;
+ ; RV64I-LABEL: name: vload_nx8i32
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
+ ; RV64I-NEXT: [[PseudoVLE32_V_M4_:%[0-9]+]]:vrm4 = PseudoVLE32_V_M4 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ :: (load (<vscale x 8 x s32>))
+ ; RV64I-NEXT: $v8m4 = COPY [[PseudoVLE32_V_M4_]]
+ ; RV64I-NEXT: PseudoRET implicit $v8m4
%0:gprb(p0) = COPY $x10
- %1:vrb(<vscale x 8 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 8 x s32>) from %ir.pa)
+ %1:vrb(<vscale x 8 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 8 x s32>))
$v8m4 = COPY %1(<vscale x 8 x s32>)
PseudoRET implicit $v8m4
@@ -480,11 +550,28 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10
-
+
+ ; RV32I-LABEL: name: vload_nx16i32
+ ; RV32I: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
+ ; RV32I-NEXT: [[PseudoVLE32_V_M8_:%[0-9]+]]:vrm8 = PseudoVLE32_V_M8 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ :: (load (<vscale x 16 x s32>))
+ ; RV32I-NEXT: $v8m8 = COPY [[PseudoVLE32_V_M8_]]
+ ; RV32I-NEXT: PseudoRET implicit $v8m8
+ ;
+ ; RV64I-LABEL: name: vload_nx16i32
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
+ ; RV64I-NEXT: [[PseudoVLE32_V_M8_:%[0-9]+]]:vrm8 = PseudoVLE32_V_M8 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ :: (load (<vscale x 16 x s32>))
+ ; RV64I-NEXT: $v8m8 = COPY [[PseudoVLE32_V_M8_]]
+ ; RV64I-NEXT: PseudoRET implicit $v8m8
%0:gprb(p0) = COPY $x10
- %1:vrb(<vscale x 16 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 16 x s32>) from %ir.pa)
+ %1:vrb(<vscale x 16 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 16 x s32>))
$v8m8 = COPY %1(<vscale x 16 x s32>)
PseudoRET implicit $v8m8
@@ -495,11 +582,28 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10
-
+
+ ; RV32I-LABEL: name: vload_nx1i64
+ ; RV32I: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
+ ; RV32I-NEXT: [[PseudoVLE64_V_M1_:%[0-9]+]]:vr = PseudoVLE64_V_M1 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ :: (load (<vscale x 1 x s64>))
+ ; RV32I-NEXT: $v8 = COPY [[PseudoVLE64_V_M1_]]
+ ; RV32I-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64I-LABEL: name: vload_nx1i64
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
+ ; RV64I-NEXT: [[PseudoVLE64_V_M1_:%[0-9]+]]:vr = PseudoVLE64_V_M1 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ :: (load (<vscale x 1 x s64>))
+ ; RV64I-NEXT: $v8 = COPY [[PseudoVLE64_V_M1_]]
+ ; RV64I-NEXT: PseudoRET implicit $v8
%0:gprb(p0) = COPY $x10
- %1:vrb(<vscale x 1 x s64>) = G_LOAD %0(p0) :: (load (<vscale x 1 x s64>) from %ir.pa)
+ %1:vrb(<vscale x 1 x s64>) = G_LOAD %0(p0) :: (load (<vscale x 1 x s64>))
$v8 = COPY %1(<vscale x 1 x s64>)
PseudoRET implicit $v8
@@ -510,11 +614,28 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10
-
+
+ ; RV32I-LABEL: name: vload_nx2i64
+ ; RV32I: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF
+ ; RV32I-NEXT: [[PseudoVLE64_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE64_V_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ :: (load (<vscale x 2 x s64>))
+ ; RV32I-NEXT: $v8m2 = COPY [[PseudoVLE64_V_M2_]]
+ ; RV32I-NEXT: PseudoRET implicit $v8m2
+ ;
+ ; RV64I-LABEL: name: vload_nx2i64
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF
+ ; RV64I-NEXT: [[PseudoVLE64_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE64_V_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ :: (load (<vscale x 2 x s64>))
+ ; RV64I-NEXT: $v8m2 = COPY [[PseudoVLE64_V_M2_]]
+ ; RV64I-NEXT: PseudoRET implicit $v8m2
%0:gprb(p0) = COPY $x10
- %1:vrb(<vscale x 2 x s64>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s64>) from %ir.pa)
+ %1:vrb(<vscale x 2 x s64>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s64>))
$v8m2 = COPY %1(<vscale x 2 x s64>)
PseudoRET implicit $v8m2
@@ -525,11 +646,28 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10
-
+
+ ; RV32I-LABEL: name: vload_nx4i64
+ ; RV32I: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
+ ; RV32I-NEXT: [[PseudoVLE64_V_M4_:%[0-9]+]]:vrm4 = PseudoVLE64_V_M4 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ :: (load (<vscale x 4 x s64>))
+ ; RV32I-NEXT: $v8m4 = COPY [[PseudoVLE64_V_M4_]]
+ ; RV32I-NEXT: PseudoRET implicit $v8m4
+ ;
+ ; RV64I-LABEL: name: vload_nx4i64
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
+ ; RV64I-NEXT: [[PseudoVLE64_V_M4_:%[0-9]+]]:vrm4 = PseudoVLE64_V_M4 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ :: (load (<vscale x 4 x s64>))
+ ; RV64I-NEXT: $v8m4 = COPY [[PseudoVLE64_V_M4_]]
+ ; RV64I-NEXT: PseudoRET implicit $v8m4
%0:gprb(p0) = COPY $x10
- %1:vrb(<vscale x 4 x s64>) = G_LOAD %0(p0) :: (load (<vscale x 4 x s64>) from %ir.pa)
+ %1:vrb(<vscale x 4 x s64>) = G_LOAD %0(p0) :: (load (<vscale x 4 x s64>))
$v8m4 = COPY %1(<vscale x 4 x s64>)
PseudoRET implicit $v8m4
@@ -540,11 +678,28 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10
-
+
+ ; RV32I-LABEL: name: vload_nx8i64
+ ; RV32I: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
+ ; RV32I-NEXT: [[PseudoVLE64_V_M8_:%[0-9]+]]:vrm8 = PseudoVLE64_V_M8 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ :: (load (<vscale x 8 x s64>))
+ ; RV32I-NEXT: $v8m8 = COPY [[PseudoVLE64_V_M8_]]
+ ; RV32I-NEXT: PseudoRET implicit $v8m8
+ ;
+ ; RV64I-LABEL: name: vload_nx8i64
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
+ ; RV64I-NEXT: [[PseudoVLE64_V_M8_:%[0-9]+]]:vrm8 = PseudoVLE64_V_M8 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ :: (load (<vscale x 8 x s64>))
+ ; RV64I-NEXT: $v8m8 = COPY [[PseudoVLE64_V_M8_]]
+ ; RV64I-NEXT: PseudoRET implicit $v8m8
%0:gprb(p0) = COPY $x10
- %1:vrb(<vscale x 8 x s64>) = G_LOAD %0(p0) :: (load (<vscale x 8 x s64>) from %ir.pa)
+ %1:vrb(<vscale x 8 x s64>) = G_LOAD %0(p0) :: (load (<vscale x 8 x s64>))
$v8m8 = COPY %1(<vscale x 8 x s64>)
PseudoRET implicit $v8m8
@@ -555,11 +710,28 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10
-
+
+ ; RV32I-LABEL: name: vload_nx16i8_align1
+ ; RV32I: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF
+ ; RV32I-NEXT: [[PseudoVLE8_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE8_V_M2 [[DEF]], [[COPY]], -1, 3 /* e8 */, 3 /* ta, ma */ :: (load (<vscale x 16 x s8>), align 1)
+ ; RV32I-NEXT: $v8m2 = COPY [[PseudoVLE8_V_M2_]]
+ ; RV32I-NEXT: PseudoRET implicit $v8m2
+ ;
+ ; RV64I-LABEL: name: vload_nx16i8_align1
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF
+ ; RV64I-NEXT: [[PseudoVLE8_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE8_V_M2 [[DEF]], [[COPY]], -1, 3 /* e8 */, 3 /* ta, ma */ :: (load (<vscale x 16 x s8>), align 1)
+ ; RV64I-NEXT: $v8m2 = COPY [[PseudoVLE8_V_M2_]]
+ ; RV64I-NEXT: PseudoRET implicit $v8m2
%0:gprb(p0) = COPY $x10
- %1:vrb(<vscale x 16 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 16 x s8>) from %ir.pa, align 1)
+ %1:vrb(<vscale x 16 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 16 x s8>), align 1)
$v8m2 = COPY %1(<vscale x 16 x s8>)
PseudoRET implicit $v8m2
@@ -570,11 +742,28 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10
-
+
+ ; RV32I-LABEL: name: vload_nx16i8_align2
+ ; RV32I: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF
+ ; RV32I-NEXT: [[PseudoVLE8_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE8_V_M2 [[DEF]], [[COPY]], -1, 3 /* e8 */, 3 /* ta, ma */ :: (load (<vscale x 16 x s8>), align 2)
+ ; RV32I-NEXT: $v8m2 = COPY [[PseudoVLE8_V_M2_]]
+ ; RV32I-NEXT: PseudoRET implicit $v8m2
+ ;
+ ; RV64I-LABEL: name: vload_nx16i8_align2
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF
+ ; RV64I-NEXT: [[PseudoVLE8_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE8_V_M2 [[DEF]], [[COPY]], -1, 3 /* e8 */, 3 /* ta, ma */ :: (load (<vscale x 16 x s8>), align 2)
+ ; RV64I-NEXT: $v8m2 = COPY [[PseudoVLE8_V_M2_]]
+ ; RV64I-NEXT: PseudoRET implicit $v8m2
%0:gprb(p0) = COPY $x10
- %1:vrb(<vscale x 16 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 16 x s8>) from %ir.pa, align 2)
+ %1:vrb(<vscale x 16 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 16 x s8>), align 2)
$v8m2 = COPY %1(<vscale x 16 x s8>)
PseudoRET implicit $v8m2
@@ -585,11 +774,28 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10
-
+
+ ; RV32I-LABEL: name: vload_nx16i8_align16
+ ; RV32I: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF
+ ; RV32I-NEXT: [[PseudoVLE8_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE8_V_M2 [[DEF]], [[COPY]], -1, 3 /* e8 */, 3 /* ta, ma */ :: (load (<vscale x 16 x s8>))
+ ; RV32I-NEXT: $v8m2 = COPY [[PseudoVLE8_V_M2_]]
+ ; RV32I-NEXT: PseudoRET implicit $v8m2
+ ;
+ ; RV64I-LABEL: name: vload_nx16i8_align16
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF
+ ; RV64I-NEXT: [[PseudoVLE8_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE8_V_M2 [[DEF]], [[COPY]], -1, 3 /* e8 */, 3 /* ta, ma */ :: (load (<vscale x 16 x s8>))
+ ; RV64I-NEXT: $v8m2 = COPY [[PseudoVLE8_V_M2_]]
+ ; RV64I-NEXT: PseudoRET implicit $v8m2
%0:gprb(p0) = COPY $x10
- %1:vrb(<vscale x 16 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 16 x s8>) from %ir.pa)
+ %1:vrb(<vscale x 16 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 16 x s8>))
$v8m2 = COPY %1(<vscale x 16 x s8>)
PseudoRET implicit $v8m2
@@ -600,11 +806,28 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10
-
+
+ ; RV32I-LABEL: name: vload_nx16i8_align64
+ ; RV32I: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF
+ ; RV32I-NEXT: [[PseudoVLE8_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE8_V_M2 [[DEF]], [[COPY]], -1, 3 /* e8 */, 3 /* ta, ma */ :: (load (<vscale x 16 x s8>), align 64)
+ ; RV32I-NEXT: $v8m2 = COPY [[PseudoVLE8_V_M2_]]
+ ; RV32I-NEXT: PseudoRET implicit $v8m2
+ ;
+ ; RV64I-LABEL: name: vload_nx16i8_align64
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF
+ ; RV64I-NEXT: [[PseudoVLE8_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE8_V_M2 [[DEF]], [[COPY]], -1, 3 /* e8 */, 3 /* ta, ma */ :: (load (<vscale x 16 x s8>), align 64)
+ ; RV64I-NEXT: $v8m2 = COPY [[PseudoVLE8_V_M2_]]
+ ; RV64I-NEXT: PseudoRET implicit $v8m2
%0:gprb(p0) = COPY $x10
- %1:vrb(<vscale x 16 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 16 x s8>) from %ir.pa, align 64)
+ %1:vrb(<vscale x 16 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 16 x s8>), align 64)
$v8m2 = COPY %1(<vscale x 16 x s8>)
PseudoRET implicit $v8m2
@@ -615,11 +838,28 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10
-
+
+ ; RV32I-LABEL: name: vload_nx4i16_align1
+ ; RV32I: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
+ ; RV32I-NEXT: [[PseudoVLE8_V_M1_:%[0-9]+]]:vr = PseudoVLE8_V_M1 [[DEF]], [[COPY]], -1, 3 /* e8 */, 3 /* ta, ma */ :: (load (<vscale x 8 x s8>), align 1)
+ ; RV32I-NEXT: $v8 = COPY [[PseudoVLE8_V_M1_]]
+ ; RV32I-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64I-LABEL: name: vload_nx4i16_align1
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
+ ; RV64I-NEXT: [[PseudoVLE8_V_M1_:%[0-9]+]]:vr = PseudoVLE8_V_M1 [[DEF]], [[COPY]], -1, 3 /* e8 */, 3 /* ta, ma */ :: (load (<vscale x 8 x s8>), align 1)
+ ; RV64I-NEXT: $v8 = COPY [[PseudoVLE8_V_M1_]]
+ ; RV64I-NEXT: PseudoRET implicit $v8
%0:gprb(p0) = COPY $x10
- %2:vrb(<vscale x 8 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 8 x s8>) from %ir.pa, align 1)
+ %2:vrb(<vscale x 8 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 8 x s8>), align 1)
%1:vrb(<vscale x 4 x s16>) = G_BITCAST %2(<vscale x 8 x s8>)
$v8 = COPY %1(<vscale x 4 x s16>)
PseudoRET implicit $v8
@@ -631,11 +871,28 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10
-
+
+ ; RV32I-LABEL: name: vload_nx4i16_align2
+ ; RV32I: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
+ ; RV32I-NEXT: [[PseudoVLE16_V_M1_:%[0-9]+]]:vr = PseudoVLE16_V_M1 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ :: (load (<vscale x 4 x s16>), align 2)
+ ; RV32I-NEXT: $v8 = COPY [[PseudoVLE16_V_M1_]]
+ ; RV32I-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64I-LABEL: name: vload_nx4i16_align2
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
+ ; RV64I-NEXT: [[PseudoVLE16_V_M1_:%[0-9]+]]:vr = PseudoVLE16_V_M1 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ :: (load (<vscale x 4 x s16>), align 2)
+ ; RV64I-NEXT: $v8 = COPY [[PseudoVLE16_V_M1_]]
+ ; RV64I-NEXT: PseudoRET implicit $v8
%0:gprb(p0) = COPY $x10
- %1:vrb(<vscale x 4 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 4 x s16>) from %ir.pa, align 2)
+ %1:vrb(<vscale x 4 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 4 x s16>), align 2)
$v8 = COPY %1(<vscale x 4 x s16>)
PseudoRET implicit $v8
@@ -646,11 +903,28 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10
-
+
+ ; RV32I-LABEL: name: vload_nx4i16_align4
+ ; RV32I: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
+ ; RV32I-NEXT: [[PseudoVLE16_V_M1_:%[0-9]+]]:vr = PseudoVLE16_V_M1 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ :: (load (<vscale x 4 x s16>), align 4)
+ ; RV32I-NEXT: $v8 = COPY [[PseudoVLE16_V_M1_]]
+ ; RV32I-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64I-LABEL: name: vload_nx4i16_align4
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
+ ; RV64I-NEXT: [[PseudoVLE16_V_M1_:%[0-9]+]]:vr = PseudoVLE16_V_M1 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ :: (load (<vscale x 4 x s16>), align 4)
+ ; RV64I-NEXT: $v8 = COPY [[PseudoVLE16_V_M1_]]
+ ; RV64I-NEXT: PseudoRET implicit $v8
%0:gprb(p0) = COPY $x10
- %1:vrb(<vscale x 4 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 4 x s16>) from %ir.pa, align 4)
+ %1:vrb(<vscale x 4 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 4 x s16>), align 4)
$v8 = COPY %1(<vscale x 4 x s16>)
PseudoRET implicit $v8
@@ -661,11 +935,28 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10
-
+
+ ; RV32I-LABEL: name: vload_nx4i16_align8
+ ; RV32I: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
+ ; RV32I-NEXT: [[PseudoVLE16_V_M1_:%[0-9]+]]:vr = PseudoVLE16_V_M1 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ :: (load (<vscale x 4 x s16>))
+ ; RV32I-NEXT: $v8 = COPY [[PseudoVLE16_V_M1_]]
+ ; RV32I-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64I-LABEL: name: vload_nx4i16_align8
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
+ ; RV64I-NEXT: [[PseudoVLE16_V_M1_:%[0-9]+]]:vr = PseudoVLE16_V_M1 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ :: (load (<vscale x 4 x s16>))
+ ; RV64I-NEXT: $v8 = COPY [[PseudoVLE16_V_M1_]]
+ ; RV64I-NEXT: PseudoRET implicit $v8
%0:gprb(p0) = COPY $x10
- %1:vrb(<vscale x 4 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 4 x s16>) from %ir.pa)
+ %1:vrb(<vscale x 4 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 4 x s16>))
$v8 = COPY %1(<vscale x 4 x s16>)
PseudoRET implicit $v8
@@ -676,11 +967,28 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10
-
+
+ ; RV32I-LABEL: name: vload_nx4i16_align16
+ ; RV32I: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
+ ; RV32I-NEXT: [[PseudoVLE16_V_M1_:%[0-9]+]]:vr = PseudoVLE16_V_M1 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ :: (load (<vscale x 4 x s16>), align 16)
+ ; RV32I-NEXT: $v8 = COPY [[PseudoVLE16_V_M1_]]
+ ; RV32I-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64I-LABEL: name: vload_nx4i16_align16
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
+ ; RV64I-NEXT: [[PseudoVLE16_V_M1_:%[0-9]+]]:vr = PseudoVLE16_V_M1 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ :: (load (<vscale x 4 x s16>), align 16)
+ ; RV64I-NEXT: $v8 = COPY [[PseudoVLE16_V_M1_]]
+ ; RV64I-NEXT: PseudoRET implicit $v8
%0:gprb(p0) = COPY $x10
- %1:vrb(<vscale x 4 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 4 x s16>) from %ir.pa, align 16)
+ %1:vrb(<vscale x 4 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 4 x s16>), align 16)
$v8 = COPY %1(<vscale x 4 x s16>)
PseudoRET implicit $v8
@@ -691,11 +999,28 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10
-
+
+ ; RV32I-LABEL: name: vload_nx2i32_align2
+ ; RV32I: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
+ ; RV32I-NEXT: [[PseudoVLE8_V_M1_:%[0-9]+]]:vr = PseudoVLE8_V_M1 [[DEF]], [[COPY]], -1, 3 /* e8 */, 3 /* ta, ma */ :: (load (<vscale x 8 x s8>), align 2)
+ ; RV32I-NEXT: $v8 = COPY [[PseudoVLE8_V_M1_]]
+ ; RV32I-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64I-LABEL: name: vload_nx2i32_align2
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
+ ; RV64I-NEXT: [[PseudoVLE8_V_M1_:%[0-9]+]]:vr = PseudoVLE8_V_M1 [[DEF]], [[COPY]], -1, 3 /* e8 */, 3 /* ta, ma */ :: (load (<vscale x 8 x s8>), align 2)
+ ; RV64I-NEXT: $v8 = COPY [[PseudoVLE8_V_M1_]]
+ ; RV64I-NEXT: PseudoRET implicit $v8
%0:gprb(p0) = COPY $x10
- %2:vrb(<vscale x 8 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 8 x s8>) from %ir.pa, align 2)
+ %2:vrb(<vscale x 8 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 8 x s8>), align 2)
%1:vrb(<vscale x 2 x s32>) = G_BITCAST %2(<vscale x 8 x s8>)
$v8 = COPY %1(<vscale x 2 x s32>)
PseudoRET implicit $v8
@@ -707,11 +1032,28 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10
-
+
+ ; RV32I-LABEL: name: vload_nx2i32_align4
+ ; RV32I: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
+ ; RV32I-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ :: (load (<vscale x 2 x s32>), align 4)
+ ; RV32I-NEXT: $v8 = COPY [[PseudoVLE32_V_M1_]]
+ ; RV32I-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64I-LABEL: name: vload_nx2i32_align4
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
+ ; RV64I-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ :: (load (<vscale x 2 x s32>), align 4)
+ ; RV64I-NEXT: $v8 = COPY [[PseudoVLE32_V_M1_]]
+ ; RV64I-NEXT: PseudoRET implicit $v8
%0:gprb(p0) = COPY $x10
- %1:vrb(<vscale x 2 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s32>) from %ir.pa, align 4)
+ %1:vrb(<vscale x 2 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s32>), align 4)
$v8 = COPY %1(<vscale x 2 x s32>)
PseudoRET implicit $v8
@@ -722,11 +1064,28 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10
-
+
+ ; RV32I-LABEL: name: vload_nx2i32_align8
+ ; RV32I: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
+ ; RV32I-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ :: (load (<vscale x 2 x s32>))
+ ; RV32I-NEXT: $v8 = COPY [[PseudoVLE32_V_M1_]]
+ ; RV32I-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64I-LABEL: name: vload_nx2i32_align8
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
+ ; RV64I-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ :: (load (<vscale x 2 x s32>))
+ ; RV64I-NEXT: $v8 = COPY [[PseudoVLE32_V_M1_]]
+ ; RV64I-NEXT: PseudoRET implicit $v8
%0:gprb(p0) = COPY $x10
- %1:vrb(<vscale x 2 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s32>) from %ir.pa)
+ %1:vrb(<vscale x 2 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s32>))
$v8 = COPY %1(<vscale x 2 x s32>)
PseudoRET implicit $v8
@@ -737,11 +1096,28 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10
-
+
+ ; RV32I-LABEL: name: vload_nx2i32_align16
+ ; RV32I: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
+ ; RV32I-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ :: (load (<vscale x 2 x s32>), align 16)
+ ; RV32I-NEXT: $v8 = COPY [[PseudoVLE32_V_M1_]]
+ ; RV32I-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64I-LABEL: name: vload_nx2i32_align16
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
+ ; RV64I-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ :: (load (<vscale x 2 x s32>), align 16)
+ ; RV64I-NEXT: $v8 = COPY [[PseudoVLE32_V_M1_]]
+ ; RV64I-NEXT: PseudoRET implicit $v8
%0:gprb(p0) = COPY $x10
- %1:vrb(<vscale x 2 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s32>) from %ir.pa, align 16)
+ %1:vrb(<vscale x 2 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s32>), align 16)
$v8 = COPY %1(<vscale x 2 x s32>)
PseudoRET implicit $v8
@@ -752,11 +1128,28 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10
-
+
+ ; RV32I-LABEL: name: vload_nx2i32_align256
+ ; RV32I: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
+ ; RV32I-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ :: (load (<vscale x 2 x s32>), align 256)
+ ; RV32I-NEXT: $v8 = COPY [[PseudoVLE32_V_M1_]]
+ ; RV32I-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64I-LABEL: name: vload_nx2i32_align256
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
+ ; RV64I-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ :: (load (<vscale x 2 x s32>), align 256)
+ ; RV64I-NEXT: $v8 = COPY [[PseudoVLE32_V_M1_]]
+ ; RV64I-NEXT: PseudoRET implicit $v8
%0:gprb(p0) = COPY $x10
- %1:vrb(<vscale x 2 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s32>) from %ir.pa, align 256)
+ %1:vrb(<vscale x 2 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s32>), align 256)
$v8 = COPY %1(<vscale x 2 x s32>)
PseudoRET implicit $v8
@@ -767,11 +1160,28 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10
-
+
+ ; RV32I-LABEL: name: vload_nx2i64_align4
+ ; RV32I: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF
+ ; RV32I-NEXT: [[PseudoVLE8_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE8_V_M2 [[DEF]], [[COPY]], -1, 3 /* e8 */, 3 /* ta, ma */ :: (load (<vscale x 16 x s8>), align 4)
+ ; RV32I-NEXT: $v8m2 = COPY [[PseudoVLE8_V_M2_]]
+ ; RV32I-NEXT: PseudoRET implicit $v8m2
+ ;
+ ; RV64I-LABEL: name: vload_nx2i64_align4
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF
+ ; RV64I-NEXT: [[PseudoVLE8_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE8_V_M2 [[DEF]], [[COPY]], -1, 3 /* e8 */, 3 /* ta, ma */ :: (load (<vscale x 16 x s8>), align 4)
+ ; RV64I-NEXT: $v8m2 = COPY [[PseudoVLE8_V_M2_]]
+ ; RV64I-NEXT: PseudoRET implicit $v8m2
%0:gprb(p0) = COPY $x10
- %2:vrb(<vscale x 16 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 16 x s8>) from %ir.pa, align 4)
+ %2:vrb(<vscale x 16 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 16 x s8>), align 4)
%1:vrb(<vscale x 2 x s64>) = G_BITCAST %2(<vscale x 16 x s8>)
$v8m2 = COPY %1(<vscale x 2 x s64>)
PseudoRET implicit $v8m2
@@ -783,11 +1193,28 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10
-
+
+ ; RV32I-LABEL: name: vload_nx2i64_align8
+ ; RV32I: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF
+ ; RV32I-NEXT: [[PseudoVLE64_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE64_V_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ :: (load (<vscale x 2 x s64>), align 8)
+ ; RV32I-NEXT: $v8m2 = COPY [[PseudoVLE64_V_M2_]]
+ ; RV32I-NEXT: PseudoRET implicit $v8m2
+ ;
+ ; RV64I-LABEL: name: vload_nx2i64_align8
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF
+ ; RV64I-NEXT: [[PseudoVLE64_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE64_V_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ :: (load (<vscale x 2 x s64>), align 8)
+ ; RV64I-NEXT: $v8m2 = COPY [[PseudoVLE64_V_M2_]]
+ ; RV64I-NEXT: PseudoRET implicit $v8m2
%0:gprb(p0) = COPY $x10
- %1:vrb(<vscale x 2 x s64>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s64>) from %ir.pa, align 8)
+ %1:vrb(<vscale x 2 x s64>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s64>), align 8)
$v8m2 = COPY %1(<vscale x 2 x s64>)
PseudoRET implicit $v8m2
@@ -798,11 +1225,28 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10
-
+
+ ; RV32I-LABEL: name: vload_nx2i64_align16
+ ; RV32I: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF
+ ; RV32I-NEXT: [[PseudoVLE64_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE64_V_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ :: (load (<vscale x 2 x s64>))
+ ; RV32I-NEXT: $v8m2 = COPY [[PseudoVLE64_V_M2_]]
+ ; RV32I-NEXT: PseudoRET implicit $v8m2
+ ;
+ ; RV64I-LABEL: name: vload_nx2i64_align16
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF
+ ; RV64I-NEXT: [[PseudoVLE64_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE64_V_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ :: (load (<vscale x 2 x s64>))
+ ; RV64I-NEXT: $v8m2 = COPY [[PseudoVLE64_V_M2_]]
+ ; RV64I-NEXT: PseudoRET implicit $v8m2
%0:gprb(p0) = COPY $x10
- %1:vrb(<vscale x 2 x s64>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s64>) from %ir.pa)
+ %1:vrb(<vscale x 2 x s64>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s64>))
$v8m2 = COPY %1(<vscale x 2 x s64>)
PseudoRET implicit $v8m2
@@ -813,11 +1257,28 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10
-
+
+ ; RV32I-LABEL: name: vload_nx2i64_align32
+ ; RV32I: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF
+ ; RV32I-NEXT: [[PseudoVLE64_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE64_V_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ :: (load (<vscale x 2 x s64>), align 32)
+ ; RV32I-NEXT: $v8m2 = COPY [[PseudoVLE64_V_M2_]]
+ ; RV32I-NEXT: PseudoRET implicit $v8m2
+ ;
+ ; RV64I-LABEL: name: vload_nx2i64_align32
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF
+ ; RV64I-NEXT: [[PseudoVLE64_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE64_V_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ :: (load (<vscale x 2 x s64>), align 32)
+ ; RV64I-NEXT: $v8m2 = COPY [[PseudoVLE64_V_M2_]]
+ ; RV64I-NEXT: PseudoRET implicit $v8m2
%0:gprb(p0) = COPY $x10
- %1:vrb(<vscale x 2 x s64>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s64>) from %ir.pa, align 32)
+ %1:vrb(<vscale x 2 x s64>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s64>), align 32)
$v8m2 = COPY %1(<vscale x 2 x s64>)
PseudoRET implicit $v8m2
@@ -828,11 +1289,28 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10
-
+
+ ; RV32I-LABEL: name: vload_nx1ptr
+ ; RV32I: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
+ ; RV32I-NEXT: [[PseudoVLE32_V_MF2_:%[0-9]+]]:vr = PseudoVLE32_V_MF2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ :: (load (<vscale x 1 x p0>))
+ ; RV32I-NEXT: $v8 = COPY [[PseudoVLE32_V_MF2_]]
+ ; RV32I-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64I-LABEL: name: vload_nx1ptr
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
+ ; RV64I-NEXT: [[PseudoVLE64_V_M1_:%[0-9]+]]:vr = PseudoVLE64_V_M1 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ :: (load (<vscale x 1 x p0>))
+ ; RV64I-NEXT: $v8 = COPY [[PseudoVLE64_V_M1_]]
+ ; RV64I-NEXT: PseudoRET implicit $v8
%0:gprb(p0) = COPY $x10
- %1:vrb(<vscale x 1 x p0>) = G_LOAD %0(p0) :: (load (<vscale x 1 x p0>) from %ir.pa)
+ %1:vrb(<vscale x 1 x p0>) = G_LOAD %0(p0) :: (load (<vscale x 1 x p0>))
$v8 = COPY %1(<vscale x 1 x p0>)
PseudoRET implicit $v8
@@ -843,11 +1321,28 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10
-
+
+ ; RV32I-LABEL: name: vload_nx2ptr
+ ; RV32I: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
+ ; RV32I-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ :: (load (<vscale x 2 x p0>))
+ ; RV32I-NEXT: $v8 = COPY [[PseudoVLE32_V_M1_]]
+ ; RV32I-NEXT: PseudoRET implicit $v8
+ ;
+ ; RV64I-LABEL: name: vload_nx2ptr
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF
+ ; RV64I-NEXT: [[PseudoVLE64_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE64_V_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ :: (load (<vscale x 2 x p0>))
+ ; RV64I-NEXT: $v8 = COPY [[PseudoVLE64_V_M2_]]
+ ; RV64I-NEXT: PseudoRET implicit $v8
%0:gprb(p0) = COPY $x10
- %1:vrb(<vscale x 2 x p0>) = G_LOAD %0(p0) :: (load (<vscale x 2 x p0>) from %ir.pa)
+ %1:vrb(<vscale x 2 x p0>) = G_LOAD %0(p0) :: (load (<vscale x 2 x p0>))
$v8 = COPY %1(<vscale x 2 x p0>)
PseudoRET implicit $v8
@@ -858,11 +1353,28 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10
-
+
+ ; RV32I-LABEL: name: vload_nx8ptr
+ ; RV32I: liveins: $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
+ ; RV32I-NEXT: [[PseudoVLE32_V_M4_:%[0-9]+]]:vrm4 = PseudoVLE32_V_M4 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ :: (load (<vscale x 8 x p0>))
+ ; RV32I-NEXT: $v8m4 = COPY [[PseudoVLE32_V_M4_]]
+ ; RV32I-NEXT: PseudoRET implicit $v8m4
+ ;
+ ; RV64I-LABEL: name: vload_nx8ptr
+ ; RV64I: liveins: $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
+ ; RV64I-NEXT: [[PseudoVLE64_V_M8_:%[0-9]+]]:vrm8 = PseudoVLE64_V_M8 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ :: (load (<vscale x 8 x p0>))
+ ; RV64I-NEXT: $v8m4 = COPY [[PseudoVLE64_V_M8_]]
+ ; RV64I-NEXT: PseudoRET implicit $v8m4
%0:gprb(p0) = COPY $x10
- %1:vrb(<vscale x 8 x p0>) = G_LOAD %0(p0) :: (load (<vscale x 8 x p0>) from %ir.pa)
+ %1:vrb(<vscale x 8 x p0>) = G_LOAD %0(p0) :: (load (<vscale x 8 x p0>))
$v8m4 = COPY %1(<vscale x 8 x p0>)
PseudoRET implicit $v8m4
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/store.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/store.mir
index 05c00f672dea37..3ae7aa0a7b1e25 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/store.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/store.mir
@@ -1,236 +1,33 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV32I %s
# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV64I %s
---- |
-
- define void @vstore_nx1i8(ptr %pa, <vscale x 1 x i8> %b) #0 {
- store <vscale x 1 x i8> %b, ptr %pa, align 1
- ret void
- }
-
- define void @vstore_nx2i8(ptr %pa, <vscale x 2 x i8> %b) #0 {
- store <vscale x 2 x i8> %b, ptr %pa, align 2
- ret void
- }
-
- define void @vstore_nx4i8(ptr %pa, <vscale x 4 x i8> %b) #0 {
- store <vscale x 4 x i8> %b, ptr %pa, align 4
- ret void
- }
-
- define void @vstore_nx8i8(ptr %pa, <vscale x 8 x i8> %b) #0 {
- store <vscale x 8 x i8> %b, ptr %pa, align 8
- ret void
- }
-
- define void @vstore_nx16i8(ptr %pa, <vscale x 16 x i8> %b) #0 {
- store <vscale x 16 x i8> %b, ptr %pa, align 16
- ret void
- }
-
- define void @vstore_nx32i8(ptr %pa, <vscale x 32 x i8> %b) #0 {
- store <vscale x 32 x i8> %b, ptr %pa, align 32
- ret void
- }
-
- define void @vstore_nx64i8(ptr %pa, <vscale x 64 x i8> %b) #0 {
- store <vscale x 64 x i8> %b, ptr %pa, align 64
- ret void
- }
-
- define void @vstore_nx1i16(ptr %pa, <vscale x 1 x i16> %b) #0 {
- store <vscale x 1 x i16> %b, ptr %pa, align 2
- ret void
- }
-
- define void @vstore_nx2i16(ptr %pa, <vscale x 2 x i16> %b) #0 {
- store <vscale x 2 x i16> %b, ptr %pa, align 4
- ret void
- }
-
- define void @vstore_nx4i16(ptr %pa, <vscale x 4 x i16> %b) #0 {
- store <vscale x 4 x i16> %b, ptr %pa, align 8
- ret void
- }
-
- define void @vstore_nx8i16(ptr %pa, <vscale x 8 x i16> %b) #0 {
- store <vscale x 8 x i16> %b, ptr %pa, align 16
- ret void
- }
-
- define void @vstore_nx16i16(ptr %pa, <vscale x 16 x i16> %b) #0 {
- store <vscale x 16 x i16> %b, ptr %pa, align 32
- ret void
- }
-
- define void @vstore_nx32i16(ptr %pa, <vscale x 32 x i16> %b) #0 {
- store <vscale x 32 x i16> %b, ptr %pa, align 64
- ret void
- }
-
- define void @vstore_nx1i32(ptr %pa, <vscale x 1 x i32> %b) #0 {
- store <vscale x 1 x i32> %b, ptr %pa, align 4
- ret void
- }
-
- define void @vstore_nx2i32(ptr %pa, <vscale x 2 x i32> %b) #0 {
- store <vscale x 2 x i32> %b, ptr %pa, align 8
- ret void
- }
-
- define void @vstore_nx4i32(ptr %pa, <vscale x 4 x i32> %b) #0 {
- store <vscale x 4 x i32> %b, ptr %pa, align 16
- ret void
- }
-
- define void @vstore_nx8i32(ptr %pa, <vscale x 8 x i32> %b) #0 {
- store <vscale x 8 x i32> %b, ptr %pa, align 32
- ret void
- }
-
- define void @vstore_nx16i32(ptr %pa, <vscale x 16 x i32> %b) #0 {
- store <vscale x 16 x i32> %b, ptr %pa, align 64
- ret void
- }
-
- define void @vstore_nx1i64(ptr %pa, <vscale x 1 x i64> %b) #0 {
- store <vscale x 1 x i64> %b, ptr %pa, align 8
- ret void
- }
-
- define void @vstore_nx2i64(ptr %pa, <vscale x 2 x i64> %b) #0 {
- store <vscale x 2 x i64> %b, ptr %pa, align 16
- ret void
- }
-
- define void @vstore_nx4i64(ptr %pa, <vscale x 4 x i64> %b) #0 {
- store <vscale x 4 x i64> %b, ptr %pa, align 32
- ret void
- }
-
- define void @vstore_nx8i64(ptr %pa, <vscale x 8 x i64> %b) #0 {
- store <vscale x 8 x i64> %b, ptr %pa, align 64
- ret void
- }
-
- define void @vstore_nx16i8_align1(ptr %pa, <vscale x 16 x i8> %b) #0 {
- store <vscale x 16 x i8> %b, ptr %pa, align 1
- ret void
- }
-
- define void @vstore_nx16i8_align2(ptr %pa, <vscale x 16 x i8> %b) #0 {
- store <vscale x 16 x i8> %b, ptr %pa, align 2
- ret void
- }
-
- define void @vstore_nx16i8_align16(ptr %pa, <vscale x 16 x i8> %b) #0 {
- store <vscale x 16 x i8> %b, ptr %pa, align 16
- ret void
- }
-
- define void @vstore_nx16i8_align64(ptr %pa, <vscale x 16 x i8> %b) #0 {
- store <vscale x 16 x i8> %b, ptr %pa, align 64
- ret void
- }
-
- define void @vstore_nx4i16_align1(ptr %pa, <vscale x 4 x i16> %b) #0 {
- store <vscale x 4 x i16> %b, ptr %pa, align 1
- ret void
- }
-
- define void @vstore_nx4i16_align2(ptr %pa, <vscale x 4 x i16> %b) #0 {
- store <vscale x 4 x i16> %b, ptr %pa, align 2
- ret void
- }
-
- define void @vstore_nx4i16_align4(ptr %pa, <vscale x 4 x i16> %b) #0 {
- store <vscale x 4 x i16> %b, ptr %pa, align 4
- ret void
- }
-
- define void @vstore_nx4i16_align8(ptr %pa, <vscale x 4 x i16> %b) #0 {
- store <vscale x 4 x i16> %b, ptr %pa, align 8
- ret void
- }
-
- define void @vstore_nx4i16_align16(ptr %pa, <vscale x 4 x i16> %b) #0 {
- store <vscale x 4 x i16> %b, ptr %pa, align 16
- ret void
- }
-
- define void @vstore_nx2i32_align2(ptr %pa, <vscale x 2 x i32> %b) #0 {
- store <vscale x 2 x i32> %b, ptr %pa, align 2
- ret void
- }
-
- define void @vstore_nx2i32_align4(ptr %pa, <vscale x 2 x i32> %b) #0 {
- store <vscale x 2 x i32> %b, ptr %pa, align 4
- ret void
- }
-
- define void @vstore_nx2i32_align8(ptr %pa, <vscale x 2 x i32> %b) #0 {
- store <vscale x 2 x i32> %b, ptr %pa, align 8
- ret void
- }
-
- define void @vstore_nx2i32_align16(ptr %pa, <vscale x 2 x i32> %b) #0 {
- store <vscale x 2 x i32> %b, ptr %pa, align 16
- ret void
- }
-
- define void @vstore_nx2i32_align256(ptr %pa, <vscale x 2 x i32> %b) #0 {
- store <vscale x 2 x i32> %b, ptr %pa, align 256
- ret void
- }
-
- define void @vstore_nx2i64_align4(ptr %pa, <vscale x 2 x i64> %b) #0 {
- store <vscale x 2 x i64> %b, ptr %pa, align 4
- ret void
- }
-
- define void @vstore_nx2i64_align8(ptr %pa, <vscale x 2 x i64> %b) #0 {
- store <vscale x 2 x i64> %b, ptr %pa, align 8
- ret void
- }
-
- define void @vstore_nx2i64_align16(ptr %pa, <vscale x 2 x i64> %b) #0 {
- store <vscale x 2 x i64> %b, ptr %pa, align 16
- ret void
- }
-
- define void @vstore_nx2i64_align32(ptr %pa, <vscale x 2 x i64> %b) #0 {
- store <vscale x 2 x i64> %b, ptr %pa, align 32
- ret void
- }
-
- define void @vstore_nx1ptr(ptr %pa, <vscale x 1 x ptr> %b) #0 {
- store <vscale x 1 x ptr> %b, ptr %pa, align 4
- ret void
- }
-
- define void @vstore_nx2ptr(ptr %pa, <vscale x 2 x ptr> %b) #0 {
- store <vscale x 2 x ptr> %b, ptr %pa, align 8
- ret void
- }
-
- define void @vstore_nx8ptr(ptr %pa, <vscale x 8 x ptr> %b) #0 {
- store <vscale x 8 x ptr> %b, ptr %pa, align 32
- ret void
- }
-
-...
---
name: vstore_nx1i8
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $v8, $x10
-
+
+ ; RV32I-LABEL: name: vstore_nx1i8
+ ; RV32I: liveins: $v8, $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8
+ ; RV32I-NEXT: PseudoVSE8_V_MF8 [[COPY1]], [[COPY]], -1, 3 /* e8 */ :: (store (<vscale x 1 x s8>))
+ ; RV32I-NEXT: PseudoRET
+ ;
+ ; RV64I-LABEL: name: vstore_nx1i8
+ ; RV64I: liveins: $v8, $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8
+ ; RV64I-NEXT: PseudoVSE8_V_MF8 [[COPY1]], [[COPY]], -1, 3 /* e8 */ :: (store (<vscale x 1 x s8>))
+ ; RV64I-NEXT: PseudoRET
%0:gprb(p0) = COPY $x10
%1:vrb(<vscale x 1 x s8>) = COPY $v8
- G_STORE %1(<vscale x 1 x s8>), %0(p0) :: (store (<vscale x 1 x s8>) into %ir.pa)
+ G_STORE %1(<vscale x 1 x s8>), %0(p0) :: (store (<vscale x 1 x s8>))
PseudoRET
...
@@ -240,12 +37,27 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $v8, $x10
-
+
+ ; RV32I-LABEL: name: vstore_nx2i8
+ ; RV32I: liveins: $v8, $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8
+ ; RV32I-NEXT: PseudoVSE8_V_MF4 [[COPY1]], [[COPY]], -1, 3 /* e8 */ :: (store (<vscale x 2 x s8>))
+ ; RV32I-NEXT: PseudoRET
+ ;
+ ; RV64I-LABEL: name: vstore_nx2i8
+ ; RV64I: liveins: $v8, $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8
+ ; RV64I-NEXT: PseudoVSE8_V_MF4 [[COPY1]], [[COPY]], -1, 3 /* e8 */ :: (store (<vscale x 2 x s8>))
+ ; RV64I-NEXT: PseudoRET
%0:gprb(p0) = COPY $x10
%1:vrb(<vscale x 2 x s8>) = COPY $v8
- G_STORE %1(<vscale x 2 x s8>), %0(p0) :: (store (<vscale x 2 x s8>) into %ir.pa)
+ G_STORE %1(<vscale x 2 x s8>), %0(p0) :: (store (<vscale x 2 x s8>))
PseudoRET
...
@@ -255,12 +67,27 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $v8, $x10
-
+
+ ; RV32I-LABEL: name: vstore_nx4i8
+ ; RV32I: liveins: $v8, $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8
+ ; RV32I-NEXT: PseudoVSE8_V_MF2 [[COPY1]], [[COPY]], -1, 3 /* e8 */ :: (store (<vscale x 4 x s8>))
+ ; RV32I-NEXT: PseudoRET
+ ;
+ ; RV64I-LABEL: name: vstore_nx4i8
+ ; RV64I: liveins: $v8, $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8
+ ; RV64I-NEXT: PseudoVSE8_V_MF2 [[COPY1]], [[COPY]], -1, 3 /* e8 */ :: (store (<vscale x 4 x s8>))
+ ; RV64I-NEXT: PseudoRET
%0:gprb(p0) = COPY $x10
%1:vrb(<vscale x 4 x s8>) = COPY $v8
- G_STORE %1(<vscale x 4 x s8>), %0(p0) :: (store (<vscale x 4 x s8>) into %ir.pa)
+ G_STORE %1(<vscale x 4 x s8>), %0(p0) :: (store (<vscale x 4 x s8>))
PseudoRET
...
@@ -270,12 +97,27 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $v8, $x10
-
+
+ ; RV32I-LABEL: name: vstore_nx8i8
+ ; RV32I: liveins: $v8, $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8
+ ; RV32I-NEXT: PseudoVSE8_V_M1 [[COPY1]], [[COPY]], -1, 3 /* e8 */ :: (store (<vscale x 8 x s8>))
+ ; RV32I-NEXT: PseudoRET
+ ;
+ ; RV64I-LABEL: name: vstore_nx8i8
+ ; RV64I: liveins: $v8, $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8
+ ; RV64I-NEXT: PseudoVSE8_V_M1 [[COPY1]], [[COPY]], -1, 3 /* e8 */ :: (store (<vscale x 8 x s8>))
+ ; RV64I-NEXT: PseudoRET
%0:gprb(p0) = COPY $x10
%1:vrb(<vscale x 8 x s8>) = COPY $v8
- G_STORE %1(<vscale x 8 x s8>), %0(p0) :: (store (<vscale x 8 x s8>) into %ir.pa)
+ G_STORE %1(<vscale x 8 x s8>), %0(p0) :: (store (<vscale x 8 x s8>))
PseudoRET
...
@@ -285,12 +127,27 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10, $v8m2
-
+
+ ; RV32I-LABEL: name: vstore_nx16i8
+ ; RV32I: liveins: $x10, $v8m2
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v8m2
+ ; RV32I-NEXT: PseudoVSE8_V_M2 [[COPY1]], [[COPY]], -1, 3 /* e8 */ :: (store (<vscale x 16 x s8>))
+ ; RV32I-NEXT: PseudoRET
+ ;
+ ; RV64I-LABEL: name: vstore_nx16i8
+ ; RV64I: liveins: $x10, $v8m2
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v8m2
+ ; RV64I-NEXT: PseudoVSE8_V_M2 [[COPY1]], [[COPY]], -1, 3 /* e8 */ :: (store (<vscale x 16 x s8>))
+ ; RV64I-NEXT: PseudoRET
%0:gprb(p0) = COPY $x10
%1:vrb(<vscale x 16 x s8>) = COPY $v8m2
- G_STORE %1(<vscale x 16 x s8>), %0(p0) :: (store (<vscale x 16 x s8>) into %ir.pa)
+ G_STORE %1(<vscale x 16 x s8>), %0(p0) :: (store (<vscale x 16 x s8>))
PseudoRET
...
@@ -300,12 +157,27 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10, $v8m4
-
+
+ ; RV32I-LABEL: name: vstore_nx32i8
+ ; RV32I: liveins: $x10, $v8m4
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY $v8m4
+ ; RV32I-NEXT: PseudoVSE8_V_M4 [[COPY1]], [[COPY]], -1, 3 /* e8 */ :: (store (<vscale x 32 x s8>))
+ ; RV32I-NEXT: PseudoRET
+ ;
+ ; RV64I-LABEL: name: vstore_nx32i8
+ ; RV64I: liveins: $x10, $v8m4
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY $v8m4
+ ; RV64I-NEXT: PseudoVSE8_V_M4 [[COPY1]], [[COPY]], -1, 3 /* e8 */ :: (store (<vscale x 32 x s8>))
+ ; RV64I-NEXT: PseudoRET
%0:gprb(p0) = COPY $x10
%1:vrb(<vscale x 32 x s8>) = COPY $v8m4
- G_STORE %1(<vscale x 32 x s8>), %0(p0) :: (store (<vscale x 32 x s8>) into %ir.pa)
+ G_STORE %1(<vscale x 32 x s8>), %0(p0) :: (store (<vscale x 32 x s8>))
PseudoRET
...
@@ -315,12 +187,27 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10, $v8m8
-
+
+ ; RV32I-LABEL: name: vstore_nx64i8
+ ; RV32I: liveins: $x10, $v8m8
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY $v8m8
+ ; RV32I-NEXT: PseudoVSE8_V_M8 [[COPY1]], [[COPY]], -1, 3 /* e8 */ :: (store (<vscale x 64 x s8>))
+ ; RV32I-NEXT: PseudoRET
+ ;
+ ; RV64I-LABEL: name: vstore_nx64i8
+ ; RV64I: liveins: $x10, $v8m8
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY $v8m8
+ ; RV64I-NEXT: PseudoVSE8_V_M8 [[COPY1]], [[COPY]], -1, 3 /* e8 */ :: (store (<vscale x 64 x s8>))
+ ; RV64I-NEXT: PseudoRET
%0:gprb(p0) = COPY $x10
%1:vrb(<vscale x 64 x s8>) = COPY $v8m8
- G_STORE %1(<vscale x 64 x s8>), %0(p0) :: (store (<vscale x 64 x s8>) into %ir.pa)
+ G_STORE %1(<vscale x 64 x s8>), %0(p0) :: (store (<vscale x 64 x s8>))
PseudoRET
...
@@ -330,12 +217,27 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $v8, $x10
-
+
+ ; RV32I-LABEL: name: vstore_nx1i16
+ ; RV32I: liveins: $v8, $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8
+ ; RV32I-NEXT: PseudoVSE16_V_MF4 [[COPY1]], [[COPY]], -1, 4 /* e16 */ :: (store (<vscale x 1 x s16>))
+ ; RV32I-NEXT: PseudoRET
+ ;
+ ; RV64I-LABEL: name: vstore_nx1i16
+ ; RV64I: liveins: $v8, $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8
+ ; RV64I-NEXT: PseudoVSE16_V_MF4 [[COPY1]], [[COPY]], -1, 4 /* e16 */ :: (store (<vscale x 1 x s16>))
+ ; RV64I-NEXT: PseudoRET
%0:gprb(p0) = COPY $x10
%1:vrb(<vscale x 1 x s16>) = COPY $v8
- G_STORE %1(<vscale x 1 x s16>), %0(p0) :: (store (<vscale x 1 x s16>) into %ir.pa)
+ G_STORE %1(<vscale x 1 x s16>), %0(p0) :: (store (<vscale x 1 x s16>))
PseudoRET
...
@@ -345,12 +247,27 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $v8, $x10
-
+
+ ; RV32I-LABEL: name: vstore_nx2i16
+ ; RV32I: liveins: $v8, $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8
+ ; RV32I-NEXT: PseudoVSE16_V_MF2 [[COPY1]], [[COPY]], -1, 4 /* e16 */ :: (store (<vscale x 2 x s16>))
+ ; RV32I-NEXT: PseudoRET
+ ;
+ ; RV64I-LABEL: name: vstore_nx2i16
+ ; RV64I: liveins: $v8, $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8
+ ; RV64I-NEXT: PseudoVSE16_V_MF2 [[COPY1]], [[COPY]], -1, 4 /* e16 */ :: (store (<vscale x 2 x s16>))
+ ; RV64I-NEXT: PseudoRET
%0:gprb(p0) = COPY $x10
%1:vrb(<vscale x 2 x s16>) = COPY $v8
- G_STORE %1(<vscale x 2 x s16>), %0(p0) :: (store (<vscale x 2 x s16>) into %ir.pa)
+ G_STORE %1(<vscale x 2 x s16>), %0(p0) :: (store (<vscale x 2 x s16>))
PseudoRET
...
@@ -360,12 +277,27 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $v8, $x10
-
+
+ ; RV32I-LABEL: name: vstore_nx4i16
+ ; RV32I: liveins: $v8, $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8
+ ; RV32I-NEXT: PseudoVSE16_V_M1 [[COPY1]], [[COPY]], -1, 4 /* e16 */ :: (store (<vscale x 4 x s16>))
+ ; RV32I-NEXT: PseudoRET
+ ;
+ ; RV64I-LABEL: name: vstore_nx4i16
+ ; RV64I: liveins: $v8, $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8
+ ; RV64I-NEXT: PseudoVSE16_V_M1 [[COPY1]], [[COPY]], -1, 4 /* e16 */ :: (store (<vscale x 4 x s16>))
+ ; RV64I-NEXT: PseudoRET
%0:gprb(p0) = COPY $x10
%1:vrb(<vscale x 4 x s16>) = COPY $v8
- G_STORE %1(<vscale x 4 x s16>), %0(p0) :: (store (<vscale x 4 x s16>) into %ir.pa)
+ G_STORE %1(<vscale x 4 x s16>), %0(p0) :: (store (<vscale x 4 x s16>))
PseudoRET
...
@@ -375,12 +307,27 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10, $v8m2
-
+
+ ; RV32I-LABEL: name: vstore_nx8i16
+ ; RV32I: liveins: $x10, $v8m2
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v8m2
+ ; RV32I-NEXT: PseudoVSE16_V_M2 [[COPY1]], [[COPY]], -1, 4 /* e16 */ :: (store (<vscale x 8 x s16>))
+ ; RV32I-NEXT: PseudoRET
+ ;
+ ; RV64I-LABEL: name: vstore_nx8i16
+ ; RV64I: liveins: $x10, $v8m2
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v8m2
+ ; RV64I-NEXT: PseudoVSE16_V_M2 [[COPY1]], [[COPY]], -1, 4 /* e16 */ :: (store (<vscale x 8 x s16>))
+ ; RV64I-NEXT: PseudoRET
%0:gprb(p0) = COPY $x10
%1:vrb(<vscale x 8 x s16>) = COPY $v8m2
- G_STORE %1(<vscale x 8 x s16>), %0(p0) :: (store (<vscale x 8 x s16>) into %ir.pa)
+ G_STORE %1(<vscale x 8 x s16>), %0(p0) :: (store (<vscale x 8 x s16>))
PseudoRET
...
@@ -390,12 +337,27 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10, $v8m4
-
+
+ ; RV32I-LABEL: name: vstore_nx16i16
+ ; RV32I: liveins: $x10, $v8m4
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY $v8m4
+ ; RV32I-NEXT: PseudoVSE16_V_M4 [[COPY1]], [[COPY]], -1, 4 /* e16 */ :: (store (<vscale x 16 x s16>))
+ ; RV32I-NEXT: PseudoRET
+ ;
+ ; RV64I-LABEL: name: vstore_nx16i16
+ ; RV64I: liveins: $x10, $v8m4
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY $v8m4
+ ; RV64I-NEXT: PseudoVSE16_V_M4 [[COPY1]], [[COPY]], -1, 4 /* e16 */ :: (store (<vscale x 16 x s16>))
+ ; RV64I-NEXT: PseudoRET
%0:gprb(p0) = COPY $x10
%1:vrb(<vscale x 16 x s16>) = COPY $v8m4
- G_STORE %1(<vscale x 16 x s16>), %0(p0) :: (store (<vscale x 16 x s16>) into %ir.pa)
+ G_STORE %1(<vscale x 16 x s16>), %0(p0) :: (store (<vscale x 16 x s16>))
PseudoRET
...
@@ -405,12 +367,27 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10, $v8m8
-
+
+ ; RV32I-LABEL: name: vstore_nx32i16
+ ; RV32I: liveins: $x10, $v8m8
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY $v8m8
+ ; RV32I-NEXT: PseudoVSE16_V_M8 [[COPY1]], [[COPY]], -1, 4 /* e16 */ :: (store (<vscale x 32 x s16>))
+ ; RV32I-NEXT: PseudoRET
+ ;
+ ; RV64I-LABEL: name: vstore_nx32i16
+ ; RV64I: liveins: $x10, $v8m8
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY $v8m8
+ ; RV64I-NEXT: PseudoVSE16_V_M8 [[COPY1]], [[COPY]], -1, 4 /* e16 */ :: (store (<vscale x 32 x s16>))
+ ; RV64I-NEXT: PseudoRET
%0:gprb(p0) = COPY $x10
%1:vrb(<vscale x 32 x s16>) = COPY $v8m8
- G_STORE %1(<vscale x 32 x s16>), %0(p0) :: (store (<vscale x 32 x s16>) into %ir.pa)
+ G_STORE %1(<vscale x 32 x s16>), %0(p0) :: (store (<vscale x 32 x s16>))
PseudoRET
...
@@ -420,12 +397,27 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $v8, $x10
-
+
+ ; RV32I-LABEL: name: vstore_nx1i32
+ ; RV32I: liveins: $v8, $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8
+ ; RV32I-NEXT: PseudoVSE32_V_MF2 [[COPY1]], [[COPY]], -1, 5 /* e32 */ :: (store (<vscale x 1 x s32>))
+ ; RV32I-NEXT: PseudoRET
+ ;
+ ; RV64I-LABEL: name: vstore_nx1i32
+ ; RV64I: liveins: $v8, $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8
+ ; RV64I-NEXT: PseudoVSE32_V_MF2 [[COPY1]], [[COPY]], -1, 5 /* e32 */ :: (store (<vscale x 1 x s32>))
+ ; RV64I-NEXT: PseudoRET
%0:gprb(p0) = COPY $x10
%1:vrb(<vscale x 1 x s32>) = COPY $v8
- G_STORE %1(<vscale x 1 x s32>), %0(p0) :: (store (<vscale x 1 x s32>) into %ir.pa)
+ G_STORE %1(<vscale x 1 x s32>), %0(p0) :: (store (<vscale x 1 x s32>))
PseudoRET
...
@@ -435,12 +427,27 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $v8, $x10
-
+
+ ; RV32I-LABEL: name: vstore_nx2i32
+ ; RV32I: liveins: $v8, $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8
+ ; RV32I-NEXT: PseudoVSE32_V_M1 [[COPY1]], [[COPY]], -1, 5 /* e32 */ :: (store (<vscale x 2 x s32>))
+ ; RV32I-NEXT: PseudoRET
+ ;
+ ; RV64I-LABEL: name: vstore_nx2i32
+ ; RV64I: liveins: $v8, $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8
+ ; RV64I-NEXT: PseudoVSE32_V_M1 [[COPY1]], [[COPY]], -1, 5 /* e32 */ :: (store (<vscale x 2 x s32>))
+ ; RV64I-NEXT: PseudoRET
%0:gprb(p0) = COPY $x10
%1:vrb(<vscale x 2 x s32>) = COPY $v8
- G_STORE %1(<vscale x 2 x s32>), %0(p0) :: (store (<vscale x 2 x s32>) into %ir.pa)
+ G_STORE %1(<vscale x 2 x s32>), %0(p0) :: (store (<vscale x 2 x s32>))
PseudoRET
...
@@ -450,12 +457,27 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10, $v8m2
-
+
+ ; RV32I-LABEL: name: vstore_nx4i32
+ ; RV32I: liveins: $x10, $v8m2
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v8m2
+ ; RV32I-NEXT: PseudoVSE32_V_M2 [[COPY1]], [[COPY]], -1, 5 /* e32 */ :: (store (<vscale x 4 x s32>))
+ ; RV32I-NEXT: PseudoRET
+ ;
+ ; RV64I-LABEL: name: vstore_nx4i32
+ ; RV64I: liveins: $x10, $v8m2
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v8m2
+ ; RV64I-NEXT: PseudoVSE32_V_M2 [[COPY1]], [[COPY]], -1, 5 /* e32 */ :: (store (<vscale x 4 x s32>))
+ ; RV64I-NEXT: PseudoRET
%0:gprb(p0) = COPY $x10
%1:vrb(<vscale x 4 x s32>) = COPY $v8m2
- G_STORE %1(<vscale x 4 x s32>), %0(p0) :: (store (<vscale x 4 x s32>) into %ir.pa)
+ G_STORE %1(<vscale x 4 x s32>), %0(p0) :: (store (<vscale x 4 x s32>))
PseudoRET
...
@@ -465,12 +487,27 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10, $v8m4
-
+
+ ; RV32I-LABEL: name: vstore_nx8i32
+ ; RV32I: liveins: $x10, $v8m4
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY $v8m4
+ ; RV32I-NEXT: PseudoVSE32_V_M4 [[COPY1]], [[COPY]], -1, 5 /* e32 */ :: (store (<vscale x 8 x s32>))
+ ; RV32I-NEXT: PseudoRET
+ ;
+ ; RV64I-LABEL: name: vstore_nx8i32
+ ; RV64I: liveins: $x10, $v8m4
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY $v8m4
+ ; RV64I-NEXT: PseudoVSE32_V_M4 [[COPY1]], [[COPY]], -1, 5 /* e32 */ :: (store (<vscale x 8 x s32>))
+ ; RV64I-NEXT: PseudoRET
%0:gprb(p0) = COPY $x10
%1:vrb(<vscale x 8 x s32>) = COPY $v8m4
- G_STORE %1(<vscale x 8 x s32>), %0(p0) :: (store (<vscale x 8 x s32>) into %ir.pa)
+ G_STORE %1(<vscale x 8 x s32>), %0(p0) :: (store (<vscale x 8 x s32>))
PseudoRET
...
@@ -480,12 +517,27 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10, $v8m8
-
+
+ ; RV32I-LABEL: name: vstore_nx16i32
+ ; RV32I: liveins: $x10, $v8m8
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY $v8m8
+ ; RV32I-NEXT: PseudoVSE32_V_M8 [[COPY1]], [[COPY]], -1, 5 /* e32 */ :: (store (<vscale x 16 x s32>))
+ ; RV32I-NEXT: PseudoRET
+ ;
+ ; RV64I-LABEL: name: vstore_nx16i32
+ ; RV64I: liveins: $x10, $v8m8
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY $v8m8
+ ; RV64I-NEXT: PseudoVSE32_V_M8 [[COPY1]], [[COPY]], -1, 5 /* e32 */ :: (store (<vscale x 16 x s32>))
+ ; RV64I-NEXT: PseudoRET
%0:gprb(p0) = COPY $x10
%1:vrb(<vscale x 16 x s32>) = COPY $v8m8
- G_STORE %1(<vscale x 16 x s32>), %0(p0) :: (store (<vscale x 16 x s32>) into %ir.pa)
+ G_STORE %1(<vscale x 16 x s32>), %0(p0) :: (store (<vscale x 16 x s32>))
PseudoRET
...
@@ -495,12 +547,27 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $v8, $x10
-
+
+ ; RV32I-LABEL: name: vstore_nx1i64
+ ; RV32I: liveins: $v8, $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8
+ ; RV32I-NEXT: PseudoVSE64_V_M1 [[COPY1]], [[COPY]], -1, 6 /* e64 */ :: (store (<vscale x 1 x s64>))
+ ; RV32I-NEXT: PseudoRET
+ ;
+ ; RV64I-LABEL: name: vstore_nx1i64
+ ; RV64I: liveins: $v8, $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8
+ ; RV64I-NEXT: PseudoVSE64_V_M1 [[COPY1]], [[COPY]], -1, 6 /* e64 */ :: (store (<vscale x 1 x s64>))
+ ; RV64I-NEXT: PseudoRET
%0:gprb(p0) = COPY $x10
%1:vrb(<vscale x 1 x s64>) = COPY $v8
- G_STORE %1(<vscale x 1 x s64>), %0(p0) :: (store (<vscale x 1 x s64>) into %ir.pa)
+ G_STORE %1(<vscale x 1 x s64>), %0(p0) :: (store (<vscale x 1 x s64>))
PseudoRET
...
@@ -510,12 +577,27 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10, $v8m2
-
+
+ ; RV32I-LABEL: name: vstore_nx2i64
+ ; RV32I: liveins: $x10, $v8m2
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v8m2
+ ; RV32I-NEXT: PseudoVSE64_V_M2 [[COPY1]], [[COPY]], -1, 6 /* e64 */ :: (store (<vscale x 2 x s64>))
+ ; RV32I-NEXT: PseudoRET
+ ;
+ ; RV64I-LABEL: name: vstore_nx2i64
+ ; RV64I: liveins: $x10, $v8m2
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v8m2
+ ; RV64I-NEXT: PseudoVSE64_V_M2 [[COPY1]], [[COPY]], -1, 6 /* e64 */ :: (store (<vscale x 2 x s64>))
+ ; RV64I-NEXT: PseudoRET
%0:gprb(p0) = COPY $x10
%1:vrb(<vscale x 2 x s64>) = COPY $v8m2
- G_STORE %1(<vscale x 2 x s64>), %0(p0) :: (store (<vscale x 2 x s64>) into %ir.pa)
+ G_STORE %1(<vscale x 2 x s64>), %0(p0) :: (store (<vscale x 2 x s64>))
PseudoRET
...
@@ -525,12 +607,27 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10, $v8m4
-
+
+ ; RV32I-LABEL: name: vstore_nx4i64
+ ; RV32I: liveins: $x10, $v8m4
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY $v8m4
+ ; RV32I-NEXT: PseudoVSE64_V_M4 [[COPY1]], [[COPY]], -1, 6 /* e64 */ :: (store (<vscale x 4 x s64>))
+ ; RV32I-NEXT: PseudoRET
+ ;
+ ; RV64I-LABEL: name: vstore_nx4i64
+ ; RV64I: liveins: $x10, $v8m4
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY $v8m4
+ ; RV64I-NEXT: PseudoVSE64_V_M4 [[COPY1]], [[COPY]], -1, 6 /* e64 */ :: (store (<vscale x 4 x s64>))
+ ; RV64I-NEXT: PseudoRET
%0:gprb(p0) = COPY $x10
%1:vrb(<vscale x 4 x s64>) = COPY $v8m4
- G_STORE %1(<vscale x 4 x s64>), %0(p0) :: (store (<vscale x 4 x s64>) into %ir.pa)
+ G_STORE %1(<vscale x 4 x s64>), %0(p0) :: (store (<vscale x 4 x s64>))
PseudoRET
...
@@ -540,12 +637,27 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10, $v8m8
-
+
+ ; RV32I-LABEL: name: vstore_nx8i64
+ ; RV32I: liveins: $x10, $v8m8
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY $v8m8
+ ; RV32I-NEXT: PseudoVSE64_V_M8 [[COPY1]], [[COPY]], -1, 6 /* e64 */ :: (store (<vscale x 8 x s64>))
+ ; RV32I-NEXT: PseudoRET
+ ;
+ ; RV64I-LABEL: name: vstore_nx8i64
+ ; RV64I: liveins: $x10, $v8m8
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY $v8m8
+ ; RV64I-NEXT: PseudoVSE64_V_M8 [[COPY1]], [[COPY]], -1, 6 /* e64 */ :: (store (<vscale x 8 x s64>))
+ ; RV64I-NEXT: PseudoRET
%0:gprb(p0) = COPY $x10
%1:vrb(<vscale x 8 x s64>) = COPY $v8m8
- G_STORE %1(<vscale x 8 x s64>), %0(p0) :: (store (<vscale x 8 x s64>) into %ir.pa)
+ G_STORE %1(<vscale x 8 x s64>), %0(p0) :: (store (<vscale x 8 x s64>))
PseudoRET
...
@@ -555,12 +667,27 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10, $v8m2
-
+
+ ; RV32I-LABEL: name: vstore_nx16i8_align1
+ ; RV32I: liveins: $x10, $v8m2
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v8m2
+ ; RV32I-NEXT: PseudoVSE8_V_M2 [[COPY1]], [[COPY]], -1, 3 /* e8 */ :: (store (<vscale x 16 x s8>), align 1)
+ ; RV32I-NEXT: PseudoRET
+ ;
+ ; RV64I-LABEL: name: vstore_nx16i8_align1
+ ; RV64I: liveins: $x10, $v8m2
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v8m2
+ ; RV64I-NEXT: PseudoVSE8_V_M2 [[COPY1]], [[COPY]], -1, 3 /* e8 */ :: (store (<vscale x 16 x s8>), align 1)
+ ; RV64I-NEXT: PseudoRET
%0:gprb(p0) = COPY $x10
%1:vrb(<vscale x 16 x s8>) = COPY $v8m2
- G_STORE %1(<vscale x 16 x s8>), %0(p0) :: (store (<vscale x 16 x s8>) into %ir.pa, align 1)
+ G_STORE %1(<vscale x 16 x s8>), %0(p0) :: (store (<vscale x 16 x s8>), align 1)
PseudoRET
...
@@ -570,12 +697,27 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10, $v8m2
-
+
+ ; RV32I-LABEL: name: vstore_nx16i8_align2
+ ; RV32I: liveins: $x10, $v8m2
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v8m2
+ ; RV32I-NEXT: PseudoVSE8_V_M2 [[COPY1]], [[COPY]], -1, 3 /* e8 */ :: (store (<vscale x 16 x s8>), align 2)
+ ; RV32I-NEXT: PseudoRET
+ ;
+ ; RV64I-LABEL: name: vstore_nx16i8_align2
+ ; RV64I: liveins: $x10, $v8m2
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v8m2
+ ; RV64I-NEXT: PseudoVSE8_V_M2 [[COPY1]], [[COPY]], -1, 3 /* e8 */ :: (store (<vscale x 16 x s8>), align 2)
+ ; RV64I-NEXT: PseudoRET
%0:gprb(p0) = COPY $x10
%1:vrb(<vscale x 16 x s8>) = COPY $v8m2
- G_STORE %1(<vscale x 16 x s8>), %0(p0) :: (store (<vscale x 16 x s8>) into %ir.pa, align 2)
+ G_STORE %1(<vscale x 16 x s8>), %0(p0) :: (store (<vscale x 16 x s8>), align 2)
PseudoRET
...
@@ -585,12 +727,27 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10, $v8m2
-
+
+ ; RV32I-LABEL: name: vstore_nx16i8_align16
+ ; RV32I: liveins: $x10, $v8m2
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v8m2
+ ; RV32I-NEXT: PseudoVSE8_V_M2 [[COPY1]], [[COPY]], -1, 3 /* e8 */ :: (store (<vscale x 16 x s8>))
+ ; RV32I-NEXT: PseudoRET
+ ;
+ ; RV64I-LABEL: name: vstore_nx16i8_align16
+ ; RV64I: liveins: $x10, $v8m2
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v8m2
+ ; RV64I-NEXT: PseudoVSE8_V_M2 [[COPY1]], [[COPY]], -1, 3 /* e8 */ :: (store (<vscale x 16 x s8>))
+ ; RV64I-NEXT: PseudoRET
%0:gprb(p0) = COPY $x10
%1:vrb(<vscale x 16 x s8>) = COPY $v8m2
- G_STORE %1(<vscale x 16 x s8>), %0(p0) :: (store (<vscale x 16 x s8>) into %ir.pa)
+ G_STORE %1(<vscale x 16 x s8>), %0(p0) :: (store (<vscale x 16 x s8>))
PseudoRET
...
@@ -600,12 +757,27 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10, $v8m2
-
+
+ ; RV32I-LABEL: name: vstore_nx16i8_align64
+ ; RV32I: liveins: $x10, $v8m2
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v8m2
+ ; RV32I-NEXT: PseudoVSE8_V_M2 [[COPY1]], [[COPY]], -1, 3 /* e8 */ :: (store (<vscale x 16 x s8>), align 64)
+ ; RV32I-NEXT: PseudoRET
+ ;
+ ; RV64I-LABEL: name: vstore_nx16i8_align64
+ ; RV64I: liveins: $x10, $v8m2
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v8m2
+ ; RV64I-NEXT: PseudoVSE8_V_M2 [[COPY1]], [[COPY]], -1, 3 /* e8 */ :: (store (<vscale x 16 x s8>), align 64)
+ ; RV64I-NEXT: PseudoRET
%0:gprb(p0) = COPY $x10
%1:vrb(<vscale x 16 x s8>) = COPY $v8m2
- G_STORE %1(<vscale x 16 x s8>), %0(p0) :: (store (<vscale x 16 x s8>) into %ir.pa, align 64)
+ G_STORE %1(<vscale x 16 x s8>), %0(p0) :: (store (<vscale x 16 x s8>), align 64)
PseudoRET
...
@@ -615,13 +787,28 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $v8, $x10
-
+
+ ; RV32I-LABEL: name: vstore_nx4i16_align1
+ ; RV32I: liveins: $v8, $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8
+ ; RV32I-NEXT: PseudoVSE8_V_M1 [[COPY1]], [[COPY]], -1, 3 /* e8 */ :: (store (<vscale x 8 x s8>), align 1)
+ ; RV32I-NEXT: PseudoRET
+ ;
+ ; RV64I-LABEL: name: vstore_nx4i16_align1
+ ; RV64I: liveins: $v8, $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8
+ ; RV64I-NEXT: PseudoVSE8_V_M1 [[COPY1]], [[COPY]], -1, 3 /* e8 */ :: (store (<vscale x 8 x s8>), align 1)
+ ; RV64I-NEXT: PseudoRET
%0:gprb(p0) = COPY $x10
%1:vrb(<vscale x 4 x s16>) = COPY $v8
%2:vrb(<vscale x 8 x s8>) = G_BITCAST %1(<vscale x 4 x s16>)
- G_STORE %2(<vscale x 8 x s8>), %0(p0) :: (store (<vscale x 8 x s8>) into %ir.pa, align 1)
+ G_STORE %2(<vscale x 8 x s8>), %0(p0) :: (store (<vscale x 8 x s8>), align 1)
PseudoRET
...
@@ -631,12 +818,27 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $v8, $x10
-
+
+ ; RV32I-LABEL: name: vstore_nx4i16_align2
+ ; RV32I: liveins: $v8, $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8
+ ; RV32I-NEXT: PseudoVSE16_V_M1 [[COPY1]], [[COPY]], -1, 4 /* e16 */ :: (store (<vscale x 4 x s16>), align 2)
+ ; RV32I-NEXT: PseudoRET
+ ;
+ ; RV64I-LABEL: name: vstore_nx4i16_align2
+ ; RV64I: liveins: $v8, $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8
+ ; RV64I-NEXT: PseudoVSE16_V_M1 [[COPY1]], [[COPY]], -1, 4 /* e16 */ :: (store (<vscale x 4 x s16>), align 2)
+ ; RV64I-NEXT: PseudoRET
%0:gprb(p0) = COPY $x10
%1:vrb(<vscale x 4 x s16>) = COPY $v8
- G_STORE %1(<vscale x 4 x s16>), %0(p0) :: (store (<vscale x 4 x s16>) into %ir.pa, align 2)
+ G_STORE %1(<vscale x 4 x s16>), %0(p0) :: (store (<vscale x 4 x s16>), align 2)
PseudoRET
...
@@ -646,12 +848,27 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $v8, $x10
-
+
+ ; RV32I-LABEL: name: vstore_nx4i16_align4
+ ; RV32I: liveins: $v8, $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8
+ ; RV32I-NEXT: PseudoVSE16_V_M1 [[COPY1]], [[COPY]], -1, 4 /* e16 */ :: (store (<vscale x 4 x s16>), align 4)
+ ; RV32I-NEXT: PseudoRET
+ ;
+ ; RV64I-LABEL: name: vstore_nx4i16_align4
+ ; RV64I: liveins: $v8, $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8
+ ; RV64I-NEXT: PseudoVSE16_V_M1 [[COPY1]], [[COPY]], -1, 4 /* e16 */ :: (store (<vscale x 4 x s16>), align 4)
+ ; RV64I-NEXT: PseudoRET
%0:gprb(p0) = COPY $x10
%1:vrb(<vscale x 4 x s16>) = COPY $v8
- G_STORE %1(<vscale x 4 x s16>), %0(p0) :: (store (<vscale x 4 x s16>) into %ir.pa, align 4)
+ G_STORE %1(<vscale x 4 x s16>), %0(p0) :: (store (<vscale x 4 x s16>), align 4)
PseudoRET
...
@@ -661,12 +878,27 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $v8, $x10
-
+
+ ; RV32I-LABEL: name: vstore_nx4i16_align8
+ ; RV32I: liveins: $v8, $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8
+ ; RV32I-NEXT: PseudoVSE16_V_M1 [[COPY1]], [[COPY]], -1, 4 /* e16 */ :: (store (<vscale x 4 x s16>))
+ ; RV32I-NEXT: PseudoRET
+ ;
+ ; RV64I-LABEL: name: vstore_nx4i16_align8
+ ; RV64I: liveins: $v8, $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8
+ ; RV64I-NEXT: PseudoVSE16_V_M1 [[COPY1]], [[COPY]], -1, 4 /* e16 */ :: (store (<vscale x 4 x s16>))
+ ; RV64I-NEXT: PseudoRET
%0:gprb(p0) = COPY $x10
%1:vrb(<vscale x 4 x s16>) = COPY $v8
- G_STORE %1(<vscale x 4 x s16>), %0(p0) :: (store (<vscale x 4 x s16>) into %ir.pa)
+ G_STORE %1(<vscale x 4 x s16>), %0(p0) :: (store (<vscale x 4 x s16>))
PseudoRET
...
@@ -676,12 +908,27 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $v8, $x10
-
+
+ ; RV32I-LABEL: name: vstore_nx4i16_align16
+ ; RV32I: liveins: $v8, $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8
+ ; RV32I-NEXT: PseudoVSE16_V_M1 [[COPY1]], [[COPY]], -1, 4 /* e16 */ :: (store (<vscale x 4 x s16>), align 16)
+ ; RV32I-NEXT: PseudoRET
+ ;
+ ; RV64I-LABEL: name: vstore_nx4i16_align16
+ ; RV64I: liveins: $v8, $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8
+ ; RV64I-NEXT: PseudoVSE16_V_M1 [[COPY1]], [[COPY]], -1, 4 /* e16 */ :: (store (<vscale x 4 x s16>), align 16)
+ ; RV64I-NEXT: PseudoRET
%0:gprb(p0) = COPY $x10
%1:vrb(<vscale x 4 x s16>) = COPY $v8
- G_STORE %1(<vscale x 4 x s16>), %0(p0) :: (store (<vscale x 4 x s16>) into %ir.pa, align 16)
+ G_STORE %1(<vscale x 4 x s16>), %0(p0) :: (store (<vscale x 4 x s16>), align 16)
PseudoRET
...
@@ -691,13 +938,28 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $v8, $x10
-
+
+ ; RV32I-LABEL: name: vstore_nx2i32_align2
+ ; RV32I: liveins: $v8, $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8
+ ; RV32I-NEXT: PseudoVSE8_V_M1 [[COPY1]], [[COPY]], -1, 3 /* e8 */ :: (store (<vscale x 8 x s8>), align 2)
+ ; RV32I-NEXT: PseudoRET
+ ;
+ ; RV64I-LABEL: name: vstore_nx2i32_align2
+ ; RV64I: liveins: $v8, $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8
+ ; RV64I-NEXT: PseudoVSE8_V_M1 [[COPY1]], [[COPY]], -1, 3 /* e8 */ :: (store (<vscale x 8 x s8>), align 2)
+ ; RV64I-NEXT: PseudoRET
%0:gprb(p0) = COPY $x10
%1:vrb(<vscale x 2 x s32>) = COPY $v8
%2:vrb(<vscale x 8 x s8>) = G_BITCAST %1(<vscale x 2 x s32>)
- G_STORE %2(<vscale x 8 x s8>), %0(p0) :: (store (<vscale x 8 x s8>) into %ir.pa, align 2)
+ G_STORE %2(<vscale x 8 x s8>), %0(p0) :: (store (<vscale x 8 x s8>), align 2)
PseudoRET
...
@@ -707,12 +969,27 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $v8, $x10
-
+
+ ; RV32I-LABEL: name: vstore_nx2i32_align4
+ ; RV32I: liveins: $v8, $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8
+ ; RV32I-NEXT: PseudoVSE32_V_M1 [[COPY1]], [[COPY]], -1, 5 /* e32 */ :: (store (<vscale x 2 x s32>), align 4)
+ ; RV32I-NEXT: PseudoRET
+ ;
+ ; RV64I-LABEL: name: vstore_nx2i32_align4
+ ; RV64I: liveins: $v8, $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8
+ ; RV64I-NEXT: PseudoVSE32_V_M1 [[COPY1]], [[COPY]], -1, 5 /* e32 */ :: (store (<vscale x 2 x s32>), align 4)
+ ; RV64I-NEXT: PseudoRET
%0:gprb(p0) = COPY $x10
%1:vrb(<vscale x 2 x s32>) = COPY $v8
- G_STORE %1(<vscale x 2 x s32>), %0(p0) :: (store (<vscale x 2 x s32>) into %ir.pa, align 4)
+ G_STORE %1(<vscale x 2 x s32>), %0(p0) :: (store (<vscale x 2 x s32>), align 4)
PseudoRET
...
@@ -722,12 +999,27 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $v8, $x10
-
+
+ ; RV32I-LABEL: name: vstore_nx2i32_align8
+ ; RV32I: liveins: $v8, $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8
+ ; RV32I-NEXT: PseudoVSE32_V_M1 [[COPY1]], [[COPY]], -1, 5 /* e32 */ :: (store (<vscale x 2 x s32>))
+ ; RV32I-NEXT: PseudoRET
+ ;
+ ; RV64I-LABEL: name: vstore_nx2i32_align8
+ ; RV64I: liveins: $v8, $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8
+ ; RV64I-NEXT: PseudoVSE32_V_M1 [[COPY1]], [[COPY]], -1, 5 /* e32 */ :: (store (<vscale x 2 x s32>))
+ ; RV64I-NEXT: PseudoRET
%0:gprb(p0) = COPY $x10
%1:vrb(<vscale x 2 x s32>) = COPY $v8
- G_STORE %1(<vscale x 2 x s32>), %0(p0) :: (store (<vscale x 2 x s32>) into %ir.pa)
+ G_STORE %1(<vscale x 2 x s32>), %0(p0) :: (store (<vscale x 2 x s32>))
PseudoRET
...
@@ -737,12 +1029,27 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $v8, $x10
-
+
+ ; RV32I-LABEL: name: vstore_nx2i32_align16
+ ; RV32I: liveins: $v8, $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8
+ ; RV32I-NEXT: PseudoVSE32_V_M1 [[COPY1]], [[COPY]], -1, 5 /* e32 */ :: (store (<vscale x 2 x s32>), align 16)
+ ; RV32I-NEXT: PseudoRET
+ ;
+ ; RV64I-LABEL: name: vstore_nx2i32_align16
+ ; RV64I: liveins: $v8, $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8
+ ; RV64I-NEXT: PseudoVSE32_V_M1 [[COPY1]], [[COPY]], -1, 5 /* e32 */ :: (store (<vscale x 2 x s32>), align 16)
+ ; RV64I-NEXT: PseudoRET
%0:gprb(p0) = COPY $x10
%1:vrb(<vscale x 2 x s32>) = COPY $v8
- G_STORE %1(<vscale x 2 x s32>), %0(p0) :: (store (<vscale x 2 x s32>) into %ir.pa, align 16)
+ G_STORE %1(<vscale x 2 x s32>), %0(p0) :: (store (<vscale x 2 x s32>), align 16)
PseudoRET
...
@@ -752,12 +1059,27 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $v8, $x10
-
+
+ ; RV32I-LABEL: name: vstore_nx2i32_align256
+ ; RV32I: liveins: $v8, $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8
+ ; RV32I-NEXT: PseudoVSE32_V_M1 [[COPY1]], [[COPY]], -1, 5 /* e32 */ :: (store (<vscale x 2 x s32>), align 256)
+ ; RV32I-NEXT: PseudoRET
+ ;
+ ; RV64I-LABEL: name: vstore_nx2i32_align256
+ ; RV64I: liveins: $v8, $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8
+ ; RV64I-NEXT: PseudoVSE32_V_M1 [[COPY1]], [[COPY]], -1, 5 /* e32 */ :: (store (<vscale x 2 x s32>), align 256)
+ ; RV64I-NEXT: PseudoRET
%0:gprb(p0) = COPY $x10
%1:vrb(<vscale x 2 x s32>) = COPY $v8
- G_STORE %1(<vscale x 2 x s32>), %0(p0) :: (store (<vscale x 2 x s32>) into %ir.pa, align 256)
+ G_STORE %1(<vscale x 2 x s32>), %0(p0) :: (store (<vscale x 2 x s32>), align 256)
PseudoRET
...
@@ -767,13 +1089,28 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10, $v8m2
-
+
+ ; RV32I-LABEL: name: vstore_nx2i64_align4
+ ; RV32I: liveins: $x10, $v8m2
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v8m2
+ ; RV32I-NEXT: PseudoVSE8_V_M2 [[COPY1]], [[COPY]], -1, 3 /* e8 */ :: (store (<vscale x 16 x s8>), align 4)
+ ; RV32I-NEXT: PseudoRET
+ ;
+ ; RV64I-LABEL: name: vstore_nx2i64_align4
+ ; RV64I: liveins: $x10, $v8m2
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v8m2
+ ; RV64I-NEXT: PseudoVSE8_V_M2 [[COPY1]], [[COPY]], -1, 3 /* e8 */ :: (store (<vscale x 16 x s8>), align 4)
+ ; RV64I-NEXT: PseudoRET
%0:gprb(p0) = COPY $x10
%1:vrb(<vscale x 2 x s64>) = COPY $v8m2
%2:vrb(<vscale x 16 x s8>) = G_BITCAST %1(<vscale x 2 x s64>)
- G_STORE %2(<vscale x 16 x s8>), %0(p0) :: (store (<vscale x 16 x s8>) into %ir.pa, align 4)
+ G_STORE %2(<vscale x 16 x s8>), %0(p0) :: (store (<vscale x 16 x s8>), align 4)
PseudoRET
...
@@ -783,12 +1120,27 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10, $v8m2
-
+
+ ; RV32I-LABEL: name: vstore_nx2i64_align8
+ ; RV32I: liveins: $x10, $v8m2
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v8m2
+ ; RV32I-NEXT: PseudoVSE64_V_M2 [[COPY1]], [[COPY]], -1, 6 /* e64 */ :: (store (<vscale x 2 x s64>), align 8)
+ ; RV32I-NEXT: PseudoRET
+ ;
+ ; RV64I-LABEL: name: vstore_nx2i64_align8
+ ; RV64I: liveins: $x10, $v8m2
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v8m2
+ ; RV64I-NEXT: PseudoVSE64_V_M2 [[COPY1]], [[COPY]], -1, 6 /* e64 */ :: (store (<vscale x 2 x s64>), align 8)
+ ; RV64I-NEXT: PseudoRET
%0:gprb(p0) = COPY $x10
%1:vrb(<vscale x 2 x s64>) = COPY $v8m2
- G_STORE %1(<vscale x 2 x s64>), %0(p0) :: (store (<vscale x 2 x s64>) into %ir.pa, align 8)
+ G_STORE %1(<vscale x 2 x s64>), %0(p0) :: (store (<vscale x 2 x s64>), align 8)
PseudoRET
...
@@ -798,12 +1150,27 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10, $v8m2
-
+
+ ; RV32I-LABEL: name: vstore_nx2i64_align16
+ ; RV32I: liveins: $x10, $v8m2
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v8m2
+ ; RV32I-NEXT: PseudoVSE64_V_M2 [[COPY1]], [[COPY]], -1, 6 /* e64 */ :: (store (<vscale x 2 x s64>))
+ ; RV32I-NEXT: PseudoRET
+ ;
+ ; RV64I-LABEL: name: vstore_nx2i64_align16
+ ; RV64I: liveins: $x10, $v8m2
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v8m2
+ ; RV64I-NEXT: PseudoVSE64_V_M2 [[COPY1]], [[COPY]], -1, 6 /* e64 */ :: (store (<vscale x 2 x s64>))
+ ; RV64I-NEXT: PseudoRET
%0:gprb(p0) = COPY $x10
%1:vrb(<vscale x 2 x s64>) = COPY $v8m2
- G_STORE %1(<vscale x 2 x s64>), %0(p0) :: (store (<vscale x 2 x s64>) into %ir.pa)
+ G_STORE %1(<vscale x 2 x s64>), %0(p0) :: (store (<vscale x 2 x s64>))
PseudoRET
...
@@ -813,12 +1180,27 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10, $v8m2
-
+
+ ; RV32I-LABEL: name: vstore_nx2i64_align32
+ ; RV32I: liveins: $x10, $v8m2
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v8m2
+ ; RV32I-NEXT: PseudoVSE64_V_M2 [[COPY1]], [[COPY]], -1, 6 /* e64 */ :: (store (<vscale x 2 x s64>), align 32)
+ ; RV32I-NEXT: PseudoRET
+ ;
+ ; RV64I-LABEL: name: vstore_nx2i64_align32
+ ; RV64I: liveins: $x10, $v8m2
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v8m2
+ ; RV64I-NEXT: PseudoVSE64_V_M2 [[COPY1]], [[COPY]], -1, 6 /* e64 */ :: (store (<vscale x 2 x s64>), align 32)
+ ; RV64I-NEXT: PseudoRET
%0:gprb(p0) = COPY $x10
%1:vrb(<vscale x 2 x s64>) = COPY $v8m2
- G_STORE %1(<vscale x 2 x s64>), %0(p0) :: (store (<vscale x 2 x s64>) into %ir.pa, align 32)
+ G_STORE %1(<vscale x 2 x s64>), %0(p0) :: (store (<vscale x 2 x s64>), align 32)
PseudoRET
...
@@ -828,12 +1210,27 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $v8, $x10
-
+
+ ; RV32I-LABEL: name: vstore_nx1ptr
+ ; RV32I: liveins: $v8, $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8
+ ; RV32I-NEXT: PseudoVSE32_V_MF2 [[COPY1]], [[COPY]], -1, 5 /* e32 */ :: (store (<vscale x 1 x p0>))
+ ; RV32I-NEXT: PseudoRET
+ ;
+ ; RV64I-LABEL: name: vstore_nx1ptr
+ ; RV64I: liveins: $v8, $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8
+ ; RV64I-NEXT: PseudoVSE64_V_M1 [[COPY1]], [[COPY]], -1, 6 /* e64 */ :: (store (<vscale x 1 x p0>))
+ ; RV64I-NEXT: PseudoRET
%0:gprb(p0) = COPY $x10
%1:vrb(<vscale x 1 x p0>) = COPY $v8
- G_STORE %1(<vscale x 1 x p0>), %0(p0) :: (store (<vscale x 1 x p0>) into %ir.pa)
+ G_STORE %1(<vscale x 1 x p0>), %0(p0) :: (store (<vscale x 1 x p0>))
PseudoRET
...
@@ -843,12 +1240,27 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $v8, $x10
-
+
+ ; RV32I-LABEL: name: vstore_nx2ptr
+ ; RV32I: liveins: $v8, $x10
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8
+ ; RV32I-NEXT: PseudoVSE32_V_M1 [[COPY1]], [[COPY]], -1, 5 /* e32 */ :: (store (<vscale x 2 x p0>))
+ ; RV32I-NEXT: PseudoRET
+ ;
+ ; RV64I-LABEL: name: vstore_nx2ptr
+ ; RV64I: liveins: $v8, $x10
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v8
+ ; RV64I-NEXT: PseudoVSE64_V_M2 [[COPY1]], [[COPY]], -1, 6 /* e64 */ :: (store (<vscale x 2 x p0>))
+ ; RV64I-NEXT: PseudoRET
%0:gprb(p0) = COPY $x10
%1:vrb(<vscale x 2 x p0>) = COPY $v8
- G_STORE %1(<vscale x 2 x p0>), %0(p0) :: (store (<vscale x 2 x p0>) into %ir.pa)
+ G_STORE %1(<vscale x 2 x p0>), %0(p0) :: (store (<vscale x 2 x p0>))
PseudoRET
...
@@ -858,12 +1270,27 @@ legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
- bb.1 (%ir-block.0):
+ bb.1:
liveins: $x10, $v8m4
-
+
+ ; RV32I-LABEL: name: vstore_nx8ptr
+ ; RV32I: liveins: $x10, $v8m4
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY $v8m4
+ ; RV32I-NEXT: PseudoVSE32_V_M4 [[COPY1]], [[COPY]], -1, 5 /* e32 */ :: (store (<vscale x 8 x p0>))
+ ; RV32I-NEXT: PseudoRET
+ ;
+ ; RV64I-LABEL: name: vstore_nx8ptr
+ ; RV64I: liveins: $x10, $v8m4
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY $v8m4
+ ; RV64I-NEXT: PseudoVSE64_V_M8 [[COPY1]], [[COPY]], -1, 6 /* e64 */ :: (store (<vscale x 8 x p0>))
+ ; RV64I-NEXT: PseudoRET
%0:gprb(p0) = COPY $x10
%1:vrb(<vscale x 8 x p0>) = COPY $v8m4
- G_STORE %1(<vscale x 8 x p0>), %0(p0) :: (store (<vscale x 8 x p0>) into %ir.pa)
+ G_STORE %1(<vscale x 8 x p0>), %0(p0) :: (store (<vscale x 8 x p0>))
PseudoRET
...
>From 057c06a585b528be37b735feac47e73e8cda1389 Mon Sep 17 00:00:00 2001
From: Jiahan Xie <jx353 at cornell.edu>
Date: Tue, 24 Sep 2024 09:07:52 -0400
Subject: [PATCH 5/5] use replacePtrWithInt for G_LOAD
---
.../RISCV/GISel/RISCVInstructionSelector.cpp | 35 ++++++++++++-------
1 file changed, 23 insertions(+), 12 deletions(-)
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 1b55d03947d31b..78fffa5047df7f 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -758,13 +758,21 @@ bool RISCVInstructionSelector::replacePtrWithInt(MachineOperand &Op,
MachineIRBuilder &MIB,
MachineRegisterInfo &MRI) {
Register PtrReg = Op.getReg();
- assert(MRI.getType(PtrReg).isPointer() && "Operand is not a pointer!");
-
+ const LLT PtrTy = MRI.getType(PtrReg);
const LLT sXLen = LLT::scalar(STI.getXLen());
- auto PtrToInt = MIB.buildPtrToInt(sXLen, PtrReg);
- MRI.setRegBank(PtrToInt.getReg(0), RBI.getRegBank(RISCV::GPRBRegBankID));
- Op.setReg(PtrToInt.getReg(0));
- return select(*PtrToInt);
+ if (PtrTy.isPointer()) {
+ auto PtrToInt = MIB.buildPtrToInt(sXLen, PtrReg);
+ MRI.setRegBank(PtrToInt.getReg(0), RBI.getRegBank(RISCV::GPRBRegBankID));
+ Op.setReg(PtrToInt.getReg(0));
+ return select(*PtrToInt);
+ }
+ assert(PtrTy.isPointerVector() &&
+ "Operand must be a pointer of a vector of pointers");
+ assert(PtrTy.isScalableVector() &&
+ "Currently only working for scalable vector of pointers now");
+ MRI.setType(PtrReg, LLT::scalable_vector(
+ PtrTy.getElementCount().getKnownMinValue(), sXLen));
+ return true;
}
void RISCVInstructionSelector::preISelLower(MachineInstr &MI,
@@ -791,17 +799,20 @@ void RISCVInstructionSelector::preISelLower(MachineInstr &MI,
case TargetOpcode::G_LOAD: {
Register DstReg = MI.getOperand(0).getReg();
const LLT DstTy = MRI.getType(DstReg);
- if (!(DstTy.isVector() && DstTy.getElementType().isPointer()))
- break;
- const LLT sXLen = LLT::scalar(STI.getXLen());
- MRI.setType(DstReg, LLT::scalable_vector(DstTy.getElementCount().getKnownMinValue(), sXLen));
+ if (!DstTy.isPointerVector() &&
+ "Destination register that's not a vector of pointers doesn't need to "
+ "go through preISelLower")
+ break;
+ replacePtrWithInt(MI.getOperand(0), MIB, MRI);
break;
}
case TargetOpcode::G_STORE: {
MachineOperand &SrcOp = MI.getOperand(0);
const LLT SrcTy = MRI.getType(SrcOp.getReg());
- if (!(SrcTy.isVector() && SrcTy.getElementType().isPointer()))
- break;
+ if (!SrcTy.isPointerVector() &&
+ "Source register that's not a vector of pointers doesn't need to go "
+ "through preISelLower")
+ break;
const LLT sXLen = LLT::scalar(STI.getXLen());
auto Copy = MIB.buildCopy(LLT::scalable_vector(SrcTy.getElementCount().getKnownMinValue(), sXLen), SrcOp);
Register NewSrc = Copy.getReg(0);
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