[llvm] c30fa3c - [AMDGPU] Fix has_single_bit assertion for Mask in SIInstrInfo (#109785)

[via llvm-commits]

Author: Georgi Mirazchiyski
Date: 2024-09-24T15:54:05+04:00
New Revision: c30fa3cde755e7519f0962f581868a09da1ea130

URL: https://github.com/llvm/llvm-project/commit/c30fa3cde755e7519f0962f581868a09da1ea130
DIFF: https://github.com/llvm/llvm-project/commit/c30fa3cde755e7519f0962f581868a09da1ea130.diff

LOG: [AMDGPU] Fix has_single_bit assertion for Mask in SIInstrInfo (#109785)

Convert the `int64_t` Mask to `uint64_t` for `llvm::has_single_bit` to
compile.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index f5f367b2a4a7c6..9ad0b4c65e1d90 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -9793,7 +9793,7 @@ bool SIInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
 
     // A valid Mask is required to have a single bit set, hence a non-zero and
     // power-of-two value. This verifies that we will not do 64-bit shift below.
-    assert(llvm::has_single_bit(Mask) && "Invalid mask.");
+    assert(llvm::has_single_bit<uint64_t>(Mask) && "Invalid mask.");
     unsigned BitNo = llvm::countr_zero((uint64_t)Mask);
     if (IsSigned && BitNo == SrcSize - 1)
       return false;