[llvm] [WIP] [CodeGen] Enable TrapUnreachable by default for all targets. (PR #109732)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 24 04:36:18 PDT 2024
https://github.com/duk-37 updated https://github.com/llvm/llvm-project/pull/109732
>From 5ce7a94ede6c271c586a2510f17fe7705d5ab42c Mon Sep 17 00:00:00 2001
From: duk <37 at cmail.nu>
Date: Tue, 24 Sep 2024 07:35:50 -0400
Subject: [PATCH] [WIP] [CodeGen] Enable TrapUnreachable by default for all
targets.
---
llvm/include/llvm/Target/TargetOptions.h | 2 +-
llvm/lib/CodeGen/LLVMTargetMachine.cpp | 21 +--
.../Target/AArch64/AArch64TargetMachine.cpp | 6 +-
.../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 6 +
llvm/lib/Target/ARM/ARMTargetMachine.cpp | 5 -
llvm/lib/Target/BPF/BPFTargetMachine.cpp | 8 ++
.../Target/Hexagon/HexagonTargetMachine.cpp | 7 +
llvm/lib/Target/X86/X86TargetMachine.cpp | 7 +-
.../GlobalISel/arm64-irtranslator-switch.ll | 16 +++
.../AArch64/GlobalISel/arm64-irtranslator.ll | 3 +-
.../CodeGen/AArch64/arm64-big-endian-eh.ll | 2 +-
llvm/test/CodeGen/AArch64/ptrauth-invoke.ll | 1 +
.../CodeGen/ARM/ifcvt-branch-weight-bug.ll | 2 +-
.../test/CodeGen/ARM/machine-sink-multidef.ll | 3 +-
llvm/test/CodeGen/ARM/sub-cmp-peephole.ll | 10 +-
llvm/test/CodeGen/ARM/trap-unreachable.ll | 2 +-
.../ARM/v8m.base-jumptable_alignment.ll | 13 +-
llvm/test/CodeGen/ARM/vcge.ll | 1 +
llvm/test/CodeGen/ARM/vector-DAGCombine.ll | 2 +
llvm/test/CodeGen/ARM/vmov.ll | 2 +
llvm/test/CodeGen/ARM/vmul.ll | 3 +
llvm/test/CodeGen/Lanai/sub-cmp-peephole.ll | 4 +-
llvm/test/CodeGen/LoongArch/double-br-fcmp.ll | 56 ++++++++
llvm/test/CodeGen/LoongArch/float-br-fcmp.ll | 56 ++++++++
llvm/test/CodeGen/LoongArch/shrinkwrap.ll | 9 +-
llvm/test/CodeGen/Mips/insn-zero-size-bb.ll | 6 +-
.../Mips/micromips-gcc-except-table.ll | 2 +-
llvm/test/CodeGen/PowerPC/aix-vsx-splatimm.ll | 2 +
.../PowerPC/canonical-merge-shuffles.ll | 7 +
llvm/test/CodeGen/PowerPC/empty-functions.ll | 4 +-
.../CodeGen/PowerPC/expand-contiguous-isel.ll | 4 +
llvm/test/CodeGen/PowerPC/fptoui-be-crash.ll | 2 +
.../PowerPC/ifcvt-forked-bug-2016-08-08.ll | 15 +-
llvm/test/CodeGen/PowerPC/p10-spill-crlt.ll | 42 ++----
llvm/test/CodeGen/PowerPC/pr43527.ll | 4 +-
llvm/test/CodeGen/PowerPC/pr45448.ll | 17 +--
.../CodeGen/PowerPC/reduce_scalarization.ll | 20 ++-
.../PowerPC/redundant-copy-after-tail-dup.ll | 1 +
.../PowerPC/remove-redundant-load-imm.ll | 1 +
llvm/test/CodeGen/PowerPC/subreg-postra-2.ll | 19 ++-
llvm/test/CodeGen/PowerPC/subreg-postra.ll | 130 +++++++-----------
.../CodeGen/PowerPC/test-and-cmp-folding.ll | 58 ++------
llvm/test/CodeGen/PowerPC/trunc-srl-load.ll | 10 +-
llvm/test/CodeGen/RISCV/branch_zero.ll | 12 +-
.../CodeGen/RISCV/double-previous-failure.ll | 5 +-
.../CodeGen/RISCV/machine-outliner-throw.ll | 2 +
llvm/test/CodeGen/RISCV/miss-sp-restore-eh.ll | 1 +
.../test/CodeGen/RISCV/overflow-intrinsics.ll | 4 +
llvm/test/CodeGen/SPARC/empty-functions.ll | 4 +-
llvm/test/CodeGen/SPARC/missinglabel.ll | 6 +-
llvm/test/CodeGen/SystemZ/buildvector-00.ll | 3 +-
llvm/test/CodeGen/SystemZ/knownbits.ll | 13 +-
llvm/test/CodeGen/SystemZ/pr47019.ll | 2 +
llvm/test/CodeGen/SystemZ/soft-float-04.ll | 6 +-
llvm/test/CodeGen/SystemZ/vec-perm-14.ll | 12 +-
llvm/test/CodeGen/VE/Vector/ticket-64420.ll | 13 +-
.../CodeGen/WinEH/wineh-empty-seh-scope.ll | 2 +-
.../test/CodeGen/WinEH/wineh-noret-cleanup.ll | 6 +-
.../CodeGen/X86/2008-05-21-CoalescerBug.ll | 1 +
.../test/CodeGen/X86/2008-06-25-VecISelBug.ll | 1 +
.../CodeGen/X86/2010-02-23-DAGCombineBug.ll | 1 +
llvm/test/CodeGen/X86/PR40322.ll | 11 +-
llvm/test/CodeGen/X86/atomic-bit-test.ll | 2 +
llvm/test/CodeGen/X86/avx-load-store.ll | 37 +++--
...basic-block-sections-labels-empty-block.ll | 2 +-
...ic-block-sections-labels-empty-function.ll | 5 +-
llvm/test/CodeGen/X86/br-fold.ll | 8 +-
...d-implicit-def-subreg-to-reg-regression.ll | 1 +
.../test/CodeGen/X86/combine-concatvectors.ll | 1 +
.../CodeGen/X86/combineIncDecVector-crash.ll | 1 +
llvm/test/CodeGen/X86/concat-fpext-v2bf16.ll | 1 +
llvm/test/CodeGen/X86/empty-function.ll | 6 +-
llvm/test/CodeGen/X86/empty-functions.ll | 4 +-
llvm/test/CodeGen/X86/extract-combine.ll | 1 +
.../test/CodeGen/X86/gc-empty-basic-blocks.ll | 2 +-
...iller-impdef-on-implicit-def-regression.ll | 16 ++-
llvm/test/CodeGen/X86/jump_sign.ll | 29 ++--
llvm/test/CodeGen/X86/machine-cse.ll | 2 +
llvm/test/CodeGen/X86/nomerge.ll | 6 +
llvm/test/CodeGen/X86/noreturn-call-win64.ll | 2 +-
llvm/test/CodeGen/X86/noreturn-call.ll | 3 +-
.../CodeGen/X86/overflowing-iv-codegen.ll | 7 +-
llvm/test/CodeGen/X86/patchable-prologue.ll | 12 +-
llvm/test/CodeGen/X86/pr24374.ll | 2 +-
llvm/test/CodeGen/X86/pr32484.ll | 3 +-
llvm/test/CodeGen/X86/pr3366.ll | 3 +-
llvm/test/CodeGen/X86/pr49451.ll | 16 +--
llvm/test/CodeGen/X86/pr56103.ll | 7 +-
llvm/test/CodeGen/X86/shift-combine.ll | 14 +-
llvm/test/CodeGen/X86/stack-coloring-wineh.ll | 3 +-
.../CodeGen/X86/stack-protector-no-return.ll | 2 +
.../CodeGen/X86/statepoint-vreg-invoke.ll | 1 +
llvm/test/CodeGen/X86/switch-bt.ll | 3 +
llvm/test/CodeGen/X86/switch.ll | 11 +-
.../X86/tail-dup-merge-loop-headers.ll | 7 +-
.../CodeGen/X86/tail-merge-unreachable.ll | 2 +-
llvm/test/CodeGen/X86/tail-opts.ll | 8 ++
llvm/test/CodeGen/X86/trap.ll | 2 +-
llvm/test/CodeGen/X86/unreachable-trap.ll | 15 +-
.../test/CodeGen/X86/unreachable-ubsantrap.ll | 21 +--
llvm/test/CodeGen/X86/win64-eh-empty-block.ll | 2 +-
.../X86/win64-eh-trailing-statepoint.ll | 2 +-
llvm/test/CodeGen/X86/wineh-coreclr.ll | 8 +-
.../CodeGen/X86/x86-shrink-wrap-unwind.ll | 1 +
llvm/test/DebugInfo/Mips/eh_frame.ll | 4 +-
105 files changed, 584 insertions(+), 397 deletions(-)
diff --git a/llvm/include/llvm/Target/TargetOptions.h b/llvm/include/llvm/Target/TargetOptions.h
index 94e0fa2404d6fc..45b3367f76b0c4 100644
--- a/llvm/include/llvm/Target/TargetOptions.h
+++ b/llvm/include/llvm/Target/TargetOptions.h
@@ -145,7 +145,7 @@ namespace llvm {
DataSections(false), IgnoreXCOFFVisibility(false),
XCOFFTracebackTable(true), UniqueSectionNames(true),
UniqueBasicBlockSectionNames(false), SeparateNamedSections(false),
- TrapUnreachable(false), NoTrapAfterNoreturn(false), TLSSize(0),
+ TrapUnreachable(true), NoTrapAfterNoreturn(true), TLSSize(0),
EmulatedTLS(false), EnableTLSDESC(false), EnableIPRA(false),
EmitStackSizeSection(false), EnableMachineOutliner(false),
EnableMachineFunctionSplitter(false), SupportsDefaultOutlining(false),
diff --git a/llvm/lib/CodeGen/LLVMTargetMachine.cpp b/llvm/lib/CodeGen/LLVMTargetMachine.cpp
index 4ff22057b290f5..8fcd5594f9a19d 100644
--- a/llvm/lib/CodeGen/LLVMTargetMachine.cpp
+++ b/llvm/lib/CodeGen/LLVMTargetMachine.cpp
@@ -33,11 +33,11 @@
#include "llvm/Target/TargetOptions.h"
using namespace llvm;
-static cl::opt<bool>
- EnableTrapUnreachable("trap-unreachable", cl::Hidden,
- cl::desc("Enable generating trap for unreachable"));
+cl::opt<bool> EnableTrapUnreachable(
+ "trap-unreachable", cl::Hidden,
+ cl::desc("Enable generating trap for unreachable"));
-static cl::opt<bool> EnableNoTrapAfterNoreturn(
+cl::opt<bool> EnableNoTrapAfterNoreturn(
"no-trap-after-noreturn", cl::Hidden,
cl::desc("Do not emit a trap instruction for 'unreachable' IR instructions "
"after noreturn calls, even if --trap-unreachable is set."));
@@ -96,10 +96,15 @@ LLVMTargetMachine::LLVMTargetMachine(const Target &T,
this->CMModel = CM;
this->OptLevel = OL;
- if (EnableTrapUnreachable)
- this->Options.TrapUnreachable = true;
- if (EnableNoTrapAfterNoreturn)
- this->Options.NoTrapAfterNoreturn = true;
+ if (EnableTrapUnreachable.getNumOccurrences())
+ this->Options.TrapUnreachable = EnableTrapUnreachable;
+
+ if (EnableNoTrapAfterNoreturn.getNumOccurrences())
+ this->Options.NoTrapAfterNoreturn = EnableNoTrapAfterNoreturn;
+
+ // Keep all traps in debug environments.
+ else if (OL == CodeGenOptLevel::None)
+ this->Options.NoTrapAfterNoreturn = false;
}
TargetTransformInfo
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
index 9f96f6c5e83ec4..121f5b83e7e0bb 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -360,11 +360,6 @@ AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT,
TLOF(createTLOF(getTargetTriple())), isLittle(LittleEndian) {
initAsmInfo();
- if (TT.isOSBinFormatMachO()) {
- this->Options.TrapUnreachable = true;
- this->Options.NoTrapAfterNoreturn = true;
- }
-
if (getMCAsmInfo()->usesWindowsCFI()) {
// Unwinding can get confused if the last instruction in an
// exception-handling region (function, funclet, try block, etc.)
@@ -373,6 +368,7 @@ AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT,
// FIXME: We could elide the trap if the next instruction would be in
// the same region anyway.
this->Options.TrapUnreachable = true;
+ this->Options.NoTrapAfterNoreturn = false;
}
if (this->Options.TLSSize == 0) // default
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 04fdee0819b502..a2c5de816dc0f1 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -396,6 +396,8 @@ static cl::opt<bool>
cl::desc("Enable AMDGPUAttributorPass"),
cl::init(true), cl::Hidden);
+extern cl::opt<bool> EnableTrapUnreachable;
+
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
// Register the target
RegisterTargetMachine<R600TargetMachine> X(getTheR600Target());
@@ -612,6 +614,10 @@ AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
FS, Options, getEffectiveRelocModel(RM),
getEffectiveCodeModel(CM, CodeModel::Small), OptLevel),
TLOF(createTLOF(getTargetTriple())) {
+ // FIXME: There are some scenarios where targets may not have hardware traps,
+ // and external calls to `abort` also fail. For now, do a blanket-disable.
+ if (!EnableTrapUnreachable.getNumOccurrences())
+ this->Options.TrapUnreachable = false;
initAsmInfo();
if (TT.getArch() == Triple::amdgcn) {
if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize64"))
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
index 7553778c574033..69617fe8e90630 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
@@ -251,11 +251,6 @@ ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT,
this->Options.EABIVersion = EABI::EABI5;
}
- if (TT.isOSBinFormatMachO()) {
- this->Options.TrapUnreachable = true;
- this->Options.NoTrapAfterNoreturn = true;
- }
-
// ARM supports the debug entry values.
setSupportsDebugEntryValues(true);
diff --git a/llvm/lib/Target/BPF/BPFTargetMachine.cpp b/llvm/lib/Target/BPF/BPFTargetMachine.cpp
index 7d91fa8bb824cf..0f7d2376d7ae0b 100644
--- a/llvm/lib/Target/BPF/BPFTargetMachine.cpp
+++ b/llvm/lib/Target/BPF/BPFTargetMachine.cpp
@@ -34,6 +34,8 @@
#include <optional>
using namespace llvm;
+extern cl::opt<bool> EnableTrapUnreachable;
+
static cl::
opt<bool> DisableMIPeephole("disable-bpf-peephole", cl::Hidden,
cl::desc("Disable machine peepholes for BPF"));
@@ -74,6 +76,12 @@ BPFTargetMachine::BPFTargetMachine(const Target &T, const Triple &TT,
getEffectiveCodeModel(CM, CodeModel::Small), OL),
TLOF(std::make_unique<TargetLoweringObjectFileELF>()),
Subtarget(TT, std::string(CPU), std::string(FS), *this) {
+ // FIXME: If the user has not explicitly enabled TrapUnreachable,
+ // disable it. We do not have an explicit trap opcode and external calls
+ // to abort are a no-no.
+ if (!EnableTrapUnreachable.getNumOccurrences())
+ this->Options.TrapUnreachable = false;
+
initAsmInfo();
BPFMCAsmInfo *MAI =
diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
index 803b9b81045c63..3e1035c30de2cf 100644
--- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
@@ -146,6 +146,8 @@ static cl::opt<bool> EnableInstSimplify("hexagon-instsimplify", cl::Hidden,
cl::init(true),
cl::desc("Enable instsimplify"));
+extern cl::opt<bool> EnableTrapUnreachable;
+
/// HexagonTargetMachineModule - Note that this is used on hosts that
/// cannot link in a library unless there are references into the
/// library. In particular, it seems that it is not possible to get
@@ -284,6 +286,11 @@ HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
(HexagonNoOpt ? CodeGenOptLevel::None : OL)),
TLOF(std::make_unique<HexagonTargetObjectFile>()),
Subtarget(Triple(TT), CPU, FS, *this) {
+ // FIXME: If the user has not explicitly enabled TrapUnreachable,
+ // disable it. We currently seem to have problems with EH_RETURN lowering.
+ if (!EnableTrapUnreachable.getNumOccurrences())
+ this->Options.TrapUnreachable = false;
+
initializeHexagonCopyHoistingPass(*PassRegistry::getPassRegistry());
initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
initializeHexagonLoopAlignPass(*PassRegistry::getPassRegistry());
diff --git a/llvm/lib/Target/X86/X86TargetMachine.cpp b/llvm/lib/Target/X86/X86TargetMachine.cpp
index fc2a1e34b711ef..d79b3c636517a8 100644
--- a/llvm/lib/Target/X86/X86TargetMachine.cpp
+++ b/llvm/lib/Target/X86/X86TargetMachine.cpp
@@ -242,10 +242,11 @@ X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT,
OL),
TLOF(createTLOF(getTargetTriple())), IsJIT(JIT) {
// On PS4/PS5, the "return address" of a 'noreturn' call must still be within
- // the calling function, and TrapUnreachable is an easy way to get that.
- if (TT.isPS() || TT.isOSBinFormatMachO()) {
+ // the calling function, and unsetting NoTrapAfterNoreturn
+ // is an easy way to get that.
+ if (TT.isPS()) {
this->Options.TrapUnreachable = true;
- this->Options.NoTrapAfterNoreturn = TT.isOSBinFormatMachO();
+ this->Options.NoTrapAfterNoreturn = false;
}
setMachineOutliner(true);
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll
index 3b12885923db65..b56cdf33dc97d6 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll
@@ -137,6 +137,8 @@ define i32 @test_cfg_remap_multiple_preds(i32 %in) {
; CHECK-NEXT: bb.2.odd:
; CHECK-NEXT: successors:
; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: G_TRAP
+ ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.next:
; CHECK-NEXT: G_BR %bb.5
; CHECK-NEXT: {{ $}}
@@ -1147,18 +1149,28 @@ define void @jt_2_tables_phi_edge_from_second() {
; CHECK-NEXT: bb.2.if.then:
; CHECK-NEXT: successors:
; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: G_TRAP
+ ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.sw.bb2.i41:
; CHECK-NEXT: successors:
; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: G_TRAP
+ ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4.sw.bb7.i44:
; CHECK-NEXT: successors:
; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: G_TRAP
+ ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.5.sw.bb8.i45:
; CHECK-NEXT: successors:
; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: G_TRAP
+ ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.6.sw.bb13.i47:
; CHECK-NEXT: successors:
; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: G_TRAP
+ ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.7.sw.bb14.i48:
; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[DEF1]](s32), [[C5]]
; CHECK-NEXT: G_BRCOND [[ICMP5]](s1), %bb.10
@@ -1202,6 +1214,8 @@ define void @jt_2_tables_phi_edge_from_second() {
; CHECK-NEXT: bb.8.sw.default.i49:
; CHECK-NEXT: successors:
; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: G_TRAP
+ ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.9.sw.bb1.i:
; CHECK-NEXT: G_BR %bb.16
; CHECK-NEXT: {{ $}}
@@ -1234,6 +1248,7 @@ define void @jt_2_tables_phi_edge_from_second() {
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: BL @jt_2_tables_phi_edge_from_second, csr_aarch64_aapcs, implicit-def $lr, implicit $sp
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK-NEXT: G_TRAP
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.18.while.end:
; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI [[C21]](s32), %bb.30, [[PHI]](s32), %bb.16
@@ -1460,6 +1475,7 @@ define i1 @i1_value_cmp_is_signed(i1) {
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: BL @bar, csr_aarch64_aapcs, implicit-def $lr, implicit $sp
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK-NEXT: G_TRAP
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.OkValue:
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s8) = G_ZEXT [[TRUNC1]](s1)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
index 314c5458e30909..c4cfdb8a2d1d1d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
@@ -431,8 +431,7 @@ end:
; CHECK-LABEL: name: unreachable
; CHECK: G_ADD
-; CHECK-NEXT: {{^$}}
-; CHECK-NEXT: ...
+; CHECK-NEXT: G_TRAP
define void @unreachable(i32 %a) {
%sum = add i32 %a, %a
unreachable
diff --git a/llvm/test/CodeGen/AArch64/arm64-big-endian-eh.ll b/llvm/test/CodeGen/AArch64/arm64-big-endian-eh.ll
index 6c54cec24ac540..4b614db020003f 100644
--- a/llvm/test/CodeGen/AArch64/arm64-big-endian-eh.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-big-endian-eh.ll
@@ -71,6 +71,6 @@ declare void @_ZSt9terminatev()
; CHECK-LABEL: Contents of section .eh_frame:
; CHECK-NEXT: {{^ 0000}}
; CHECK-NEXT: {{^ 0010}}
-; CHECK-NEXT: 0020 0000000c 00440e10 9e040000 0000001c .....D..........
+; CHECK-NEXT: 0020 00000010 00440e10 9e040000 0000001c .....D..........
; CHECK-NEXT: 0030 00000000 017a504c 5200017c 1e0b9c00 .....zPLR..|....
diff --git a/llvm/test/CodeGen/AArch64/ptrauth-invoke.ll b/llvm/test/CodeGen/AArch64/ptrauth-invoke.ll
index f6b3a88ca46779..9b639268d84fa8 100644
--- a/llvm/test/CodeGen/AArch64/ptrauth-invoke.ll
+++ b/llvm/test/CodeGen/AArch64/ptrauth-invoke.ll
@@ -173,6 +173,7 @@ continuebb:
; ELF-NEXT: blrab x19, x17
; ELF-NEXT: [[POSTCALL:.L.*]]:
; ELF-NEXT: // %bb.1:
+; ELF-NEXT: brk #0x1
; ELF-NEXT: [[LPADBB:.LBB[0-9_]+]]:
; ELF-NEXT: [[LPAD:.L.*]]:
; ELF-NEXT: mov x19, x1
diff --git a/llvm/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll b/llvm/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll
index d4dc75a8f8bce0..90c708ea47288e 100644
--- a/llvm/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll
+++ b/llvm/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll
@@ -22,7 +22,7 @@ entry:
; for.body -> for.cond.backedge (100%)
; -> cond.false.i (0%)
; CHECK: bb.1.for.body:
-; CHECK: successors: %bb.2(0x80000000), %bb.5(0x00000000)
+; CHECK: successors: %bb.2(0x80000000), %bb.4(0x00000000)
for.body:
br i1 undef, label %for.cond.backedge, label %lor.lhs.false.i, !prof !1
diff --git a/llvm/test/CodeGen/ARM/machine-sink-multidef.ll b/llvm/test/CodeGen/ARM/machine-sink-multidef.ll
index cc10bfd8bf90eb..8dc574b3c2ce0e 100644
--- a/llvm/test/CodeGen/ARM/machine-sink-multidef.ll
+++ b/llvm/test/CodeGen/ARM/machine-sink-multidef.ll
@@ -23,7 +23,8 @@ define arm_aapcscc void @g() {
; CHECK-NEXT: push {r11, lr}
; CHECK-NEXT: ldr r1, [r1, #4]
; CHECK-NEXT: bl k
-; CHECK-NEXT: .p2align 2
+; CHECK-NEXT: .inst 0xe7ffdefe
+; CHECK-NEXT: .p2align 2 @ trap
; CHECK-NEXT: @ %bb.2:
; CHECK-NEXT: .LCPI0_0:
; CHECK-NEXT: .long f
diff --git a/llvm/test/CodeGen/ARM/sub-cmp-peephole.ll b/llvm/test/CodeGen/ARM/sub-cmp-peephole.ll
index 046bbbde686426..d67c37dafda0b8 100644
--- a/llvm/test/CodeGen/ARM/sub-cmp-peephole.ll
+++ b/llvm/test/CodeGen/ARM/sub-cmp-peephole.ll
@@ -270,8 +270,11 @@ define i32 @cmp_slt0(i32 %a, i32 %b, i32 %x, i32 %y) {
; CHECK-NEXT: @ %bb.1: @ %if.else
; CHECK-NEXT: mov r0, #0
; CHECK-NEXT: bl exit
-; CHECK-NEXT: .LBB11_2: @ %if.then
+; CHECK-NEXT: .inst 0xe7ffdefe
+; CHECK-NEXT: .LBB11_2: @ trap
+; CHECK-NEXT: @ %if.then
; CHECK-NEXT: bl abort
+; CHECK-NEXT: .inst 0xe7ffdefe
entry:
%load = load i32, ptr @t, align 4
%sub = sub i32 %load, 17
@@ -302,9 +305,12 @@ define i32 @cmp_ult0(i32 %a, i32 %b, i32 %x, i32 %y) {
; CHECK-NEXT: bhs .LBB12_2
; CHECK-NEXT: @ %bb.1: @ %if.then
; CHECK-NEXT: bl abort
-; CHECK-NEXT: .LBB12_2: @ %if.else
+; CHECK-NEXT: .inst 0xe7ffdefe
+; CHECK-NEXT: .LBB12_2: @ trap
+; CHECK-NEXT: @ %if.else
; CHECK-NEXT: mov r0, #0
; CHECK-NEXT: bl exit
+; CHECK-NEXT: .inst 0xe7ffdefe
entry:
%load = load i32, ptr @t, align 4
%sub = sub i32 %load, 17
diff --git a/llvm/test/CodeGen/ARM/trap-unreachable.ll b/llvm/test/CodeGen/ARM/trap-unreachable.ll
index 84dbb04c462b45..94d2a2e6333d7b 100644
--- a/llvm/test/CodeGen/ARM/trap-unreachable.ll
+++ b/llvm/test/CodeGen/ARM/trap-unreachable.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=thumbv7 -trap-unreachable < %s | FileCheck %s --check-prefixes CHECK,TRAP_UNREACHABLE
+; RUN: llc -mtriple=thumbv7 -trap-unreachable -no-trap-after-noreturn=false < %s | FileCheck %s --check-prefixes CHECK,TRAP_UNREACHABLE
; RUN: llc -mtriple=thumbv7 -trap-unreachable -no-trap-after-noreturn < %s | FileCheck %s --check-prefixes CHECK,NTANR
define void @test_trap_unreachable() #0 {
diff --git a/llvm/test/CodeGen/ARM/v8m.base-jumptable_alignment.ll b/llvm/test/CodeGen/ARM/v8m.base-jumptable_alignment.ll
index c3024f46dfe700..35d8c71b5eaeb0 100644
--- a/llvm/test/CodeGen/ARM/v8m.base-jumptable_alignment.ll
+++ b/llvm/test/CodeGen/ARM/v8m.base-jumptable_alignment.ll
@@ -18,9 +18,9 @@ define void @main() {
; CHECK-NEXT: ldr r0, [r0]
; CHECK-NEXT: movs r0, #0
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: beq .LBB0_7
+; CHECK-NEXT: beq .LBB0_6
; CHECK-NEXT: @ %bb.1: @ %for.cond7.preheader.i.lr.ph.i.i
-; CHECK-NEXT: bne .LBB0_7
+; CHECK-NEXT: bne .LBB0_6
; CHECK-NEXT: .LBB0_2: @ %for.cond14.preheader.us.i.i.i
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: cbnz r0, .LBB0_6
@@ -35,8 +35,8 @@ define void @main() {
; CHECK-NEXT: .LJTI0_0:
; CHECK-NEXT: b.w .LBB0_5
; CHECK-NEXT: b.w .LBB0_6
-; CHECK-NEXT: b.w .LBB0_8
-; CHECK-NEXT: b.w .LBB0_7
+; CHECK-NEXT: b.w .LBB0_6
+; CHECK-NEXT: b.w .LBB0_6
; CHECK-NEXT: b.w .LBB0_6
; CHECK-NEXT: b.w .LBB0_6
; CHECK-NEXT: b.w .LBB0_6
@@ -48,9 +48,8 @@ define void @main() {
; CHECK-NEXT: .LBB0_5: @ %for.cond14.preheader.us.i.i.i
; CHECK-NEXT: @ in Loop: Header=BB0_2 Depth=1
; CHECK-NEXT: b .LBB0_2
-; CHECK-NEXT: .LBB0_6: @ %func_1.exit.loopexit
-; CHECK-NEXT: .LBB0_7: @ %for.end476.i.i.i.loopexit
-; CHECK-NEXT: .LBB0_8: @ %lbl_1394.i.i.i.loopexit
+; CHECK-NEXT: .LBB0_6: @ %lbl_1394.i.i.i.loopexit
+; CHECK-NEXT: .inst.n 0xdefe
entry:
%0 = load volatile ptr, ptr @g_566, align 4
br label %func_16.exit.i.i.i
diff --git a/llvm/test/CodeGen/ARM/vcge.ll b/llvm/test/CodeGen/ARM/vcge.ll
index a327a90894c214..318273cad7a970 100644
--- a/llvm/test/CodeGen/ARM/vcge.ll
+++ b/llvm/test/CodeGen/ARM/vcge.ll
@@ -289,6 +289,7 @@ define void @test_vclez_fp(ptr %A) nounwind optsize {
; CHECK-NEXT: vuzp.8 d16, d18
; CHECK-NEXT: vadd.i8 d16, d16, d17
; CHECK-NEXT: vst1.8 {d16}, [r0]
+; CHECK-NEXT: .inst 0xe7ffdefe
entry:
%ld = load <4 x float>, ptr %A
%0 = fcmp ole <4 x float> %ld, zeroinitializer
diff --git a/llvm/test/CodeGen/ARM/vector-DAGCombine.ll b/llvm/test/CodeGen/ARM/vector-DAGCombine.ll
index 7bc7b844396277..2a9e5e8a6f2148 100644
--- a/llvm/test/CodeGen/ARM/vector-DAGCombine.ll
+++ b/llvm/test/CodeGen/ARM/vector-DAGCombine.ll
@@ -27,6 +27,7 @@ bb.i19: ; preds = %bb.i19, %bb3
define void @test_illegal_build_vector() nounwind {
; CHECK-LABEL: test_illegal_build_vector:
; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: .inst 0xe7ffdefe
entry:
store <2 x i64> undef, ptr undef, align 16
%0 = load <16 x i8>, ptr undef, align 16 ; <<16 x i8>> [#uses=1]
@@ -40,6 +41,7 @@ entry:
define void @test_pr22678() {
; CHECK-LABEL: test_pr22678:
; CHECK: @ %bb.0:
+; CHECK-NEXT: .inst 0xe7ffdefe
%1 = fptoui <16 x float> undef to <16 x i8>
store <16 x i8> %1, ptr undef
ret void
diff --git a/llvm/test/CodeGen/ARM/vmov.ll b/llvm/test/CodeGen/ARM/vmov.ll
index ef0592b29ab37c..e3271bc19dbd8b 100644
--- a/llvm/test/CodeGen/ARM/vmov.ll
+++ b/llvm/test/CodeGen/ARM/vmov.ll
@@ -678,6 +678,7 @@ define arm_aapcs_vfpcc void @any_extend(<4 x i1> %x, <4 x i32> %y) nounwind ssp
; CHECK-LE-NEXT: vsub.i32 q8, q8, q1
; CHECK-LE-NEXT: vmovn.i32 d16, q8
; CHECK-LE-NEXT: vst1.16 {d16}, [r0]
+; CHECK-LE-NEXT: .inst 0xe7ffdefe
;
; CHECK-BE-LABEL: any_extend:
; CHECK-BE: @ %bb.0: @ %entry
@@ -689,6 +690,7 @@ define arm_aapcs_vfpcc void @any_extend(<4 x i1> %x, <4 x i32> %y) nounwind ssp
; CHECK-BE-NEXT: vsub.i32 q8, q8, q9
; CHECK-BE-NEXT: vmovn.i32 d16, q8
; CHECK-BE-NEXT: vst1.16 {d16}, [r0]
+; CHECK-BE-NEXT: .inst 0xe7ffdefe
entry:
%and.i186 = zext <4 x i1> %x to <4 x i32>
%add.i185 = sub <4 x i32> %and.i186, %y
diff --git a/llvm/test/CodeGen/ARM/vmul.ll b/llvm/test/CodeGen/ARM/vmul.ll
index 9915e050de2a66..8316d21fb5b60e 100644
--- a/llvm/test/CodeGen/ARM/vmul.ll
+++ b/llvm/test/CodeGen/ARM/vmul.ll
@@ -728,6 +728,7 @@ define i16 @vmullWithInconsistentExtensions(<8 x i8> %vec) {
define void @vmull_buildvector() nounwind optsize ssp align 2 {
; CHECK-LABEL: vmull_buildvector:
; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: .inst 0xe7ffdefe
entry:
br i1 undef, label %for.end179, label %for.body.lr.ph
@@ -804,6 +805,7 @@ declare <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16>) nounwind readnone
define void @no_illegal_types_vmull_sext(<4 x i32> %a) {
; CHECK-LABEL: no_illegal_types_vmull_sext:
; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: .inst 0xe7ffdefe
entry:
%wide.load283.i = load <4 x i8>, ptr undef, align 1
%0 = sext <4 x i8> %wide.load283.i to <4 x i32>
@@ -816,6 +818,7 @@ entry:
define void @no_illegal_types_vmull_zext(<4 x i32> %a) {
; CHECK-LABEL: no_illegal_types_vmull_zext:
; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: .inst 0xe7ffdefe
entry:
%wide.load283.i = load <4 x i8>, ptr undef, align 1
%0 = zext <4 x i8> %wide.load283.i to <4 x i32>
diff --git a/llvm/test/CodeGen/Lanai/sub-cmp-peephole.ll b/llvm/test/CodeGen/Lanai/sub-cmp-peephole.ll
index d79db0e6fbaa9f..8fb43044c971c3 100644
--- a/llvm/test/CodeGen/Lanai/sub-cmp-peephole.ll
+++ b/llvm/test/CodeGen/Lanai/sub-cmp-peephole.ll
@@ -99,8 +99,8 @@ if.else:
ret i32 %sub
}
-declare void @abort()
-declare void @exit(i32)
+declare void @abort() noreturn
+declare void @exit(i32) noreturn
@t = common global i32 0
; If the comparison uses the C bit (signed overflow/underflow), we can't
diff --git a/llvm/test/CodeGen/LoongArch/double-br-fcmp.ll b/llvm/test/CodeGen/LoongArch/double-br-fcmp.ll
index 50cbb11be2ef63..e2334ac9287064 100644
--- a/llvm/test/CodeGen/LoongArch/double-br-fcmp.ll
+++ b/llvm/test/CodeGen/LoongArch/double-br-fcmp.ll
@@ -15,6 +15,7 @@ define void @br_fcmp_oeq_bcnez(double %a, double %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_oeq_bcnez:
; LA64: # %bb.0:
@@ -26,6 +27,7 @@ define void @br_fcmp_oeq_bcnez(double %a, double %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp oeq double %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -46,6 +48,7 @@ define void @br_fcmp_oeq_bceqz(double %a, double %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_oeq_bceqz:
; LA64: # %bb.0:
@@ -57,6 +60,7 @@ define void @br_fcmp_oeq_bceqz(double %a, double %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp oeq double %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -77,6 +81,7 @@ define void @br_fcmp_ogt_bcnez(double %a, double %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_ogt_bcnez:
; LA64: # %bb.0:
@@ -88,6 +93,7 @@ define void @br_fcmp_ogt_bcnez(double %a, double %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp ogt double %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -108,6 +114,7 @@ define void @br_fcmp_ogt_bceqz(double %a, double %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_ogt_bceqz:
; LA64: # %bb.0:
@@ -119,6 +126,7 @@ define void @br_fcmp_ogt_bceqz(double %a, double %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp ogt double %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -139,6 +147,7 @@ define void @br_fcmp_oge_bcnez(double %a, double %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_oge_bcnez:
; LA64: # %bb.0:
@@ -150,6 +159,7 @@ define void @br_fcmp_oge_bcnez(double %a, double %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp oge double %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -170,6 +180,7 @@ define void @br_fcmp_oge_bceqz(double %a, double %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_oge_bceqz:
; LA64: # %bb.0:
@@ -181,6 +192,7 @@ define void @br_fcmp_oge_bceqz(double %a, double %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp oge double %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -201,6 +213,7 @@ define void @br_fcmp_olt_bcnez(double %a, double %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_olt_bcnez:
; LA64: # %bb.0:
@@ -212,6 +225,7 @@ define void @br_fcmp_olt_bcnez(double %a, double %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp olt double %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -232,6 +246,7 @@ define void @br_fcmp_olt_bceqz(double %a, double %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_olt_bceqz:
; LA64: # %bb.0:
@@ -243,6 +258,7 @@ define void @br_fcmp_olt_bceqz(double %a, double %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp olt double %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -263,6 +279,7 @@ define void @br_fcmp_ole_bcnez(double %a, double %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_ole_bcnez:
; LA64: # %bb.0:
@@ -274,6 +291,7 @@ define void @br_fcmp_ole_bcnez(double %a, double %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp ole double %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -294,6 +312,7 @@ define void @br_fcmp_ole_bceqz(double %a, double %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_ole_bceqz:
; LA64: # %bb.0:
@@ -305,6 +324,7 @@ define void @br_fcmp_ole_bceqz(double %a, double %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp ole double %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -325,6 +345,7 @@ define void @br_fcmp_one_bcnez(double %a, double %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_one_bcnez:
; LA64: # %bb.0:
@@ -336,6 +357,7 @@ define void @br_fcmp_one_bcnez(double %a, double %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp one double %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -356,6 +378,7 @@ define void @br_fcmp_one_bceqz(double %a, double %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_one_bceqz:
; LA64: # %bb.0:
@@ -367,6 +390,7 @@ define void @br_fcmp_one_bceqz(double %a, double %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp one double %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -387,6 +411,7 @@ define void @br_fcmp_ord_bcnez(double %a, double %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_ord_bcnez:
; LA64: # %bb.0:
@@ -398,6 +423,7 @@ define void @br_fcmp_ord_bcnez(double %a, double %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp ord double %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -418,6 +444,7 @@ define void @br_fcmp_ord_bceqz(double %a, double %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_ord_bceqz:
; LA64: # %bb.0:
@@ -429,6 +456,7 @@ define void @br_fcmp_ord_bceqz(double %a, double %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp ord double %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -449,6 +477,7 @@ define void @br_fcmp_ueq_bcnez(double %a, double %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_ueq_bcnez:
; LA64: # %bb.0:
@@ -460,6 +489,7 @@ define void @br_fcmp_ueq_bcnez(double %a, double %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp ueq double %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -480,6 +510,7 @@ define void @br_fcmp_ueq_bceqz(double %a, double %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_ueq_bceqz:
; LA64: # %bb.0:
@@ -491,6 +522,7 @@ define void @br_fcmp_ueq_bceqz(double %a, double %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp ueq double %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -511,6 +543,7 @@ define void @br_fcmp_ugt_bcnez(double %a, double %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_ugt_bcnez:
; LA64: # %bb.0:
@@ -522,6 +555,7 @@ define void @br_fcmp_ugt_bcnez(double %a, double %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp ugt double %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -542,6 +576,7 @@ define void @br_fcmp_ugt_bceqz(double %a, double %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_ugt_bceqz:
; LA64: # %bb.0:
@@ -553,6 +588,7 @@ define void @br_fcmp_ugt_bceqz(double %a, double %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp ugt double %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -573,6 +609,7 @@ define void @br_fcmp_uge_bcnez(double %a, double %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_uge_bcnez:
; LA64: # %bb.0:
@@ -584,6 +621,7 @@ define void @br_fcmp_uge_bcnez(double %a, double %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp uge double %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -604,6 +642,7 @@ define void @br_fcmp_uge_bceqz(double %a, double %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_uge_bceqz:
; LA64: # %bb.0:
@@ -615,6 +654,7 @@ define void @br_fcmp_uge_bceqz(double %a, double %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp uge double %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -635,6 +675,7 @@ define void @br_fcmp_ult_bcnez(double %a, double %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_ult_bcnez:
; LA64: # %bb.0:
@@ -646,6 +687,7 @@ define void @br_fcmp_ult_bcnez(double %a, double %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp ult double %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -666,6 +708,7 @@ define void @br_fcmp_ult_bceqz(double %a, double %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_ult_bceqz:
; LA64: # %bb.0:
@@ -677,6 +720,7 @@ define void @br_fcmp_ult_bceqz(double %a, double %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp ult double %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -697,6 +741,7 @@ define void @br_fcmp_ule_bcnez(double %a, double %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_ule_bcnez:
; LA64: # %bb.0:
@@ -708,6 +753,7 @@ define void @br_fcmp_ule_bcnez(double %a, double %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp ule double %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -728,6 +774,7 @@ define void @br_fcmp_ule_bceqz(double %a, double %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_ule_bceqz:
; LA64: # %bb.0:
@@ -739,6 +786,7 @@ define void @br_fcmp_ule_bceqz(double %a, double %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp ule double %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -759,6 +807,7 @@ define void @br_fcmp_une_bcnez(double %a, double %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_une_bcnez:
; LA64: # %bb.0:
@@ -770,6 +819,7 @@ define void @br_fcmp_une_bcnez(double %a, double %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp une double %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -790,6 +840,7 @@ define void @br_fcmp_une_bceqz(double %a, double %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_une_bceqz:
; LA64: # %bb.0:
@@ -801,6 +852,7 @@ define void @br_fcmp_une_bceqz(double %a, double %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp une double %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -821,6 +873,7 @@ define void @br_fcmp_uno_bcnez(double %a, double %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_uno_bcnez:
; LA64: # %bb.0:
@@ -832,6 +885,7 @@ define void @br_fcmp_uno_bcnez(double %a, double %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp uno double %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -852,6 +906,7 @@ define void @br_fcmp_uno_bceqz(double %a, double %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_uno_bceqz:
; LA64: # %bb.0:
@@ -863,6 +918,7 @@ define void @br_fcmp_uno_bceqz(double %a, double %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp uno double %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
diff --git a/llvm/test/CodeGen/LoongArch/float-br-fcmp.ll b/llvm/test/CodeGen/LoongArch/float-br-fcmp.ll
index a5edc9aa2c6e98..80066ebc015871 100644
--- a/llvm/test/CodeGen/LoongArch/float-br-fcmp.ll
+++ b/llvm/test/CodeGen/LoongArch/float-br-fcmp.ll
@@ -15,6 +15,7 @@ define void @br_fcmp_oeq_bcnez_float(float %a, float %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_oeq_bcnez_float:
; LA64: # %bb.0:
@@ -26,6 +27,7 @@ define void @br_fcmp_oeq_bcnez_float(float %a, float %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp oeq float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -46,6 +48,7 @@ define void @br_fcmp_oeq_bceqz_float(float %a, float %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_oeq_bceqz_float:
; LA64: # %bb.0:
@@ -57,6 +60,7 @@ define void @br_fcmp_oeq_bceqz_float(float %a, float %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp oeq float %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -77,6 +81,7 @@ define void @br_fcmp_ogt_bcnez_float(float %a, float %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_ogt_bcnez_float:
; LA64: # %bb.0:
@@ -88,6 +93,7 @@ define void @br_fcmp_ogt_bcnez_float(float %a, float %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp ogt float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -108,6 +114,7 @@ define void @br_fcmp_ogt_bceqz_float(float %a, float %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_ogt_bceqz_float:
; LA64: # %bb.0:
@@ -119,6 +126,7 @@ define void @br_fcmp_ogt_bceqz_float(float %a, float %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp ogt float %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -139,6 +147,7 @@ define void @br_fcmp_oge_bcnez_float(float %a, float %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_oge_bcnez_float:
; LA64: # %bb.0:
@@ -150,6 +159,7 @@ define void @br_fcmp_oge_bcnez_float(float %a, float %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp oge float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -170,6 +180,7 @@ define void @br_fcmp_oge_bceqz_float(float %a, float %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_oge_bceqz_float:
; LA64: # %bb.0:
@@ -181,6 +192,7 @@ define void @br_fcmp_oge_bceqz_float(float %a, float %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp oge float %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -201,6 +213,7 @@ define void @br_fcmp_olt_bcnez_float(float %a, float %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_olt_bcnez_float:
; LA64: # %bb.0:
@@ -212,6 +225,7 @@ define void @br_fcmp_olt_bcnez_float(float %a, float %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp olt float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -232,6 +246,7 @@ define void @br_fcmp_olt_bceqz_float(float %a, float %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_olt_bceqz_float:
; LA64: # %bb.0:
@@ -243,6 +258,7 @@ define void @br_fcmp_olt_bceqz_float(float %a, float %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp olt float %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -263,6 +279,7 @@ define void @br_fcmp_ole_bcnez_float(float %a, float %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_ole_bcnez_float:
; LA64: # %bb.0:
@@ -274,6 +291,7 @@ define void @br_fcmp_ole_bcnez_float(float %a, float %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp ole float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -294,6 +312,7 @@ define void @br_fcmp_ole_bceqz_float(float %a, float %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_ole_bceqz_float:
; LA64: # %bb.0:
@@ -305,6 +324,7 @@ define void @br_fcmp_ole_bceqz_float(float %a, float %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp ole float %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -325,6 +345,7 @@ define void @br_fcmp_one_bcnez_float(float %a, float %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_one_bcnez_float:
; LA64: # %bb.0:
@@ -336,6 +357,7 @@ define void @br_fcmp_one_bcnez_float(float %a, float %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp one float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -356,6 +378,7 @@ define void @br_fcmp_one_bceqz_float(float %a, float %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_one_bceqz_float:
; LA64: # %bb.0:
@@ -367,6 +390,7 @@ define void @br_fcmp_one_bceqz_float(float %a, float %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp one float %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -387,6 +411,7 @@ define void @br_fcmp_ord_bcnez_float(float %a, float %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_ord_bcnez_float:
; LA64: # %bb.0:
@@ -398,6 +423,7 @@ define void @br_fcmp_ord_bcnez_float(float %a, float %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp ord float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -418,6 +444,7 @@ define void @br_fcmp_ord_bceqz_float(float %a, float %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_ord_bceqz_float:
; LA64: # %bb.0:
@@ -429,6 +456,7 @@ define void @br_fcmp_ord_bceqz_float(float %a, float %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp ord float %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -449,6 +477,7 @@ define void @br_fcmp_ueq_bcnez_float(float %a, float %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_ueq_bcnez_float:
; LA64: # %bb.0:
@@ -460,6 +489,7 @@ define void @br_fcmp_ueq_bcnez_float(float %a, float %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp ueq float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -480,6 +510,7 @@ define void @br_fcmp_ueq_bceqz_float(float %a, float %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_ueq_bceqz_float:
; LA64: # %bb.0:
@@ -491,6 +522,7 @@ define void @br_fcmp_ueq_bceqz_float(float %a, float %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp ueq float %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -511,6 +543,7 @@ define void @br_fcmp_ugt_bcnez_float(float %a, float %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_ugt_bcnez_float:
; LA64: # %bb.0:
@@ -522,6 +555,7 @@ define void @br_fcmp_ugt_bcnez_float(float %a, float %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp ugt float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -542,6 +576,7 @@ define void @br_fcmp_ugt_bceqz_float(float %a, float %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_ugt_bceqz_float:
; LA64: # %bb.0:
@@ -553,6 +588,7 @@ define void @br_fcmp_ugt_bceqz_float(float %a, float %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp ugt float %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -573,6 +609,7 @@ define void @br_fcmp_uge_bcnez_float(float %a, float %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_uge_bcnez_float:
; LA64: # %bb.0:
@@ -584,6 +621,7 @@ define void @br_fcmp_uge_bcnez_float(float %a, float %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp uge float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -604,6 +642,7 @@ define void @br_fcmp_uge_bceqz_float(float %a, float %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_uge_bceqz_float:
; LA64: # %bb.0:
@@ -615,6 +654,7 @@ define void @br_fcmp_uge_bceqz_float(float %a, float %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp uge float %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -635,6 +675,7 @@ define void @br_fcmp_ult_bcnez_float(float %a, float %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_ult_bcnez_float:
; LA64: # %bb.0:
@@ -646,6 +687,7 @@ define void @br_fcmp_ult_bcnez_float(float %a, float %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp ult float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -666,6 +708,7 @@ define void @br_fcmp_ult_bceqz_float(float %a, float %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_ult_bceqz_float:
; LA64: # %bb.0:
@@ -677,6 +720,7 @@ define void @br_fcmp_ult_bceqz_float(float %a, float %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp ult float %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -697,6 +741,7 @@ define void @br_fcmp_ule_bcnez_float(float %a, float %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_ule_bcnez_float:
; LA64: # %bb.0:
@@ -708,6 +753,7 @@ define void @br_fcmp_ule_bcnez_float(float %a, float %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp ule float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -728,6 +774,7 @@ define void @br_fcmp_ule_bceqz_float(float %a, float %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_ule_bceqz_float:
; LA64: # %bb.0:
@@ -739,6 +786,7 @@ define void @br_fcmp_ule_bceqz_float(float %a, float %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp ule float %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -759,6 +807,7 @@ define void @br_fcmp_une_bcnez_float(float %a, float %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_une_bcnez_float:
; LA64: # %bb.0:
@@ -770,6 +819,7 @@ define void @br_fcmp_une_bcnez_float(float %a, float %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp une float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -790,6 +840,7 @@ define void @br_fcmp_une_bceqz_float(float %a, float %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_une_bceqz_float:
; LA64: # %bb.0:
@@ -801,6 +852,7 @@ define void @br_fcmp_une_bceqz_float(float %a, float %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp une float %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
@@ -821,6 +873,7 @@ define void @br_fcmp_uno_bcnez_float(float %a, float %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_uno_bcnez_float:
; LA64: # %bb.0:
@@ -832,6 +885,7 @@ define void @br_fcmp_uno_bcnez_float(float %a, float %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp uno float %a, %b
br i1 %1, label %if.then, label %if.else
if.else:
@@ -852,6 +906,7 @@ define void @br_fcmp_uno_bceqz_float(float %a, float %b) nounwind {
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
; LA32-NEXT: bl %plt(abort)
+; LA32-NEXT: amswap.w $zero, $ra, $zero
;
; LA64-LABEL: br_fcmp_uno_bceqz_float:
; LA64: # %bb.0:
@@ -863,6 +918,7 @@ define void @br_fcmp_uno_bceqz_float(float %a, float %b) nounwind {
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; LA64-NEXT: bl %plt(abort)
+; LA64-NEXT: amswap.w $zero, $ra, $zero
%1 = fcmp uno float %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
diff --git a/llvm/test/CodeGen/LoongArch/shrinkwrap.ll b/llvm/test/CodeGen/LoongArch/shrinkwrap.ll
index 8e5ec17d612412..7ed0e99102bae4 100644
--- a/llvm/test/CodeGen/LoongArch/shrinkwrap.ll
+++ b/llvm/test/CodeGen/LoongArch/shrinkwrap.ll
@@ -2,22 +2,19 @@
; RUN: llc --mtriple=loongarch64 -mattr=+d -O0 < %s | FileCheck %s --check-prefix=NOSHRINKW
; RUN: llc --mtriple=loongarch64 -mattr=+d -O2 < %s | FileCheck %s --check-prefix=SHRINKW
-declare void @abort()
+declare void @abort() noreturn
define void @eliminate_restore(i32 %n) nounwind {
; NOSHRINKW-LABEL: eliminate_restore:
; NOSHRINKW: # %bb.0:
-; NOSHRINKW-NEXT: addi.d $sp, $sp, -16
-; NOSHRINKW-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; NOSHRINKW-NEXT: addi.w $a1, $a0, 0
; NOSHRINKW-NEXT: ori $a0, $zero, 32
; NOSHRINKW-NEXT: bltu $a0, $a1, .LBB0_2
; NOSHRINKW-NEXT: b .LBB0_1
; NOSHRINKW-NEXT: .LBB0_1: # %if.then
; NOSHRINKW-NEXT: bl %plt(abort)
+; NOSHRINKW-NEXT: amswap.w $zero, $ra, $zero
; NOSHRINKW-NEXT: .LBB0_2: # %if.end
-; NOSHRINKW-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
-; NOSHRINKW-NEXT: addi.d $sp, $sp, 16
; NOSHRINKW-NEXT: ret
;
; SHRINKW-LABEL: eliminate_restore:
@@ -28,8 +25,6 @@ define void @eliminate_restore(i32 %n) nounwind {
; SHRINKW-NEXT: # %bb.1: # %if.end
; SHRINKW-NEXT: ret
; SHRINKW-NEXT: .LBB0_2: # %if.then
-; SHRINKW-NEXT: addi.d $sp, $sp, -16
-; SHRINKW-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; SHRINKW-NEXT: bl %plt(abort)
%cmp = icmp ule i32 %n, 32
br i1 %cmp, label %if.then, label %if.end
diff --git a/llvm/test/CodeGen/Mips/insn-zero-size-bb.ll b/llvm/test/CodeGen/Mips/insn-zero-size-bb.ll
index a5c16f8c45322e..95900e744ab3ef 100644
--- a/llvm/test/CodeGen/Mips/insn-zero-size-bb.ll
+++ b/llvm/test/CodeGen/Mips/insn-zero-size-bb.ll
@@ -1,6 +1,6 @@
-; RUN: llc < %s -mtriple=mips -mcpu=mips32 | FileCheck %s
-; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s
-; RUN: llc < %s -mtriple=mips -mattr=mips16 | FileCheck %s
+; RUN: llc < %s -trap-unreachable=false -mtriple=mips -mcpu=mips32 | FileCheck %s
+; RUN: llc < %s -trap-unreachable=false -mtriple=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s
+; RUN: llc < %s -trap-unreachable=false -mtriple=mips -mattr=mips16 | FileCheck %s
; Verify that we emit the .insn directive for zero-sized (empty) basic blocks.
; This only really matters for microMIPS and MIPS16.
diff --git a/llvm/test/CodeGen/Mips/micromips-gcc-except-table.ll b/llvm/test/CodeGen/Mips/micromips-gcc-except-table.ll
index 20d64fc216b79b..4ff8f39a9c5491 100644
--- a/llvm/test/CodeGen/Mips/micromips-gcc-except-table.ll
+++ b/llvm/test/CodeGen/Mips/micromips-gcc-except-table.ll
@@ -1,7 +1,7 @@
; RUN: llc -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+micromips -O3 -filetype=obj < %s | llvm-objdump -s -j .gcc_except_table - | FileCheck %s
; CHECK: Contents of section .gcc_except_table:
-; CHECK-NEXT: 0000 ff9b1501 0c001000 00100e1e 011e1800
+; CHECK-NEXT: 0000 ff9b1501 0c001000 00100e22 011e1c00
; CHECK-NEXT: 0010 00010000 00000000
@_ZTIi = external constant ptr
diff --git a/llvm/test/CodeGen/PowerPC/aix-vsx-splatimm.ll b/llvm/test/CodeGen/PowerPC/aix-vsx-splatimm.ll
index f5515e8ba19bd5..12028e0a33e6d0 100644
--- a/llvm/test/CodeGen/PowerPC/aix-vsx-splatimm.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-vsx-splatimm.ll
@@ -35,6 +35,7 @@ define void @test_aix_splatimm(i32 %arg, i32 %arg1, i32 %arg2) {
; CHECK-AIX-NEXT: lxvw4x 34, 0, 3
; CHECK-AIX-NEXT: vsplth 2, 2, 0
; CHECK-AIX-NEXT: stxvw4x 34, 0, 3
+; CHECK-AIX-NEXT: trap
;
; CHECK-LABEL: test_aix_splatimm:
; CHECK: # %bb.0: # %bb
@@ -56,6 +57,7 @@ define void @test_aix_splatimm(i32 %arg, i32 %arg1, i32 %arg2) {
; CHECK-NEXT: stxvd2x 34, 0, 3
; CHECK-NEXT: vsplth 3, 3, 3
; CHECK-NEXT: stxvd2x 35, 0, 3
+; CHECK-NEXT: trap
bb:
br i1 undef, label %bb22, label %bb3
diff --git a/llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll b/llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll
index e1159e56e23ebe..60cbc8b04bcb95 100644
--- a/llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll
+++ b/llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll
@@ -565,6 +565,7 @@ define dso_local void @no_crash_elt0_from_RHS(ptr noalias nocapture dereferencea
; CHECK-P8-NEXT: xxmrghd vs0, vs1, vs0
; CHECK-P8-NEXT: xxswapd vs0, vs0
; CHECK-P8-NEXT: stxvd2x vs0, 0, r30
+; CHECK-P8-NEXT: trap
;
; CHECK-P9-LABEL: no_crash_elt0_from_RHS:
; CHECK-P9: # %bb.0: # %test_entry
@@ -578,6 +579,7 @@ define dso_local void @no_crash_elt0_from_RHS(ptr noalias nocapture dereferencea
; CHECK-P9-NEXT: xxlxor f0, f0, f0
; CHECK-P9-NEXT: xxmrghd vs0, vs1, vs0
; CHECK-P9-NEXT: stxv vs0, 0(r30)
+; CHECK-P9-NEXT: trap
;
; CHECK-P9-BE-LABEL: no_crash_elt0_from_RHS:
; CHECK-P9-BE: # %bb.0: # %test_entry
@@ -591,6 +593,7 @@ define dso_local void @no_crash_elt0_from_RHS(ptr noalias nocapture dereferencea
; CHECK-P9-BE-NEXT: xxlxor f0, f0, f0
; CHECK-P9-BE-NEXT: xxmrghd vs0, vs0, vs1
; CHECK-P9-BE-NEXT: stxv vs0, 0(r30)
+; CHECK-P9-BE-NEXT: trap
;
; CHECK-NOVSX-LABEL: no_crash_elt0_from_RHS:
; CHECK-NOVSX: # %bb.0: # %test_entry
@@ -604,6 +607,7 @@ define dso_local void @no_crash_elt0_from_RHS(ptr noalias nocapture dereferencea
; CHECK-NOVSX-NEXT: li r3, 0
; CHECK-NOVSX-NEXT: stfd f1, 8(r30)
; CHECK-NOVSX-NEXT: std r3, 0(r30)
+; CHECK-NOVSX-NEXT: trap
;
; CHECK-P7-LABEL: no_crash_elt0_from_RHS:
; CHECK-P7: # %bb.0: # %test_entry
@@ -618,6 +622,7 @@ define dso_local void @no_crash_elt0_from_RHS(ptr noalias nocapture dereferencea
; CHECK-P7-NEXT: xxmrghd vs0, vs1, vs0
; CHECK-P7-NEXT: xxswapd vs0, vs0
; CHECK-P7-NEXT: stxvd2x vs0, 0, r30
+; CHECK-P7-NEXT: trap
;
; P8-AIX-64-LABEL: no_crash_elt0_from_RHS:
; P8-AIX-64: # %bb.0: # %test_entry
@@ -631,6 +636,7 @@ define dso_local void @no_crash_elt0_from_RHS(ptr noalias nocapture dereferencea
; P8-AIX-64-NEXT: xxlxor f0, f0, f0
; P8-AIX-64-NEXT: xxmrghd vs0, vs0, vs1
; P8-AIX-64-NEXT: stxvd2x vs0, 0, r31
+; P8-AIX-64-NEXT: trap
;
; P8-AIX-32-LABEL: no_crash_elt0_from_RHS:
; P8-AIX-32: # %bb.0: # %test_entry
@@ -644,6 +650,7 @@ define dso_local void @no_crash_elt0_from_RHS(ptr noalias nocapture dereferencea
; P8-AIX-32-NEXT: xxlxor f0, f0, f0
; P8-AIX-32-NEXT: xxmrghd vs0, vs0, vs1
; P8-AIX-32-NEXT: stxvd2x vs0, 0, r31
+; P8-AIX-32-NEXT: trap
test_entry:
%_div_result = tail call double @dummy()
%oldret = insertvalue { double, double } undef, double %_div_result, 0
diff --git a/llvm/test/CodeGen/PowerPC/empty-functions.ll b/llvm/test/CodeGen/PowerPC/empty-functions.ll
index f3238bae560e6d..64e14a95e22120 100644
--- a/llvm/test/CodeGen/PowerPC/empty-functions.ll
+++ b/llvm/test/CodeGen/PowerPC/empty-functions.ll
@@ -1,5 +1,5 @@
-; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-linux-gnu | FileCheck -check-prefix=LINUX-NO-FP %s
-; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-linux-gnu -frame-pointer=all | FileCheck -check-prefix=LINUX-FP %s
+; RUN: llc -verify-machineinstrs -trap-unreachable=false < %s -mtriple=powerpc-linux-gnu | FileCheck -check-prefix=LINUX-NO-FP %s
+; RUN: llc -verify-machineinstrs -trap-unreachable=false < %s -mtriple=powerpc-linux-gnu -frame-pointer=all | FileCheck -check-prefix=LINUX-FP %s
define void @func() {
entry:
diff --git a/llvm/test/CodeGen/PowerPC/expand-contiguous-isel.ll b/llvm/test/CodeGen/PowerPC/expand-contiguous-isel.ll
index 9e53c7e88b0e30..b73991c7b3473a 100644
--- a/llvm/test/CodeGen/PowerPC/expand-contiguous-isel.ll
+++ b/llvm/test/CodeGen/PowerPC/expand-contiguous-isel.ll
@@ -117,10 +117,12 @@ define i64 @_Z3fn1N4llvm9StringRefE([2 x i64] %Str.coerce) {
; CHECK-GEN-ISEL-TRUE-NEXT: addi r6, r4, 88
; CHECK-GEN-ISEL-TRUE-NEXT: bl __assert_fail
; CHECK-GEN-ISEL-TRUE-NEXT: nop
+; CHECK-GEN-ISEL-TRUE-NEXT: trap
; CHECK-GEN-ISEL-TRUE-NEXT: .LBB0_16: # %if.then9
; CHECK-GEN-ISEL-TRUE-NEXT: li r3, 1
; CHECK-GEN-ISEL-TRUE-NEXT: bl exit
; CHECK-GEN-ISEL-TRUE-NEXT: nop
+; CHECK-GEN-ISEL-TRUE-NEXT: trap
;
; CHECK-LABEL: _Z3fn1N4llvm9StringRefE:
; CHECK: # %bb.0: # %entry
@@ -233,10 +235,12 @@ define i64 @_Z3fn1N4llvm9StringRefE([2 x i64] %Str.coerce) {
; CHECK-NEXT: addi r6, r4, 88
; CHECK-NEXT: bl __assert_fail
; CHECK-NEXT: nop
+; CHECK-NEXT: trap
; CHECK-NEXT: .LBB0_21: # %if.then9
; CHECK-NEXT: li r3, 1
; CHECK-NEXT: bl exit
; CHECK-NEXT: nop
+; CHECK-NEXT: trap
entry:
%Str.coerce.fca.0.extract = extractvalue [2 x i64] %Str.coerce, 0
%Str.coerce.fca.1.extract = extractvalue [2 x i64] %Str.coerce, 1
diff --git a/llvm/test/CodeGen/PowerPC/fptoui-be-crash.ll b/llvm/test/CodeGen/PowerPC/fptoui-be-crash.ll
index 004d77eb33933a..875be83658961e 100644
--- a/llvm/test/CodeGen/PowerPC/fptoui-be-crash.ll
+++ b/llvm/test/CodeGen/PowerPC/fptoui-be-crash.ll
@@ -62,9 +62,11 @@ define dso_local void @calc_buffer() local_unnamed_addr #0 {
; CHECK-NEXT: rldic r4, r4, 63, 0
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: std r3, 0(r3)
+; CHECK-NEXT: trap
; CHECK-NEXT: .LBB0_10:
; CHECK-NEXT: ld r3, -16(r1)
; CHECK-NEXT: std r3, 0(r3)
+; CHECK-NEXT: trap
%load_initial = load i64, ptr poison, align 8
%conv39 = uitofp i64 %load_initial to float
%add48 = fadd float 0.000000e+00, %conv39
diff --git a/llvm/test/CodeGen/PowerPC/ifcvt-forked-bug-2016-08-08.ll b/llvm/test/CodeGen/PowerPC/ifcvt-forked-bug-2016-08-08.ll
index 64c60bffa31d7a..b5e1569f8a055e 100644
--- a/llvm/test/CodeGen/PowerPC/ifcvt-forked-bug-2016-08-08.ll
+++ b/llvm/test/CodeGen/PowerPC/ifcvt-forked-bug-2016-08-08.ll
@@ -5,34 +5,33 @@ target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu"
; Function Attrs: nounwind uwtable
-define hidden void @_ZN11__sanitizer25MaybeStartBackgroudThreadEv() local_unnamed_addr #0 {
+define hidden void @func() local_unnamed_addr #0 {
entry:
br i1 undef, label %land.lhs.true, label %if.end
; CHECK: # %land.lhs.true
; Test updated due D63152 where any load/store prevents shrink-wrapping
-; CHECK-NEXT: bc
+; CHECK-NEXT: bclr
; CHECK-NEXT: # %if.end4
land.lhs.true: ; preds = %entry
br i1 undef, label %return, label %if.end4
if.end: ; preds = %entry
- %cmp = icmp ne ptr @_ZN11__sanitizer19real_pthread_createEPvS0_PFS0_S0_ES0_, null
+ %cmp = icmp ne ptr @ptr1, null
br i1 %cmp, label %if.end4, label %return
if.end4: ; preds = %if.end, %land.lhs.true
- %call5 = tail call ptr @_ZN11__sanitizer21internal_start_threadEPFvPvES0_(ptr nonnull @_ZN11__sanitizer16BackgroundThreadEPv, ptr null) #7
+ %call5 = tail call ptr @test_fun(ptr nonnull @ptr2, ptr null) #7
unreachable
return: ; preds = %if.end, %land.lhs.true
ret void
}
-declare extern_weak signext i32 @_ZN11__sanitizer19real_pthread_createEPvS0_PFS0_S0_ES0_(ptr, ptr, ptr, ptr) #2
+declare extern_weak signext i32 @ptr1(ptr, ptr, ptr, ptr)
+declare ptr @test_fun(ptr, ptr) noreturn
-declare ptr @_ZN11__sanitizer21internal_start_threadEPFvPvES0_(ptr, ptr) local_unnamed_addr #2
-
-declare hidden void @_ZN11__sanitizer16BackgroundThreadEPv(ptr nocapture readnone) #5
+declare hidden void @ptr2(ptr nocapture readnone)
attributes #0 = { nounwind uwtable "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #7 = { nobuiltin nounwind }
diff --git a/llvm/test/CodeGen/PowerPC/p10-spill-crlt.ll b/llvm/test/CodeGen/PowerPC/p10-spill-crlt.ll
index 4b032781c3764c..b5baef346e749c 100644
--- a/llvm/test/CodeGen/PowerPC/p10-spill-crlt.ll
+++ b/llvm/test/CodeGen/PowerPC/p10-spill-crlt.ll
@@ -39,9 +39,9 @@ define dso_local void @P10_Spill_CR_LT() local_unnamed_addr {
; CHECK-NEXT: .cfi_offset cr4, 8
; CHECK-NEXT: std r30, 32(r1) # 8-byte Folded Spill
; CHECK-NEXT: bl call_2 at notoc
-; CHECK-NEXT: bc 12, 4*cr5+lt, .LBB0_13
+; CHECK-NEXT: bc 12, 4*cr5+lt, .LBB0_7
; CHECK-NEXT: # %bb.1: # %bb
-; CHECK-NEXT: bc 4, 4*cr5+lt, .LBB0_14
+; CHECK-NEXT: bc 4, 4*cr5+lt, .LBB0_7
; CHECK-NEXT: # %bb.2: # %bb4
; CHECK-NEXT: cmpdi cr3, r3, 0
; CHECK-NEXT: lwz r3, 0(r3)
@@ -54,15 +54,15 @@ define dso_local void @P10_Spill_CR_LT() local_unnamed_addr {
; CHECK-NEXT: bl call_3 at notoc
; CHECK-NEXT: cmpwi r3, 1
; CHECK-NEXT: crnand 4*cr5+lt, eq, 4*cr4+gt
-; CHECK-NEXT: bc 4, 4*cr5+lt, .LBB0_8
+; CHECK-NEXT: bc 4, 4*cr5+lt, .LBB0_7
; CHECK-NEXT: # %bb.4: # %bb23
; CHECK-NEXT: #
; CHECK-NEXT: plwz r3, call_1 at PCREL(0), 1
; CHECK-NEXT: cmplwi r3, 0
-; CHECK-NEXT: bne- cr0, .LBB0_9
+; CHECK-NEXT: bne- cr0, .LBB0_7
; CHECK-NEXT: # %bb.5: # %bb30
; CHECK-NEXT: #
-; CHECK-NEXT: bc 12, 4*cr3+eq, .LBB0_11
+; CHECK-NEXT: bc 12, 4*cr3+eq, .LBB0_7
; CHECK-NEXT: # %bb.6: # %bb32
; CHECK-NEXT: #
; CHECK-NEXT: rlwinm r30, r30, 0, 24, 22
@@ -70,15 +70,8 @@ define dso_local void @P10_Spill_CR_LT() local_unnamed_addr {
; CHECK-NEXT: mcrf cr2, cr0
; CHECK-NEXT: bl call_4 at notoc
; CHECK-NEXT: beq+ cr2, .LBB0_3
-; CHECK-NEXT: # %bb.7: # %bb37
-; CHECK-NEXT: .LBB0_8: # %bb22
-; CHECK-NEXT: .LBB0_9: # %bb27
-; CHECK-NEXT: bc 4, 4*cr3+lt, .LBB0_12
-; CHECK-NEXT: # %bb.10: # %bb28
-; CHECK-NEXT: .LBB0_11: # %bb35
-; CHECK-NEXT: .LBB0_12: # %bb29
-; CHECK-NEXT: .LBB0_13: # %bb3
-; CHECK-NEXT: .LBB0_14: # %bb2
+; CHECK-NEXT: .LBB0_7: # %bb2
+; CHECK-NEXT: trap
;
; CHECK-BE-LABEL: P10_Spill_CR_LT:
; CHECK-BE: # %bb.0: # %bb
@@ -98,9 +91,9 @@ define dso_local void @P10_Spill_CR_LT() local_unnamed_addr {
; CHECK-BE-NEXT: std r30, 128(r1) # 8-byte Folded Spill
; CHECK-BE-NEXT: bl call_2
; CHECK-BE-NEXT: nop
-; CHECK-BE-NEXT: bc 12, 4*cr5+lt, .LBB0_13
+; CHECK-BE-NEXT: bc 12, 4*cr5+lt, .LBB0_7
; CHECK-BE-NEXT: # %bb.1: # %bb
-; CHECK-BE-NEXT: bc 4, 4*cr5+lt, .LBB0_14
+; CHECK-BE-NEXT: bc 4, 4*cr5+lt, .LBB0_7
; CHECK-BE-NEXT: # %bb.2: # %bb4
; CHECK-BE-NEXT: cmpdi cr3, r3, 0
; CHECK-BE-NEXT: lwz r3, 0(r3)
@@ -115,15 +108,15 @@ define dso_local void @P10_Spill_CR_LT() local_unnamed_addr {
; CHECK-BE-NEXT: nop
; CHECK-BE-NEXT: cmpwi r3, 1
; CHECK-BE-NEXT: crnand 4*cr5+lt, eq, 4*cr4+gt
-; CHECK-BE-NEXT: bc 4, 4*cr5+lt, .LBB0_8
+; CHECK-BE-NEXT: bc 4, 4*cr5+lt, .LBB0_7
; CHECK-BE-NEXT: # %bb.4: # %bb23
; CHECK-BE-NEXT: #
; CHECK-BE-NEXT: lwz r3, call_1 at toc@l(r30)
; CHECK-BE-NEXT: cmplwi r3, 0
-; CHECK-BE-NEXT: bne- cr0, .LBB0_9
+; CHECK-BE-NEXT: bne- cr0, .LBB0_7
; CHECK-BE-NEXT: # %bb.5: # %bb30
; CHECK-BE-NEXT: #
-; CHECK-BE-NEXT: bc 12, 4*cr3+eq, .LBB0_11
+; CHECK-BE-NEXT: bc 12, 4*cr3+eq, .LBB0_7
; CHECK-BE-NEXT: # %bb.6: # %bb32
; CHECK-BE-NEXT: #
; CHECK-BE-NEXT: rlwinm r29, r29, 0, 24, 22
@@ -132,15 +125,8 @@ define dso_local void @P10_Spill_CR_LT() local_unnamed_addr {
; CHECK-BE-NEXT: bl call_4
; CHECK-BE-NEXT: nop
; CHECK-BE-NEXT: beq+ cr2, .LBB0_3
-; CHECK-BE-NEXT: # %bb.7: # %bb37
-; CHECK-BE-NEXT: .LBB0_8: # %bb22
-; CHECK-BE-NEXT: .LBB0_9: # %bb27
-; CHECK-BE-NEXT: bc 4, 4*cr3+lt, .LBB0_12
-; CHECK-BE-NEXT: # %bb.10: # %bb28
-; CHECK-BE-NEXT: .LBB0_11: # %bb35
-; CHECK-BE-NEXT: .LBB0_12: # %bb29
-; CHECK-BE-NEXT: .LBB0_13: # %bb3
-; CHECK-BE-NEXT: .LBB0_14: # %bb2
+; CHECK-BE-NEXT: .LBB0_7: # %bb2
+; CHECK-BE-NEXT: trap
bb:
%tmp = tail call ptr @call_2()
%tmp1 = icmp ne ptr %tmp, null
diff --git a/llvm/test/CodeGen/PowerPC/pr43527.ll b/llvm/test/CodeGen/PowerPC/pr43527.ll
index 379bd6c070c777..97d47509f58fc3 100644
--- a/llvm/test/CodeGen/PowerPC/pr43527.ll
+++ b/llvm/test/CodeGen/PowerPC/pr43527.ll
@@ -7,7 +7,7 @@ define dso_local void @test(i64 %arg, i64 %arg1) {
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: bc 4, 4*cr5+lt, .LBB0_5
; CHECK-NEXT: # %bb.1: # %bb3
-; CHECK-NEXT: bc 12, 4*cr5+lt, .LBB0_6
+; CHECK-NEXT: bc 12, 4*cr5+lt, .LBB0_5
; CHECK-NEXT: # %bb.2: # %bb4
; CHECK-NEXT: mflr r0
; CHECK-NEXT: .cfi_def_cfa_offset 64
@@ -38,7 +38,7 @@ define dso_local void @test(i64 %arg, i64 %arg1) {
; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr
; CHECK-NEXT: .LBB0_5: # %bb2
-; CHECK-NEXT: .LBB0_6: # %bb14
+; CHECK-NEXT: trap
bb:
br i1 undef, label %bb3, label %bb2
diff --git a/llvm/test/CodeGen/PowerPC/pr45448.ll b/llvm/test/CodeGen/PowerPC/pr45448.ll
index 0f2dcb3ccc8a0b..7f331ebef4eb29 100644
--- a/llvm/test/CodeGen/PowerPC/pr45448.ll
+++ b/llvm/test/CodeGen/PowerPC/pr45448.ll
@@ -7,18 +7,17 @@ define hidden void @julia_tryparse_internal_45896() #0 {
; CHECK: # %bb.0: # %top
; CHECK-NEXT: ld r3, 0(r3)
; CHECK-NEXT: cmpldi r3, 0
-; CHECK-NEXT: beq cr0, .LBB0_6
+; CHECK-NEXT: beq cr0, .LBB0_2
; CHECK-NEXT: # %bb.1: # %top
; CHECK-NEXT: cmpldi r3, 10
; CHECK-NEXT: beq cr0, .LBB0_3
-; CHECK-NEXT: # %bb.2: # %top
+; CHECK-NEXT: .LBB0_2: # %top
+; CHECK-NEXT: trap
; CHECK-NEXT: .LBB0_3: # %L294
-; CHECK-NEXT: bc 12, 4*cr5+lt, .LBB0_5
+; CHECK-NEXT: bc 12, 4*cr5+lt, .LBB0_2
; CHECK-NEXT: # %bb.4: # %L294
-; CHECK-NEXT: bc 4, 4*cr5+lt, .LBB0_7
-; CHECK-NEXT: .LBB0_5: # %L1057.preheader
-; CHECK-NEXT: .LBB0_6: # %fail194
-; CHECK-NEXT: .LBB0_7: # %L670
+; CHECK-NEXT: bc 12, 4*cr5+lt, .LBB0_2
+; CHECK-NEXT: # %bb.5: # %L670
; CHECK-NEXT: li r5, -3
; CHECK-NEXT: sradi r4, r3, 63
; CHECK-NEXT: rldic r5, r5, 4, 32
@@ -27,9 +26,7 @@ define hidden void @julia_tryparse_internal_45896() #0 {
; CHECK-NEXT: cmpld cr1, r6, r3
; CHECK-NEXT: mulhdu. r3, r4, r5
; CHECK-NEXT: crorc 4*cr5+lt, 4*cr1+lt, eq
-; CHECK-NEXT: bc 4, 4*cr5+lt, .LBB0_9
-; CHECK-NEXT: # %bb.8: # %L917
-; CHECK-NEXT: .LBB0_9: # %L994
+; CHECK-NEXT: trap
top:
%0 = load i64, ptr undef, align 8
%1 = icmp ne i64 %0, 0
diff --git a/llvm/test/CodeGen/PowerPC/reduce_scalarization.ll b/llvm/test/CodeGen/PowerPC/reduce_scalarization.ll
index 6d188ce3b4a5ee..407223e31e072f 100644
--- a/llvm/test/CodeGen/PowerPC/reduce_scalarization.ll
+++ b/llvm/test/CodeGen/PowerPC/reduce_scalarization.ll
@@ -239,7 +239,11 @@ define dso_local i32 @test6() #0 {
; CHECK-P10-NEXT: andi. r3, r3, 1
; CHECK-P10-NEXT: bc 4, gt, .LBB5_2
; CHECK-P10-NEXT: # %bb.1: # %bb8
+; CHECK-P10-NEXT: li r3, 2
+; CHECK-P10-NEXT: blr
; CHECK-P10-NEXT: .LBB5_2: # %bb7
+; CHECK-P10-NEXT: li r3, 1
+; CHECK-P10-NEXT: blr
;
; CHECK-P10-BE-LABEL: test6:
; CHECK-P10-BE: # %bb.0: # %bb
@@ -256,7 +260,11 @@ define dso_local i32 @test6() #0 {
; CHECK-P10-BE-NEXT: andi. r3, r3, 1
; CHECK-P10-BE-NEXT: bc 4, gt, .LBB5_2
; CHECK-P10-BE-NEXT: # %bb.1: # %bb8
+; CHECK-P10-BE-NEXT: li r3, 2
+; CHECK-P10-BE-NEXT: blr
; CHECK-P10-BE-NEXT: .LBB5_2: # %bb7
+; CHECK-P10-BE-NEXT: li r3, 1
+; CHECK-P10-BE-NEXT: blr
;
; AIX-64-LABEL: test6:
; AIX-64: # %bb.0: # %bb
@@ -274,7 +282,11 @@ define dso_local i32 @test6() #0 {
; AIX-64-NEXT: andi. r3, r3, 1
; AIX-64-NEXT: bc 4, gt, L..BB5_2
; AIX-64-NEXT: # %bb.1: # %bb8
+; AIX-64-NEXT: li r3, 2
+; AIX-64-NEXT: blr
; AIX-64-NEXT: L..BB5_2: # %bb7
+; AIX-64-NEXT: li r3, 1
+; AIX-64-NEXT: blr
;
; AIX-32-LABEL: test6:
; AIX-32: # %bb.0: # %bb
@@ -294,7 +306,11 @@ define dso_local i32 @test6() #0 {
; AIX-32-NEXT: andi. r3, r3, 1
; AIX-32-NEXT: bc 4, gt, L..BB5_2
; AIX-32-NEXT: # %bb.1: # %bb8
+; AIX-32-NEXT: li r3, 2
+; AIX-32-NEXT: blr
; AIX-32-NEXT: L..BB5_2: # %bb7
+; AIX-32-NEXT: li r3, 1
+; AIX-32-NEXT: blr
bb:
br label %bb1
@@ -308,8 +324,8 @@ bb1: ; preds = %bb
br i1 %i6, label %bb8, label %bb7
bb7: ; preds = %bb1
- unreachable
+ ret i32 1
bb8: ; preds = %bb1
- unreachable
+ ret i32 2
}
diff --git a/llvm/test/CodeGen/PowerPC/redundant-copy-after-tail-dup.ll b/llvm/test/CodeGen/PowerPC/redundant-copy-after-tail-dup.ll
index 376655bfb2b06a..d3149e74397ce4 100644
--- a/llvm/test/CodeGen/PowerPC/redundant-copy-after-tail-dup.ll
+++ b/llvm/test/CodeGen/PowerPC/redundant-copy-after-tail-dup.ll
@@ -35,6 +35,7 @@ define dso_local i1 @t(ptr %this, i32 %color, i32 %vertex) local_unnamed_addr {
; CHECK-P9-NEXT: mr r3, r5
; CHECK-P9-NEXT: blr
; CHECK-P9-NEXT: .LBB0_6: # %lor.lhs.false.1
+; CHECK-P9-NEXT: trap
entry:
br i1 undef, label %land.lhs.true, label %lor.lhs.false
diff --git a/llvm/test/CodeGen/PowerPC/remove-redundant-load-imm.ll b/llvm/test/CodeGen/PowerPC/remove-redundant-load-imm.ll
index 0be72d9fc59542..c13c3fcc633df6 100644
--- a/llvm/test/CodeGen/PowerPC/remove-redundant-load-imm.ll
+++ b/llvm/test/CodeGen/PowerPC/remove-redundant-load-imm.ll
@@ -45,6 +45,7 @@ define void @redundancy_on_ppc_and_other_targets() nounwind {
; PPC64LE-NEXT: std 4, 0(3)
; PPC64LE-NEXT: bl barney.94
; PPC64LE-NEXT: nop
+; PPC64LE-NEXT: trap
store ptr null, ptr @global.6
call void @barney.94(ptr undef, i32 0)
unreachable
diff --git a/llvm/test/CodeGen/PowerPC/subreg-postra-2.ll b/llvm/test/CodeGen/PowerPC/subreg-postra-2.ll
index f696745c9d4142..007445a8480894 100644
--- a/llvm/test/CodeGen/PowerPC/subreg-postra-2.ll
+++ b/llvm/test/CodeGen/PowerPC/subreg-postra-2.ll
@@ -38,9 +38,7 @@ define void @jbd2_journal_commit_transaction(i32 %input1, ptr %input2, ptr %inpu
; CHECK-NEXT: isel 7, 3, 8, 20
; CHECK-NEXT: .LBB0_4: # %while.end418
; CHECK-NEXT: cmplwi 7, 0
-; CHECK-NEXT: beq 0, .LBB0_6
-; CHECK-NEXT: # %bb.5: # %if.then420
-; CHECK-NEXT: .LBB0_6: # %if.end421
+; CHECK-NEXT: trap
;
; CHECK-NO-ISEL-LABEL: jbd2_journal_commit_transaction:
; CHECK-NO-ISEL: # %bb.0: # %entry
@@ -61,10 +59,10 @@ define void @jbd2_journal_commit_transaction(i32 %input1, ptr %input2, ptr %inpu
; CHECK-NO-ISEL-EMPTY:
; CHECK-NO-ISEL-NEXT: #NO_APP
; CHECK-NO-ISEL-NEXT: std 5, 0(6)
-; CHECK-NO-ISEL-NEXT: beq- 5, .LBB0_6
+; CHECK-NO-ISEL-NEXT: beq- 5, .LBB0_5
; CHECK-NO-ISEL-NEXT: .LBB0_2: # %while.body392
; CHECK-NO-ISEL-NEXT: #
-; CHECK-NO-ISEL-NEXT: bne- 1, .LBB0_5
+; CHECK-NO-ISEL-NEXT: bne- 1, .LBB0_6
; CHECK-NO-ISEL-NEXT: # %bb.3: # %wait_on_buffer.exit1319
; CHECK-NO-ISEL-NEXT: #
; CHECK-NO-ISEL-NEXT: ld 5, 0(6)
@@ -77,13 +75,12 @@ define void @jbd2_journal_commit_transaction(i32 %input1, ptr %input2, ptr %inpu
; CHECK-NO-ISEL-NEXT: #
; CHECK-NO-ISEL-NEXT: li 4, -5
; CHECK-NO-ISEL-NEXT: b .LBB0_1
-; CHECK-NO-ISEL-NEXT: .LBB0_5:
-; CHECK-NO-ISEL-NEXT: mr 4, 7
-; CHECK-NO-ISEL-NEXT: .LBB0_6: # %while.end418
+; CHECK-NO-ISEL-NEXT: .LBB0_5: # %while.end418
; CHECK-NO-ISEL-NEXT: cmplwi 4, 0
-; CHECK-NO-ISEL-NEXT: beq 0, .LBB0_8
-; CHECK-NO-ISEL-NEXT: # %bb.7: # %if.then420
-; CHECK-NO-ISEL-NEXT: .LBB0_8: # %if.end421
+; CHECK-NO-ISEL-NEXT: trap
+; CHECK-NO-ISEL-NEXT: .LBB0_6:
+; CHECK-NO-ISEL-NEXT: cmplwi 7, 0
+; CHECK-NO-ISEL-NEXT: trap
entry:
br label %while.body392
diff --git a/llvm/test/CodeGen/PowerPC/subreg-postra.ll b/llvm/test/CodeGen/PowerPC/subreg-postra.ll
index a315da545ba0f8..1fb041936e1456 100644
--- a/llvm/test/CodeGen/PowerPC/subreg-postra.ll
+++ b/llvm/test/CodeGen/PowerPC/subreg-postra.ll
@@ -25,54 +25,50 @@ define void @jbd2_journal_commit_transaction(ptr %journal, i64 %inp1, i32 %inp2,
; CHECK-NEXT: andi. 6, 10, 1
; CHECK-NEXT: crmove 8, 1
; CHECK-NEXT: andi. 6, 9, 1
-; CHECK-NEXT: bc 4, 20, .LBB0_24
+; CHECK-NEXT: bc 4, 20, .LBB0_22
; CHECK-NEXT: # %bb.1: # %do.body
-; CHECK-NEXT: bc 4, 20, .LBB0_25
+; CHECK-NEXT: bc 4, 20, .LBB0_22
; CHECK-NEXT: # %bb.2: # %trace_jbd2_start_commit.exit
; CHECK-NEXT: mr 30, 8
; CHECK-NEXT: mr 29, 7
; CHECK-NEXT: bc 12, 20, .LBB0_4
; CHECK-NEXT: # %bb.3: # %do.body.i1116
-; CHECK-NEXT: bc 4, 20, .LBB0_26
+; CHECK-NEXT: bc 4, 20, .LBB0_22
; CHECK-NEXT: .LBB0_4: # %trace_jbd2_commit_locking.exit
-; CHECK-NEXT: bc 4, 20, .LBB0_27
+; CHECK-NEXT: bc 4, 20, .LBB0_22
; CHECK-NEXT: # %bb.5: # %spin_unlock.exit1146
-; CHECK-NEXT: bc 4, 20, .LBB0_28
+; CHECK-NEXT: bc 4, 20, .LBB0_22
; CHECK-NEXT: # %bb.6: # %trace_jbd2_commit_flushing.exit
-; CHECK-NEXT: bc 4, 20, .LBB0_29
+; CHECK-NEXT: bc 4, 20, .LBB0_22
; CHECK-NEXT: # %bb.7: # %for.end.i
-; CHECK-NEXT: bc 4, 20, .LBB0_31
+; CHECK-NEXT: bc 4, 20, .LBB0_22
; CHECK-NEXT: # %bb.8: # %journal_submit_data_buffers.exit
-; CHECK-NEXT: bc 4, 20, .LBB0_32
+; CHECK-NEXT: bc 4, 20, .LBB0_22
; CHECK-NEXT: # %bb.9: # %if.end103
-; CHECK-NEXT: bc 4, 20, .LBB0_33
+; CHECK-NEXT: bc 4, 20, .LBB0_22
; CHECK-NEXT: # %bb.10: # %trace_jbd2_commit_logging.exit
-; CHECK-NEXT: bc 4, 20, .LBB0_34
+; CHECK-NEXT: bc 4, 20, .LBB0_22
; CHECK-NEXT: # %bb.11: # %for.end.i1287
-; CHECK-NEXT: bc 4, 20, .LBB0_35
+; CHECK-NEXT: bc 4, 20, .LBB0_22
; CHECK-NEXT: # %bb.12: # %journal_finish_inode_data_buffers.exit
-; CHECK-NEXT: bc 4, 20, .LBB0_36
+; CHECK-NEXT: bc 4, 20, .LBB0_22
; CHECK-NEXT: # %bb.13: # %if.end256
; CHECK-NEXT: cmpdi 1, 4, 0
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB0_14: # %while.body318
; CHECK-NEXT: #
-; CHECK-NEXT: bc 4, 6, .LBB0_19
+; CHECK-NEXT: bc 4, 6, .LBB0_22
; CHECK-NEXT: # %bb.15: # %wait_on_buffer.exit
; CHECK-NEXT: #
; CHECK-NEXT: bc 4, 1, .LBB0_14
; CHECK-NEXT: # %bb.16: # %do.body378
-; CHECK-NEXT: bc 4, 8, .LBB0_20
-; CHECK-NEXT: # %bb.17: # %while.end418
-; CHECK-NEXT: bc 4, 8, .LBB0_23
-; CHECK-NEXT: .LBB0_18: # %if.end421
-; CHECK-NEXT: .LBB0_19: # %if.then.i1296
-; CHECK-NEXT: .LBB0_20: # %while.body392.lr.ph
+; CHECK-NEXT: bc 12, 8, .LBB0_20
+; CHECK-NEXT: # %bb.17: # %while.body392.lr.ph
; CHECK-NEXT: lis 26, 4
; CHECK-NEXT: mr 27, 5
; CHECK-NEXT: mr 28, 3
; CHECK-NEXT: .p2align 4
-; CHECK-NEXT: .LBB0_21: # %while.body392
+; CHECK-NEXT: .LBB0_18: # %while.body392
; CHECK-NEXT: #
; CHECK-NEXT: ld 3, 0(3)
; CHECK-NEXT: ldu 25, -72(3)
@@ -88,33 +84,21 @@ define void @jbd2_journal_commit_transaction(ptr %journal, i64 %inp1, i32 %inp2,
; CHECK-NEXT: std 3, 0(30)
; CHECK-NEXT: bl __brelse
; CHECK-NEXT: nop
-; CHECK-NEXT: bc 4, 9, .LBB0_21
-; CHECK-NEXT: # %bb.22: # %while.end418.loopexit
+; CHECK-NEXT: bc 4, 9, .LBB0_18
+; CHECK-NEXT: # %bb.19: # %while.end418.loopexit
; CHECK-NEXT: andi. 3, 25, 1
; CHECK-NEXT: li 3, -5
; CHECK-NEXT: mr 5, 27
; CHECK-NEXT: iselgt 5, 5, 3
; CHECK-NEXT: mr 3, 28
-; CHECK-NEXT: bc 12, 8, .LBB0_18
-; CHECK-NEXT: .LBB0_23: # %if.then420
+; CHECK-NEXT: .LBB0_20: # %while.end418
+; CHECK-NEXT: bc 12, 8, .LBB0_22
+; CHECK-NEXT: # %bb.21: # %if.then420
; CHECK-NEXT: extsw 4, 5
; CHECK-NEXT: bl jbd2_journal_abort
; CHECK-NEXT: nop
-; CHECK-NEXT: .LBB0_24: # %if.then5
-; CHECK-NEXT: .LBB0_25: # %do.body.i
-; CHECK-NEXT: .LBB0_26: # %do.body5.i1122
-; CHECK-NEXT: .LBB0_27: # %if.then.i.i.i.i1144
-; CHECK-NEXT: .LBB0_28: # %do.body.i1159
-; CHECK-NEXT: .LBB0_29: # %for.body.lr.ph.i
-; CHECK-NEXT: bc 4, 20, .LBB0_37
-; CHECK-NEXT: # %bb.30: # %spin_unlock.exit.i
-; CHECK-NEXT: .LBB0_31: # %if.then.i.i.i.i31.i
-; CHECK-NEXT: .LBB0_32: # %if.then102
-; CHECK-NEXT: .LBB0_33: # %do.body.i1182
-; CHECK-NEXT: .LBB0_34: # %for.body.i1277
-; CHECK-NEXT: .LBB0_35: # %if.then.i.i.i.i84.i
-; CHECK-NEXT: .LBB0_36: # %if.then249
-; CHECK-NEXT: .LBB0_37: # %if.then.i.i.i.i.i
+; CHECK-NEXT: .LBB0_22: # %if.then5
+; CHECK-NEXT: trap
;
; CHECK-NO-ISEL-LABEL: jbd2_journal_commit_transaction:
; CHECK-NO-ISEL: # %bb.0: # %entry
@@ -135,54 +119,50 @@ define void @jbd2_journal_commit_transaction(ptr %journal, i64 %inp1, i32 %inp2,
; CHECK-NO-ISEL-NEXT: andi. 6, 10, 1
; CHECK-NO-ISEL-NEXT: crmove 8, 1
; CHECK-NO-ISEL-NEXT: andi. 6, 9, 1
-; CHECK-NO-ISEL-NEXT: bc 4, 20, .LBB0_26
+; CHECK-NO-ISEL-NEXT: bc 4, 20, .LBB0_24
; CHECK-NO-ISEL-NEXT: # %bb.1: # %do.body
-; CHECK-NO-ISEL-NEXT: bc 4, 20, .LBB0_27
+; CHECK-NO-ISEL-NEXT: bc 4, 20, .LBB0_24
; CHECK-NO-ISEL-NEXT: # %bb.2: # %trace_jbd2_start_commit.exit
; CHECK-NO-ISEL-NEXT: mr 30, 8
; CHECK-NO-ISEL-NEXT: mr 29, 7
; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB0_4
; CHECK-NO-ISEL-NEXT: # %bb.3: # %do.body.i1116
-; CHECK-NO-ISEL-NEXT: bc 4, 20, .LBB0_28
+; CHECK-NO-ISEL-NEXT: bc 4, 20, .LBB0_24
; CHECK-NO-ISEL-NEXT: .LBB0_4: # %trace_jbd2_commit_locking.exit
-; CHECK-NO-ISEL-NEXT: bc 4, 20, .LBB0_29
+; CHECK-NO-ISEL-NEXT: bc 4, 20, .LBB0_24
; CHECK-NO-ISEL-NEXT: # %bb.5: # %spin_unlock.exit1146
-; CHECK-NO-ISEL-NEXT: bc 4, 20, .LBB0_30
+; CHECK-NO-ISEL-NEXT: bc 4, 20, .LBB0_24
; CHECK-NO-ISEL-NEXT: # %bb.6: # %trace_jbd2_commit_flushing.exit
-; CHECK-NO-ISEL-NEXT: bc 4, 20, .LBB0_31
+; CHECK-NO-ISEL-NEXT: bc 4, 20, .LBB0_24
; CHECK-NO-ISEL-NEXT: # %bb.7: # %for.end.i
-; CHECK-NO-ISEL-NEXT: bc 4, 20, .LBB0_33
+; CHECK-NO-ISEL-NEXT: bc 4, 20, .LBB0_24
; CHECK-NO-ISEL-NEXT: # %bb.8: # %journal_submit_data_buffers.exit
-; CHECK-NO-ISEL-NEXT: bc 4, 20, .LBB0_34
+; CHECK-NO-ISEL-NEXT: bc 4, 20, .LBB0_24
; CHECK-NO-ISEL-NEXT: # %bb.9: # %if.end103
-; CHECK-NO-ISEL-NEXT: bc 4, 20, .LBB0_35
+; CHECK-NO-ISEL-NEXT: bc 4, 20, .LBB0_24
; CHECK-NO-ISEL-NEXT: # %bb.10: # %trace_jbd2_commit_logging.exit
-; CHECK-NO-ISEL-NEXT: bc 4, 20, .LBB0_36
+; CHECK-NO-ISEL-NEXT: bc 4, 20, .LBB0_24
; CHECK-NO-ISEL-NEXT: # %bb.11: # %for.end.i1287
-; CHECK-NO-ISEL-NEXT: bc 4, 20, .LBB0_37
+; CHECK-NO-ISEL-NEXT: bc 4, 20, .LBB0_24
; CHECK-NO-ISEL-NEXT: # %bb.12: # %journal_finish_inode_data_buffers.exit
-; CHECK-NO-ISEL-NEXT: bc 4, 20, .LBB0_38
+; CHECK-NO-ISEL-NEXT: bc 4, 20, .LBB0_24
; CHECK-NO-ISEL-NEXT: # %bb.13: # %if.end256
; CHECK-NO-ISEL-NEXT: cmpdi 1, 4, 0
; CHECK-NO-ISEL-NEXT: .p2align 4
; CHECK-NO-ISEL-NEXT: .LBB0_14: # %while.body318
; CHECK-NO-ISEL-NEXT: #
-; CHECK-NO-ISEL-NEXT: bc 4, 6, .LBB0_19
+; CHECK-NO-ISEL-NEXT: bc 4, 6, .LBB0_24
; CHECK-NO-ISEL-NEXT: # %bb.15: # %wait_on_buffer.exit
; CHECK-NO-ISEL-NEXT: #
; CHECK-NO-ISEL-NEXT: bc 4, 1, .LBB0_14
; CHECK-NO-ISEL-NEXT: # %bb.16: # %do.body378
-; CHECK-NO-ISEL-NEXT: bc 4, 8, .LBB0_20
-; CHECK-NO-ISEL-NEXT: # %bb.17: # %while.end418
-; CHECK-NO-ISEL-NEXT: bc 4, 8, .LBB0_25
-; CHECK-NO-ISEL-NEXT: .LBB0_18: # %if.end421
-; CHECK-NO-ISEL-NEXT: .LBB0_19: # %if.then.i1296
-; CHECK-NO-ISEL-NEXT: .LBB0_20: # %while.body392.lr.ph
+; CHECK-NO-ISEL-NEXT: bc 12, 8, .LBB0_22
+; CHECK-NO-ISEL-NEXT: # %bb.17: # %while.body392.lr.ph
; CHECK-NO-ISEL-NEXT: lis 26, 4
; CHECK-NO-ISEL-NEXT: mr 27, 5
; CHECK-NO-ISEL-NEXT: mr 28, 3
; CHECK-NO-ISEL-NEXT: .p2align 4
-; CHECK-NO-ISEL-NEXT: .LBB0_21: # %while.body392
+; CHECK-NO-ISEL-NEXT: .LBB0_18: # %while.body392
; CHECK-NO-ISEL-NEXT: #
; CHECK-NO-ISEL-NEXT: ld 3, 0(3)
; CHECK-NO-ISEL-NEXT: ldu 25, -72(3)
@@ -198,35 +178,23 @@ define void @jbd2_journal_commit_transaction(ptr %journal, i64 %inp1, i32 %inp2,
; CHECK-NO-ISEL-NEXT: std 3, 0(30)
; CHECK-NO-ISEL-NEXT: bl __brelse
; CHECK-NO-ISEL-NEXT: nop
-; CHECK-NO-ISEL-NEXT: bc 4, 9, .LBB0_21
-; CHECK-NO-ISEL-NEXT: # %bb.22: # %while.end418.loopexit
+; CHECK-NO-ISEL-NEXT: bc 4, 9, .LBB0_18
+; CHECK-NO-ISEL-NEXT: # %bb.19: # %while.end418.loopexit
; CHECK-NO-ISEL-NEXT: andi. 3, 25, 1
; CHECK-NO-ISEL-NEXT: mr 5, 27
-; CHECK-NO-ISEL-NEXT: bc 12, 1, .LBB0_24
-; CHECK-NO-ISEL-NEXT: # %bb.23: # %while.end418.loopexit
+; CHECK-NO-ISEL-NEXT: bc 12, 1, .LBB0_21
+; CHECK-NO-ISEL-NEXT: # %bb.20: # %while.end418.loopexit
; CHECK-NO-ISEL-NEXT: li 5, -5
-; CHECK-NO-ISEL-NEXT: .LBB0_24: # %while.end418.loopexit
+; CHECK-NO-ISEL-NEXT: .LBB0_21: # %while.end418.loopexit
; CHECK-NO-ISEL-NEXT: mr 3, 28
-; CHECK-NO-ISEL-NEXT: bc 12, 8, .LBB0_18
-; CHECK-NO-ISEL-NEXT: .LBB0_25: # %if.then420
+; CHECK-NO-ISEL-NEXT: .LBB0_22: # %while.end418
+; CHECK-NO-ISEL-NEXT: bc 12, 8, .LBB0_24
+; CHECK-NO-ISEL-NEXT: # %bb.23: # %if.then420
; CHECK-NO-ISEL-NEXT: extsw 4, 5
; CHECK-NO-ISEL-NEXT: bl jbd2_journal_abort
; CHECK-NO-ISEL-NEXT: nop
-; CHECK-NO-ISEL-NEXT: .LBB0_26: # %if.then5
-; CHECK-NO-ISEL-NEXT: .LBB0_27: # %do.body.i
-; CHECK-NO-ISEL-NEXT: .LBB0_28: # %do.body5.i1122
-; CHECK-NO-ISEL-NEXT: .LBB0_29: # %if.then.i.i.i.i1144
-; CHECK-NO-ISEL-NEXT: .LBB0_30: # %do.body.i1159
-; CHECK-NO-ISEL-NEXT: .LBB0_31: # %for.body.lr.ph.i
-; CHECK-NO-ISEL-NEXT: bc 4, 20, .LBB0_39
-; CHECK-NO-ISEL-NEXT: # %bb.32: # %spin_unlock.exit.i
-; CHECK-NO-ISEL-NEXT: .LBB0_33: # %if.then.i.i.i.i31.i
-; CHECK-NO-ISEL-NEXT: .LBB0_34: # %if.then102
-; CHECK-NO-ISEL-NEXT: .LBB0_35: # %do.body.i1182
-; CHECK-NO-ISEL-NEXT: .LBB0_36: # %for.body.i1277
-; CHECK-NO-ISEL-NEXT: .LBB0_37: # %if.then.i.i.i.i84.i
-; CHECK-NO-ISEL-NEXT: .LBB0_38: # %if.then249
-; CHECK-NO-ISEL-NEXT: .LBB0_39: # %if.then.i.i.i.i.i
+; CHECK-NO-ISEL-NEXT: .LBB0_24: # %if.then5
+; CHECK-NO-ISEL-NEXT: trap
ptr %inp3, ptr %inp4,
ptr %inp5, i1 %inp6,
i1 %inp7, i1 %inp8) #0 {
diff --git a/llvm/test/CodeGen/PowerPC/test-and-cmp-folding.ll b/llvm/test/CodeGen/PowerPC/test-and-cmp-folding.ll
index 0e924eabbed240..950d6244f1e827 100644
--- a/llvm/test/CodeGen/PowerPC/test-and-cmp-folding.ll
+++ b/llvm/test/CodeGen/PowerPC/test-and-cmp-folding.ll
@@ -1,53 +1,25 @@
; RUN: llc < %s -mtriple=powerpc64le-unknown-unknown -mcpu=pwr8 \
; RUN: -verify-machineinstrs | FileCheck %s
-declare void @free()
-define dso_local fastcc void @test2() {
-; CHECK-LABEL: test2
-entry:
- switch i16 undef, label %sw.default [
- i16 10, label %sw.bb52
- i16 134, label %sw.bb54
- ]
-
-sw.default: ; preds = %entry
- unreachable
-
-
-sw.bb52: ; preds = %entry, %entry, %entry, %entry, %entry, %entry
- br i1 undef, label %if.then14.i, label %sw.epilog.i642
-
-if.then14.i: ; preds = %sw.bb52
- %call39.i = call i64 @test() #3
- %and.i126.i = and i64 %call39.i, 1
- br i1 undef, label %dummy.exit.i, label %if.then.i.i.i636
+; test folding and + cmp to and + bc
-if.then.i.i.i636: ; preds = %if.then14.i
- %0 = load ptr, ptr undef, align 8
- call void @free() #3
- br label %dummy.exit.i
-
-dummy.exit.i: ; preds = %if.then.i.i.i636, %if.then14.i
-; CHECK: # %dummy.exit.i
-; CHECK-NEXT: andi.
-; CHECK-NEXT: bc 12
- %cond82.i = icmp eq i64 %and.i126.i, 0
- br i1 %cond82.i, label %if.end50.i, label %dummy.exit
-
-if.end50.i: ; preds = %dummy.exit.i
- unreachable
-
-sw.epilog.i642: ; preds = %sw.bb52
- unreachable
+; CHECK-LABEL: test
+define dso_local fastcc void @test(i64 %v1) {
+entry:
+; CHECK: andi.
+; CHECK-NEXT: bc
+ %and1 = and i64 %v1, 1
+ %cmp1 = icmp eq i64 %and1, 0
+ br i1 %cmp1, label %if.then, label %if.end
-dummy.exit: ; preds = %dummy.exit.i
- unreachable
+if.then:
+ call fastcc void @test2()
+ ret void
-sw.bb54: ; preds = %entry, %entry
+if.end:
call fastcc void @test3()
- unreachable
+ ret void
}
+declare dso_local fastcc void @test2()
declare dso_local fastcc void @test3()
-
-declare i64 @test()
diff --git a/llvm/test/CodeGen/PowerPC/trunc-srl-load.ll b/llvm/test/CodeGen/PowerPC/trunc-srl-load.ll
index dfc1bd46601ccf..fadd2c2b0002b4 100644
--- a/llvm/test/CodeGen/PowerPC/trunc-srl-load.ll
+++ b/llvm/test/CodeGen/PowerPC/trunc-srl-load.ll
@@ -1,14 +1,18 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=powerpc64-unknown-unknown %s -o - | FileCheck %s
-define dso_local fastcc void @trunc_srl_load(i32 zeroext %AttrArgNo) {
+define dso_local fastcc i32 @trunc_srl_load(i32 zeroext %AttrArgNo) {
; CHECK-LABEL: trunc_srl_load:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lhz 4, 2(0)
; CHECK-NEXT: cmplw 4, 3
; CHECK-NEXT: ble 0, .LBB0_2
; CHECK-NEXT: # %bb.1: # %exit
+; CHECK-NEXT: li 3, 1
+; CHECK-NEXT: blr
; CHECK-NEXT: .LBB0_2: # %cond.false
+; CHECK-NEXT: li 3, 2
+; CHECK-NEXT: blr
entry:
%bf.load.i = load i64, ptr null, align 8
%bf.lshr.i = lshr i64 %bf.load.i, 32
@@ -17,9 +21,9 @@ entry:
%cmp.i = icmp ugt i32 %bf.cast.i, %AttrArgNo
br i1 %cmp.i, label %exit, label %cond.false
exit: ; preds = %entry
- unreachable
+ ret i32 1
cond.false: ; preds = %entry
- unreachable
+ ret i32 2
}
define i32 @sh_trunc_sh(i64 %x) {
diff --git a/llvm/test/CodeGen/RISCV/branch_zero.ll b/llvm/test/CodeGen/RISCV/branch_zero.ll
index fd0979977ba3b3..0b9e9e500bd574 100644
--- a/llvm/test/CodeGen/RISCV/branch_zero.ll
+++ b/llvm/test/CodeGen/RISCV/branch_zero.ll
@@ -8,13 +8,13 @@ define void @foo(i16 %finder_idx) {
; CHECK-NEXT: .LBB0_1: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: slli a0, a0, 48
-; CHECK-NEXT: bltz a0, .LBB0_4
+; CHECK-NEXT: bltz a0, .LBB0_3
; CHECK-NEXT: # %bb.2: # %while.cond.preheader.i
; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1
; CHECK-NEXT: li a0, 0
; CHECK-NEXT: bnez zero, .LBB0_1
-; CHECK-NEXT: # %bb.3: # %while.body
-; CHECK-NEXT: .LBB0_4: # %while.cond1.preheader.i
+; CHECK-NEXT: .LBB0_3: # %while.cond1.preheader.i
+; CHECK-NEXT: unimp
entry:
br label %for.body
@@ -49,13 +49,13 @@ define void @bar(i16 %finder_idx) {
; CHECK-NEXT: .LBB1_1: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: slli a0, a0, 48
-; CHECK-NEXT: bgez a0, .LBB1_4
+; CHECK-NEXT: bgez a0, .LBB1_3
; CHECK-NEXT: # %bb.2: # %while.cond.preheader.i
; CHECK-NEXT: # in Loop: Header=BB1_1 Depth=1
; CHECK-NEXT: li a0, 0
; CHECK-NEXT: bnez zero, .LBB1_1
-; CHECK-NEXT: # %bb.3: # %while.body
-; CHECK-NEXT: .LBB1_4: # %while.cond1.preheader.i
+; CHECK-NEXT: .LBB1_3: # %while.cond1.preheader.i
+; CHECK-NEXT: unimp
entry:
br label %for.body
diff --git a/llvm/test/CodeGen/RISCV/double-previous-failure.ll b/llvm/test/CodeGen/RISCV/double-previous-failure.ll
index c169b1099b273a..a60dcff4a826f9 100644
--- a/llvm/test/CodeGen/RISCV/double-previous-failure.ll
+++ b/llvm/test/CodeGen/RISCV/double-previous-failure.ll
@@ -81,6 +81,5 @@ if.end:
unreachable
}
-declare void @abort()
-
-declare void @exit(i32)
+declare void @abort() noreturn
+declare void @exit(i32) noreturn
diff --git a/llvm/test/CodeGen/RISCV/machine-outliner-throw.ll b/llvm/test/CodeGen/RISCV/machine-outliner-throw.ll
index 2de29fe2fa68a9..6d08cefe3f3fc2 100644
--- a/llvm/test/CodeGen/RISCV/machine-outliner-throw.ll
+++ b/llvm/test/CodeGen/RISCV/machine-outliner-throw.ll
@@ -21,6 +21,7 @@ define i32 @func1(i32 %x) #0 {
; CHECK-NEXT: addi a1, a1, %lo(_ZTIi)
; CHECK-NEXT: li a2, 0
; CHECK-NEXT: call __cxa_throw
+; CHECK-NEXT: unimp
entry:
%mul = mul i32 %x, %x
%add = add i32 %mul, 1
@@ -48,6 +49,7 @@ define i32 @func2(i32 %x) #0 {
; CHECK-NEXT: addi a1, a1, %lo(_ZTIi)
; CHECK-NEXT: li a2, 0
; CHECK-NEXT: call __cxa_throw
+; CHECK-NEXT: unimp
entry:
%mul = mul i32 %x, %x
%add = add i32 %mul, 1
diff --git a/llvm/test/CodeGen/RISCV/miss-sp-restore-eh.ll b/llvm/test/CodeGen/RISCV/miss-sp-restore-eh.ll
index 45db5078f150c4..4c12cc4516f68e 100644
--- a/llvm/test/CodeGen/RISCV/miss-sp-restore-eh.ll
+++ b/llvm/test/CodeGen/RISCV/miss-sp-restore-eh.ll
@@ -38,6 +38,7 @@ define signext i32 @foo() #1 personality ptr @__gxx_personality_v0 {
; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: .Ltmp1:
; CHECK-NEXT: # %bb.1: # %try.cont.unreachable
+; CHECK-NEXT: unimp
; CHECK-NEXT: .LBB0_2: # %lpad
; CHECK-NEXT: .Ltmp2:
; CHECK-NEXT: sext.w a1, a1
diff --git a/llvm/test/CodeGen/RISCV/overflow-intrinsics.ll b/llvm/test/CodeGen/RISCV/overflow-intrinsics.ll
index 4bb65f376218f1..28ad0c1edbf3ca 100644
--- a/llvm/test/CodeGen/RISCV/overflow-intrinsics.ll
+++ b/llvm/test/CodeGen/RISCV/overflow-intrinsics.ll
@@ -1185,9 +1185,11 @@ end:
define void @bar() {
; RV32-LABEL: bar:
; RV32: # %bb.0:
+; RV32-NEXT: unimp
;
; RV64-LABEL: bar:
; RV64: # %bb.0:
+; RV64-NEXT: unimp
%cmp = icmp eq i64 1, -1
%frombool = zext i1 %cmp to i8
unreachable
@@ -1196,9 +1198,11 @@ define void @bar() {
define void @foo() {
; RV32-LABEL: foo:
; RV32: # %bb.0:
+; RV32-NEXT: unimp
;
; RV64-LABEL: foo:
; RV64: # %bb.0:
+; RV64-NEXT: unimp
%sub = add nsw i64 1, 1
%conv = trunc i64 %sub to i32
unreachable
diff --git a/llvm/test/CodeGen/SPARC/empty-functions.ll b/llvm/test/CodeGen/SPARC/empty-functions.ll
index 797bbdad54e6b4..40a64501d1be52 100644
--- a/llvm/test/CodeGen/SPARC/empty-functions.ll
+++ b/llvm/test/CodeGen/SPARC/empty-functions.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -mtriple=sparc-linux-gnu | FileCheck -check-prefix=LINUX-NO-FP %s
-; RUN: llc < %s -mtriple=sparc-linux-gnu -frame-pointer=all | FileCheck -check-prefix=LINUX-FP %s
+; RUN: llc < %s -trap-unreachable=false -mtriple=sparc-linux-gnu | FileCheck -check-prefix=LINUX-NO-FP %s
+; RUN: llc < %s -trap-unreachable=false -mtriple=sparc-linux-gnu -frame-pointer=all | FileCheck -check-prefix=LINUX-FP %s
define void @func() {
entry:
diff --git a/llvm/test/CodeGen/SPARC/missinglabel.ll b/llvm/test/CodeGen/SPARC/missinglabel.ll
index e29f5ba3444406..c0b11939e460d8 100644
--- a/llvm/test/CodeGen/SPARC/missinglabel.ll
+++ b/llvm/test/CodeGen/SPARC/missinglabel.ll
@@ -11,12 +11,10 @@ define void @f(i64 %a0) align 2 {
; CHECK-NEXT: brz %o0, .LBB0_2
; CHECK-NEXT: nop
; CHECK-NEXT: ! %bb.1: ! %cond.false
+; CHECK-NEXT: ta 5
; CHECK-NEXT: .LBB0_2: ! %targetblock
; CHECK-NEXT: cmp %g0, 0
-; CHECK-NEXT: bne %icc, .LBB0_4
-; CHECK-NEXT: nop
-; CHECK-NEXT: ! %bb.3: ! %cond.false.i83
-; CHECK-NEXT: .LBB0_4: ! %exit.i85
+; CHECK-NEXT: ta 5
entry:
%cmp = icmp eq i64 %a0, 0
br i1 %cmp, label %targetblock, label %cond.false
diff --git a/llvm/test/CodeGen/SystemZ/buildvector-00.ll b/llvm/test/CodeGen/SystemZ/buildvector-00.ll
index 00c9f02070cf52..ddc3f90a3f45c2 100644
--- a/llvm/test/CodeGen/SystemZ/buildvector-00.ll
+++ b/llvm/test/CodeGen/SystemZ/buildvector-00.ll
@@ -17,7 +17,8 @@ define void @f1(<2 x i64> %a0) {
; CHECK-NEXT: vnc %v0, %v2, %v0
; CHECK-NEXT: vlgvf %r0, %v0, 1
; CHECK-NEXT: tmll %r0, 1
-; CHECK-NEXT: # %bb.1: # %bb15
+; CHECK-NEXT: .Ltmp0:
+; CHECK-NEXT: j .Ltmp0+2
bb:
%tmp = shufflevector <2 x i64> undef, <2 x i64> undef, <2 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/SystemZ/knownbits.ll b/llvm/test/CodeGen/SystemZ/knownbits.ll
index a85c9397975184..aa469618906771 100644
--- a/llvm/test/CodeGen/SystemZ/knownbits.ll
+++ b/llvm/test/CodeGen/SystemZ/knownbits.ll
@@ -44,12 +44,11 @@ define void @f1(i64 %a0, i64 %a1) {
; CHECK-NEXT: vrepig %v1, 1
; CHECK-NEXT: vx %v0, %v0, %v1
; CHECK-NEXT: vlgvg %r0, %v0, 0
-; CHECK-NEXT: cgijlh %r0, 0, .LBB1_3
-; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: cgiblh %r0, 0, 0(%r14)
+; CHECK-NEXT: .LBB1_1:
; CHECK-NEXT: vlgvg %r0, %v0, 1
-; CHECK-NEXT: cgijlh %r0, 0, .LBB1_3
-; CHECK-NEXT: # %bb.2:
-; CHECK-NEXT: .LBB1_3:
+; CHECK-NEXT: cghi %r0, 0
+; CHECK-NEXT: br %r14
%1 = and i64 %a0, 1
%2 = and i64 %a1, 1
%3 = insertelement <2 x i64> undef, i64 %1, i32 0
@@ -67,8 +66,8 @@ define void @f1(i64 %a0, i64 %a1) {
br i1 %12, label %13, label %14
; <label>:13: ; preds = %0
- unreachable
+ ret void
; <label>:14: ; preds = %0
- unreachable
+ ret void
}
diff --git a/llvm/test/CodeGen/SystemZ/pr47019.ll b/llvm/test/CodeGen/SystemZ/pr47019.ll
index 19ff67a53b105b..613c8b3eb4c90b 100644
--- a/llvm/test/CodeGen/SystemZ/pr47019.ll
+++ b/llvm/test/CodeGen/SystemZ/pr47019.ll
@@ -13,6 +13,8 @@ define dso_local void @main() local_unnamed_addr {
; CHECK-NEXT: strl %r0, g_317+296
; CHECK-NEXT: lhi %r0, 6
; CHECK-NEXT: strl %r0, g_150+12
+; CHECK-NEXT: .Ltmp0:
+; CHECK-NEXT: j .Ltmp0+2
bb:
br label %bb1
diff --git a/llvm/test/CodeGen/SystemZ/soft-float-04.ll b/llvm/test/CodeGen/SystemZ/soft-float-04.ll
index 1dbe843090b040..12e9258eb154f1 100644
--- a/llvm/test/CodeGen/SystemZ/soft-float-04.ll
+++ b/llvm/test/CodeGen/SystemZ/soft-float-04.ll
@@ -3,7 +3,7 @@
; Check that this function with soft-float does not result in a s390.tdc
; intrinsic (which cannot be handled by SoftenFloatOperand).
-define void @fun(float %arg) {
+define i32 @fun(float %arg) {
; CHECK-LABEL: fun:
; CHECK: cijl
bb:
@@ -15,8 +15,8 @@ bb1: ; preds = %bb
br i1 %tmp2, label %bb3, label %bb4
bb3: ; preds = %bb1
- unreachable
+ ret i32 1
bb4: ; preds = %bb1
- unreachable
+ ret i32 2
}
diff --git a/llvm/test/CodeGen/SystemZ/vec-perm-14.ll b/llvm/test/CodeGen/SystemZ/vec-perm-14.ll
index 0b392676fa3ec3..e0aa59550eaaf4 100644
--- a/llvm/test/CodeGen/SystemZ/vec-perm-14.ll
+++ b/llvm/test/CodeGen/SystemZ/vec-perm-14.ll
@@ -1,7 +1,7 @@
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s
; Test that no vperm of the vector compare is needed for the extracts.
-define void @fun() {
+define i32 @fun() {
; CHECK-LABEL: fun:
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: vlrepf %v0, 0(%r1)
@@ -13,11 +13,15 @@ define void @fun() {
; CHECK-NEXT: tmll %r0, 1
; CHECK-NEXT: je .LBB0_2
; CHECK-NEXT: # %bb.1: # %bb1
+; CHECK-NEXT: lhi %r2, 1
+; CHECK-NEXT: br %r14
; CHECK-NEXT: .LBB0_2: # %bb2
; CHECK-NEXT: vlgvf %r0, %v0, 1
; CHECK-NEXT: tmll %r0, 1
; CHECK-NEXT: je .LBB0_4
; CHECK-NEXT: # %bb.3: # %bb3
+; CHECK-NEXT: lhi %r2, 2
+; CHECK-NEXT: br %r14
; CHECK-NEXT: .LBB0_4: # %bb4
bb:
%tmp = load <4 x i8>, ptr undef
@@ -26,17 +30,17 @@ bb:
br i1 %tmp2, label %bb1, label %bb2
bb1:
- unreachable
+ ret i32 1
bb2:
%tmp3 = extractelement <4 x i1> %tmp1, i32 1
br i1 %tmp3, label %bb3, label %bb4
bb3:
- unreachable
+ ret i32 2
bb4:
- unreachable
+ ret i32 3
}
; Test that a zero index in the permute vector is used instead of VGBM, with
diff --git a/llvm/test/CodeGen/VE/Vector/ticket-64420.ll b/llvm/test/CodeGen/VE/Vector/ticket-64420.ll
index c3fe443f911c9f..7c4b8ad9f94d33 100644
--- a/llvm/test/CodeGen/VE/Vector/ticket-64420.ll
+++ b/llvm/test/CodeGen/VE/Vector/ticket-64420.ll
@@ -9,17 +9,16 @@
; https://github.com/llvm/llvm-project/issues/64420
; CHECK-LABEL: func:
-; CHECK: # %bb.1:
+; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v0, 0
; CHECK-NEXT: or %s1, 4, (0)1
; CHECK-NEXT: lvl %s1
-; CHECK-NEXT: vstl %v0, 4, %s0
-; CHECK-NEXT: b.l.t (, %s10)
; SCALAR-LABEL: func:
-; SCALAR: # %bb.1:
+; SCALAR: # %bb.0:
+; SCALAR-NEXT: or %s1, 0, (0)1
; SCALAR-NEXT: st %s1, 8(, %s0)
; SCALAR-NEXT: st %s1, (, %s0)
; SCALAR-NEXT: b.l.t (, %s10)
@@ -31,14 +30,8 @@ target triple = "ve-unknown-linux-gnu"
define dso_local void @func(ptr %_0) unnamed_addr #0 {
start:
- br i1 poison, label %bb7, label %panic3
-
-bb7: ; preds = %start
store <4 x i32> zeroinitializer, ptr %_0, align 4
ret void
-
-panic3: ; preds = %start
- unreachable
}
attributes #0 = { "target-features"="+vpu" }
diff --git a/llvm/test/CodeGen/WinEH/wineh-empty-seh-scope.ll b/llvm/test/CodeGen/WinEH/wineh-empty-seh-scope.ll
index 5f382f10f180bc..b64f95b233074c 100644
--- a/llvm/test/CodeGen/WinEH/wineh-empty-seh-scope.ll
+++ b/llvm/test/CodeGen/WinEH/wineh-empty-seh-scope.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=x86_64-pc-windows-msvc19.41.34120 < %s | FileCheck %s
+; RUN: llc -trap-unreachable=false -mtriple=x86_64-pc-windows-msvc19.41.34120 < %s | FileCheck %s
define void @foo() personality ptr @__CxxFrameHandler3 {
; CHECK-LABEL: foo:
diff --git a/llvm/test/CodeGen/WinEH/wineh-noret-cleanup.ll b/llvm/test/CodeGen/WinEH/wineh-noret-cleanup.ll
index e42b005cf64bdb..2e155bbb76a712 100644
--- a/llvm/test/CodeGen/WinEH/wineh-noret-cleanup.ll
+++ b/llvm/test/CodeGen/WinEH/wineh-noret-cleanup.ll
@@ -68,13 +68,13 @@ catch.body.2:
; SEH-NEXT: .long .Ltmp0 at IMGREL
; SEH-NEXT: .long .Ltmp1 at IMGREL+1
; SEH-NEXT: .long dummy_filter at IMGREL
-; SEH-NEXT: .long .LBB0_5 at IMGREL
+; SEH-NEXT: .long .LBB0_2 at IMGREL
; SEH-NEXT: .long .Ltmp2 at IMGREL
; SEH-NEXT: .long .Ltmp3 at IMGREL+1
-; SEH-NEXT: .long "?dtor$2@?0?test at 4HA"@IMGREL
+; SEH-NEXT: .long "?dtor$5@?0?test at 4HA"@IMGREL
; SEH-NEXT: .long 0
; SEH-NEXT: .long .Ltmp2 at IMGREL
; SEH-NEXT: .long .Ltmp3 at IMGREL+1
; SEH-NEXT: .long dummy_filter at IMGREL
-; SEH-NEXT: .long .LBB0_5 at IMGREL
+; SEH-NEXT: .long .LBB0_2 at IMGREL
; SEH-NEXT: .Llsda_end0:
diff --git a/llvm/test/CodeGen/X86/2008-05-21-CoalescerBug.ll b/llvm/test/CodeGen/X86/2008-05-21-CoalescerBug.ll
index 58d626f5866e78..91b564575cbefe 100644
--- a/llvm/test/CodeGen/X86/2008-05-21-CoalescerBug.ll
+++ b/llvm/test/CodeGen/X86/2008-05-21-CoalescerBug.ll
@@ -98,6 +98,7 @@ define ptr @tree_redirect_edge_and_branch(ptr %e1, ptr %dest2) nounwind {
; CHECK-NEXT: movl $0, (%esi)
; CHECK-NEXT: jmp .LBB0_5
; CHECK-NEXT: .LBB0_5: # %bb841
+; CHECK-NEXT: ud2
entry:
br label %bb497
diff --git a/llvm/test/CodeGen/X86/2008-06-25-VecISelBug.ll b/llvm/test/CodeGen/X86/2008-06-25-VecISelBug.ll
index d56f526cd156a8..a82f01f5dff9e1 100644
--- a/llvm/test/CodeGen/X86/2008-06-25-VecISelBug.ll
+++ b/llvm/test/CodeGen/X86/2008-06-25-VecISelBug.ll
@@ -6,6 +6,7 @@ define void @t() nounwind {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movaps {{.*#+}} xmm0 = [0.0E+0,0.0E+0,0.0E+0,1.0E+0]
; CHECK-NEXT: movaps %xmm0, 0
+; CHECK-NEXT: ud2
entry:
%tmp1 = shufflevector <4 x float> zeroinitializer, <4 x float> < float 0.000000e+00, float 1.000000e+00, float 0.000000e+00, float 1.000000e+00 >, <4 x i32> < i32 0, i32 1, i32 4, i32 5 >
%tmp2 = insertelement <4 x float> %tmp1, float 1.000000e+00, i32 3
diff --git a/llvm/test/CodeGen/X86/2010-02-23-DAGCombineBug.ll b/llvm/test/CodeGen/X86/2010-02-23-DAGCombineBug.ll
index 2fde534560b25d..5153deef6c180c 100644
--- a/llvm/test/CodeGen/X86/2010-02-23-DAGCombineBug.ll
+++ b/llvm/test/CodeGen/X86/2010-02-23-DAGCombineBug.ll
@@ -9,6 +9,7 @@ define ptr @t(i32 %a0) nounwind optsize ssp {
; CHECK-NEXT: # %bb.1: # %if.then27
; CHECK-NEXT: retl
; CHECK-NEXT: .LBB0_2: # %if.else29
+; CHECK-NEXT: ud2
entry:
%cmp = icmp slt i32 %a0, 0 ; <i1> [#uses=1]
%outsearch.0 = select i1 %cmp, i1 false, i1 true ; <i1> [#uses=1]
diff --git a/llvm/test/CodeGen/X86/PR40322.ll b/llvm/test/CodeGen/X86/PR40322.ll
index 49709cb9b88f88..dd84e573543dbd 100644
--- a/llvm/test/CodeGen/X86/PR40322.ll
+++ b/llvm/test/CodeGen/X86/PR40322.ll
@@ -72,16 +72,17 @@ define void @_Z2ami(i32) #0 personality ptr @__gxx_personality_v0 {
; CHECK-MINGW-X86-NEXT: addl $12, %esp
; CHECK-MINGW-X86-NEXT: .cfi_adjust_cfa_offset -12
; CHECK-MINGW-X86-NEXT: Ltmp4:
-; CHECK-MINGW-X86-NEXT: # %bb.8: # %unreachable
-; CHECK-MINGW-X86-NEXT: LBB0_5: # %lpad
+; CHECK-MINGW-X86-NEXT: # %bb.5: # %unreachable
+; CHECK-MINGW-X86-NEXT: ud2
+; CHECK-MINGW-X86-NEXT: LBB0_6: # %lpad
; CHECK-MINGW-X86-NEXT: Ltmp2:
; CHECK-MINGW-X86-NEXT: movl %eax, %edi
; CHECK-MINGW-X86-NEXT: .cfi_escape 0x2e, 0x04
; CHECK-MINGW-X86-NEXT: pushl $__ZGVZ2amiE2au
; CHECK-MINGW-X86-NEXT: .cfi_adjust_cfa_offset 4
; CHECK-MINGW-X86-NEXT: calll ___cxa_guard_abort
-; CHECK-MINGW-X86-NEXT: jmp LBB0_7
-; CHECK-MINGW-X86-NEXT: LBB0_6: # %lpad1
+; CHECK-MINGW-X86-NEXT: jmp LBB0_8
+; CHECK-MINGW-X86-NEXT: LBB0_7: # %lpad1
; CHECK-MINGW-X86-NEXT: .cfi_def_cfa_offset 12
; CHECK-MINGW-X86-NEXT: Ltmp5:
; CHECK-MINGW-X86-NEXT: movl %eax, %edi
@@ -89,7 +90,7 @@ define void @_Z2ami(i32) #0 personality ptr @__gxx_personality_v0 {
; CHECK-MINGW-X86-NEXT: pushl %esi
; CHECK-MINGW-X86-NEXT: .cfi_adjust_cfa_offset 4
; CHECK-MINGW-X86-NEXT: calll __ZdlPv
-; CHECK-MINGW-X86-NEXT: LBB0_7: # %eh.resume
+; CHECK-MINGW-X86-NEXT: LBB0_8: # %eh.resume
; CHECK-MINGW-X86-NEXT: addl $4, %esp
; CHECK-MINGW-X86-NEXT: .cfi_adjust_cfa_offset -4
; CHECK-MINGW-X86-NEXT: .cfi_escape 0x2e, 0x04
diff --git a/llvm/test/CodeGen/X86/atomic-bit-test.ll b/llvm/test/CodeGen/X86/atomic-bit-test.ll
index 10b6605c3fb05e..0e8f606ef7252a 100644
--- a/llvm/test/CodeGen/X86/atomic-bit-test.ll
+++ b/llvm/test/CodeGen/X86/atomic-bit-test.ll
@@ -541,6 +541,7 @@ define void @no_and_cmp0_fold() nounwind {
; X86-NEXT: # %bb.2: # %if.end
; X86-NEXT: retl
; X86-NEXT: .LBB18_1: # %if.then
+; X86-NEXT: ud2
;
; X64-LABEL: no_and_cmp0_fold:
; X64: # %bb.0: # %entry
@@ -551,6 +552,7 @@ define void @no_and_cmp0_fold() nounwind {
; X64-NEXT: # %bb.2: # %if.end
; X64-NEXT: retq
; X64-NEXT: .LBB18_1: # %if.then
+; X64-NEXT: ud2
entry:
%0 = atomicrmw or ptr @v32, i32 8 monotonic, align 4
%and = and i32 %0, 8
diff --git a/llvm/test/CodeGen/X86/avx-load-store.ll b/llvm/test/CodeGen/X86/avx-load-store.ll
index 3f856d33145d86..b7e38798024936 100644
--- a/llvm/test/CodeGen/X86/avx-load-store.ll
+++ b/llvm/test/CodeGen/X86/avx-load-store.ll
@@ -110,11 +110,13 @@ define void @storev16i16(<16 x i16> %a) nounwind {
; CHECK-LABEL: storev16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovaps %ymm0, (%rax)
+; CHECK-NEXT: ud2
;
; CHECK_O0-LABEL: storev16i16:
; CHECK_O0: # %bb.0:
; CHECK_O0-NEXT: # implicit-def: $rax
-; CHECK_O0-NEXT: vmovdqa %ymm0, (%rax)
+; CHECK_O0-NEXT: vmovaps %ymm0, (%rax)
+; CHECK_O0-NEXT: ud2
store <16 x i16> %a, ptr undef, align 32
unreachable
}
@@ -124,11 +126,16 @@ define void @storev16i16_01(<16 x i16> %a) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: vextractf128 $1, %ymm0, (%rax)
; CHECK-NEXT: vmovups %xmm0, (%rax)
+; CHECK-NEXT: ud2
;
; CHECK_O0-LABEL: storev16i16_01:
; CHECK_O0: # %bb.0:
; CHECK_O0-NEXT: # implicit-def: $rax
-; CHECK_O0-NEXT: vmovdqu %ymm0, (%rax)
+; CHECK_O0-NEXT: vextractf128 $1, %ymm0, (%rax)
+; CHECK_O0-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
+; CHECK_O0-NEXT: # implicit-def: $rax
+; CHECK_O0-NEXT: vmovdqu %xmm0, (%rax)
+; CHECK_O0-NEXT: ud2
store <16 x i16> %a, ptr undef, align 4
unreachable
}
@@ -137,11 +144,13 @@ define void @storev32i8(<32 x i8> %a) nounwind {
; CHECK-LABEL: storev32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovaps %ymm0, (%rax)
+; CHECK-NEXT: ud2
;
; CHECK_O0-LABEL: storev32i8:
; CHECK_O0: # %bb.0:
; CHECK_O0-NEXT: # implicit-def: $rax
-; CHECK_O0-NEXT: vmovdqa %ymm0, (%rax)
+; CHECK_O0-NEXT: vmovaps %ymm0, (%rax)
+; CHECK_O0-NEXT: ud2
store <32 x i8> %a, ptr undef, align 32
unreachable
}
@@ -151,11 +160,16 @@ define void @storev32i8_01(<32 x i8> %a) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: vextractf128 $1, %ymm0, (%rax)
; CHECK-NEXT: vmovups %xmm0, (%rax)
+; CHECK-NEXT: ud2
;
; CHECK_O0-LABEL: storev32i8_01:
; CHECK_O0: # %bb.0:
; CHECK_O0-NEXT: # implicit-def: $rax
-; CHECK_O0-NEXT: vmovdqu %ymm0, (%rax)
+; CHECK_O0-NEXT: vextractf128 $1, %ymm0, (%rax)
+; CHECK_O0-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
+; CHECK_O0-NEXT: # implicit-def: $rax
+; CHECK_O0-NEXT: vmovdqu %xmm0, (%rax)
+; CHECK_O0-NEXT: ud2
store <32 x i8> %a, ptr undef, align 4
unreachable
}
@@ -213,16 +227,16 @@ define void @f_f() nounwind {
; CHECK: # %bb.0: # %allocas
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al
-; CHECK-NEXT: jne .LBB9_2
-; CHECK-NEXT: # %bb.1: # %cif_mask_all
-; CHECK-NEXT: .LBB9_2: # %cif_mask_mixed
+; CHECK-NEXT: je .LBB9_3
+; CHECK-NEXT: # %bb.1: # %cif_mask_mixed
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al
-; CHECK-NEXT: jne .LBB9_4
-; CHECK-NEXT: # %bb.3: # %cif_mixed_test_all
+; CHECK-NEXT: jne .LBB9_3
+; CHECK-NEXT: # %bb.2: # %cif_mixed_test_all
; CHECK-NEXT: vmovss {{.*#+}} xmm0 = [4294967295,0,0,0]
; CHECK-NEXT: vmaskmovps %ymm0, %ymm0, (%rax)
-; CHECK-NEXT: .LBB9_4: # %cif_mixed_test_any_check
+; CHECK-NEXT: .LBB9_3: # %cif_mask_all
+; CHECK-NEXT: ud2
;
; CHECK_O0-LABEL: f_f:
; CHECK_O0: # %bb.0: # %allocas
@@ -231,6 +245,7 @@ define void @f_f() nounwind {
; CHECK_O0-NEXT: jne .LBB9_1
; CHECK_O0-NEXT: jmp .LBB9_2
; CHECK_O0-NEXT: .LBB9_1: # %cif_mask_all
+; CHECK_O0-NEXT: ud2
; CHECK_O0-NEXT: .LBB9_2: # %cif_mask_mixed
; CHECK_O0-NEXT: # implicit-def: $al
; CHECK_O0-NEXT: testb $1, %al
@@ -243,7 +258,9 @@ define void @f_f() nounwind {
; CHECK_O0-NEXT: # implicit-def: $rax
; CHECK_O0-NEXT: # implicit-def: $ymm1
; CHECK_O0-NEXT: vmaskmovps %ymm1, %ymm0, (%rax)
+; CHECK_O0-NEXT: ud2
; CHECK_O0-NEXT: .LBB9_4: # %cif_mixed_test_any_check
+; CHECK_O0-NEXT: ud2
allocas:
br i1 undef, label %cif_mask_all, label %cif_mask_mixed
diff --git a/llvm/test/CodeGen/X86/basic-block-sections-labels-empty-block.ll b/llvm/test/CodeGen/X86/basic-block-sections-labels-empty-block.ll
index 8e0f4fa7bc928e..80e4a0cb25d06d 100644
--- a/llvm/test/CodeGen/X86/basic-block-sections-labels-empty-block.ll
+++ b/llvm/test/CodeGen/X86/basic-block-sections-labels-empty-block.ll
@@ -1,5 +1,5 @@
;; This test verifies that with -gc-empty-basic-blocks SHT_LLVM_BB_ADDR_MAP will not include entries for empty blocks.
-; RUN: llc < %s -mtriple=x86_64 -O0 -basic-block-sections=labels -gc-empty-basic-blocks | FileCheck --check-prefix=CHECK %s
+; RUN: llc < %s -mtriple=x86_64 -trap-unreachable=false -O0 -basic-block-sections=labels -gc-empty-basic-blocks | FileCheck --check-prefix=CHECK %s
define void @foo(i1 zeroext %0) nounwind {
br i1 %0, label %2, label %empty_block
diff --git a/llvm/test/CodeGen/X86/basic-block-sections-labels-empty-function.ll b/llvm/test/CodeGen/X86/basic-block-sections-labels-empty-function.ll
index 42d09212e66916..c6a8bb68d4a954 100644
--- a/llvm/test/CodeGen/X86/basic-block-sections-labels-empty-function.ll
+++ b/llvm/test/CodeGen/X86/basic-block-sections-labels-empty-function.ll
@@ -1,6 +1,7 @@
;; Verify that the BB address map is not emitted for empty functions.
-; RUN: llc < %s -mtriple=x86_64 -basic-block-sections=labels | FileCheck %s --check-prefixes=CHECK,BASIC
-; RUN: llc < %s -mtriple=x86_64 -basic-block-sections=labels -pgo-analysis-map=func-entry-count,bb-freq | FileCheck %s --check-prefixes=CHECK,PGO
+;; Set trap-unreachable to false so that we test this behavior correctly.
+; RUN: llc < %s -mtriple=x86_64 -trap-unreachable=false -basic-block-sections=labels | FileCheck %s --check-prefixes=CHECK,BASIC
+; RUN: llc < %s -mtriple=x86_64 -trap-unreachable=false -basic-block-sections=labels -pgo-analysis-map=func-entry-count,bb-freq | FileCheck %s --check-prefixes=CHECK,PGO
define void @empty_func() {
entry:
diff --git a/llvm/test/CodeGen/X86/br-fold.ll b/llvm/test/CodeGen/X86/br-fold.ll
index fb37d0d4a49aa7..614a9651da6ecf 100644
--- a/llvm/test/CodeGen/X86/br-fold.ll
+++ b/llvm/test/CodeGen/X86/br-fold.ll
@@ -8,15 +8,13 @@
; X64_DARWIN-NEXT: ud2
; X64_LINUX: orq _ZN11xercesc_2_56XMLUni16fgNotationStringE at GOTPCREL(%rip), %rax
-; X64_LINUX-NEXT: je
-; X64_LINUX-NEXT: %bb4.i.i318.preheader
+; X64_LINUX-NEXT: ud2
; X64_WINDOWS: orq %rax, %rcx
-; X64_WINDOWS-NEXT: je
+; X64_WINDOWS-NEXT: ud2
-; X64_WINDOWS_GNU: movq .refptr._ZN11xercesc_2_513SchemaSymbols21fgURI_SCHEMAFORSCHEMAE(%rip), %rax
; X64_WINDOWS_GNU: orq .refptr._ZN11xercesc_2_56XMLUni16fgNotationStringE(%rip), %rax
-; X64_WINDOWS_GNU-NEXT: je
+; X64_WINDOWS_GNU-NEXT: ud2
; PS4: orq _ZN11xercesc_2_56XMLUni16fgNotationStringE at GOTPCREL(%rip), %rax
; PS4-NEXT: ud2
diff --git a/llvm/test/CodeGen/X86/coalescer-add-implicit-def-subreg-to-reg-regression.ll b/llvm/test/CodeGen/X86/coalescer-add-implicit-def-subreg-to-reg-regression.ll
index 0e6cb7a3aff2ee..3752a5281d58f9 100644
--- a/llvm/test/CodeGen/X86/coalescer-add-implicit-def-subreg-to-reg-regression.ll
+++ b/llvm/test/CodeGen/X86/coalescer-add-implicit-def-subreg-to-reg-regression.ll
@@ -20,6 +20,7 @@ define void @other_regression(i1 %cmp.not.i.i.i) {
; CHECK-NEXT: xorl %edi, %edi
; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: callq *%rax
+; CHECK-NEXT: ud2
entry:
br label %for.cond10.preheader
diff --git a/llvm/test/CodeGen/X86/combine-concatvectors.ll b/llvm/test/CodeGen/X86/combine-concatvectors.ll
index 230afd1461935d..72977b1ac3aca9 100644
--- a/llvm/test/CodeGen/X86/combine-concatvectors.ll
+++ b/llvm/test/CodeGen/X86/combine-concatvectors.ll
@@ -28,6 +28,7 @@ define void @d(i1 %cmp) {
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq fun at PLT
+; CHECK-NEXT: ud2
bar:
%val = call { i8, double } @fun()
%extr = extractvalue { i8, double } %val, 1
diff --git a/llvm/test/CodeGen/X86/combineIncDecVector-crash.ll b/llvm/test/CodeGen/X86/combineIncDecVector-crash.ll
index 2d6ce2017dc0dc..d9b073dffb7acf 100644
--- a/llvm/test/CodeGen/X86/combineIncDecVector-crash.ll
+++ b/llvm/test/CodeGen/X86/combineIncDecVector-crash.ll
@@ -25,6 +25,7 @@ define void @TestvMeth(i32 %0, i64 %1) gc "statepoint-example" !prof !1 {
; CHECK-NEXT: psubd %xmm2, %xmm1
; CHECK-NEXT: movdqu %xmm1, (%rax)
; CHECK-NEXT: movss %xmm0, (%rax)
+; CHECK-NEXT: ud2
bci_0:
%token418 = call token (i64, i32, ptr, i32,
i32, ...) @llvm.experimental.gc.statepoint.p0(i64
diff --git a/llvm/test/CodeGen/X86/concat-fpext-v2bf16.ll b/llvm/test/CodeGen/X86/concat-fpext-v2bf16.ll
index c079a44bc5efd5..bad08612d9c0d5 100644
--- a/llvm/test/CodeGen/X86/concat-fpext-v2bf16.ll
+++ b/llvm/test/CodeGen/X86/concat-fpext-v2bf16.ll
@@ -16,6 +16,7 @@ define void @test(<2 x ptr> %ptr) {
; CHECK-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3]
; CHECK-NEXT: vmulps %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vmovlps %xmm0, (%rax)
+; CHECK-NEXT: ud2
entry:
br label %then.13
diff --git a/llvm/test/CodeGen/X86/empty-function.ll b/llvm/test/CodeGen/X86/empty-function.ll
index 7d908311ec8dc5..56dc6066d756f9 100644
--- a/llvm/test/CodeGen/X86/empty-function.ll
+++ b/llvm/test/CodeGen/X86/empty-function.ll
@@ -1,6 +1,6 @@
-; RUN: llc < %s -mtriple=i686-pc-win32 | FileCheck -check-prefix=CHECK -check-prefix=WIN32 %s
-; RUN: llc < %s -mtriple=x86_64-pc-win32 | FileCheck -check-prefix=CHECK -check-prefix=WIN64 %s
-; RUN: llc < %s -mtriple=i386-linux-gnu | FileCheck -check-prefix=LINUX %s
+; RUN: llc < %s -mtriple=i686-pc-win32 -trap-unreachable=false | FileCheck -check-prefix=CHECK -check-prefix=WIN32 %s
+; RUN: llc < %s -mtriple=x86_64-pc-win32 -trap-unreachable=false | FileCheck -check-prefix=CHECK -check-prefix=WIN64 %s
+; RUN: llc < %s -mtriple=i386-linux-gnu -trap-unreachable=false | FileCheck -check-prefix=LINUX %s
target datalayout = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"
target triple = "i686-pc-windows-msvc18.0.0"
diff --git a/llvm/test/CodeGen/X86/empty-functions.ll b/llvm/test/CodeGen/X86/empty-functions.ll
index faded65ac6dc5f..60857e6335c49f 100644
--- a/llvm/test/CodeGen/X86/empty-functions.ll
+++ b/llvm/test/CodeGen/X86/empty-functions.ll
@@ -1,7 +1,7 @@
; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck -check-prefix=CHECK-NO-FP %s
; RUN: llc < %s -mtriple=x86_64-apple-darwin -frame-pointer=all | FileCheck -check-prefix=CHECK-FP %s
-; RUN: llc < %s -mtriple=x86_64-linux-gnu | FileCheck -check-prefix=LINUX-NO-FP %s
-; RUN: llc < %s -mtriple=x86_64-linux-gnu -frame-pointer=all | FileCheck -check-prefix=LINUX-FP %s
+; RUN: llc < %s -trap-unreachable=false -mtriple=x86_64-linux-gnu | FileCheck -check-prefix=LINUX-NO-FP %s
+; RUN: llc < %s -trap-unreachable=false -mtriple=x86_64-linux-gnu -frame-pointer=all | FileCheck -check-prefix=LINUX-FP %s
define void @func() {
entry:
diff --git a/llvm/test/CodeGen/X86/extract-combine.ll b/llvm/test/CodeGen/X86/extract-combine.ll
index 7d2ce84c56bae2..9db5201ed7e184 100644
--- a/llvm/test/CodeGen/X86/extract-combine.ll
+++ b/llvm/test/CodeGen/X86/extract-combine.ll
@@ -6,6 +6,7 @@ define i32 @foo() nounwind {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xorps %xmm0, %xmm0
; CHECK-NEXT: movaps %xmm0, 0
+; CHECK-NEXT: ud2
entry:
%tmp74.i25762 = shufflevector <16 x float> zeroinitializer, <16 x float> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 18, i32 19> ; <<16 x float>> [#uses=1]
%tmp518 = shufflevector <16 x float> %tmp74.i25762, <16 x float> undef, <4 x i32> <i32 12, i32 13, i32 14, i32 15> ; <<4 x float>> [#uses=1]
diff --git a/llvm/test/CodeGen/X86/gc-empty-basic-blocks.ll b/llvm/test/CodeGen/X86/gc-empty-basic-blocks.ll
index 54ed34b2eae4e5..3a96d8ae4bcc4a 100644
--- a/llvm/test/CodeGen/X86/gc-empty-basic-blocks.ll
+++ b/llvm/test/CodeGen/X86/gc-empty-basic-blocks.ll
@@ -1,6 +1,6 @@
;; This test verifies that -gc-empty-basic-blocks removes regular empty blocks
;; but does not remove empty blocks which have their address taken.
-; RUN: llc < %s -mtriple=x86_64 -O0 -gc-empty-basic-blocks | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64 -O0 -gc-empty-basic-blocks -trap-unreachable=false | FileCheck %s
;; This function has a regular empty block.
define void @foo(i1 zeroext %0) nounwind {
diff --git a/llvm/test/CodeGen/X86/inline-spiller-impdef-on-implicit-def-regression.ll b/llvm/test/CodeGen/X86/inline-spiller-impdef-on-implicit-def-regression.ll
index f42c2f8f144763..d1c1fb0710787b 100644
--- a/llvm/test/CodeGen/X86/inline-spiller-impdef-on-implicit-def-regression.ll
+++ b/llvm/test/CodeGen/X86/inline-spiller-impdef-on-implicit-def-regression.ll
@@ -33,7 +33,7 @@ define i32 @decode_sb(ptr %t, i32 %bl, i32 %_msprop1966, i32 %sub.i, i64 %idxpro
; CHECK-NEXT: movl %esi, %r15d
; CHECK-NEXT: # implicit-def: $r12d
; CHECK-NEXT: testb $1, %bl
-; CHECK-NEXT: jne .LBB0_6
+; CHECK-NEXT: jne .LBB0_5
; CHECK-NEXT: # %bb.1: # %if.else
; CHECK-NEXT: movl %ecx, %r12d
; CHECK-NEXT: andl $1, %r12d
@@ -73,13 +73,13 @@ define i32 @decode_sb(ptr %t, i32 %bl, i32 %_msprop1966, i32 %sub.i, i64 %idxpro
; CHECK-NEXT: callq *%rax
; CHECK-NEXT: movb $1, %al
; CHECK-NEXT: testb %al, %al
-; CHECK-NEXT: je .LBB0_4
-; CHECK-NEXT: # %bb.5: # %bb19
+; CHECK-NEXT: je .LBB0_7
+; CHECK-NEXT: # %bb.4: # %bb19
; CHECK-NEXT: testb $1, %bl
; CHECK-NEXT: movq %r14, %rdi
; CHECK-NEXT: movabsq $87960930222080, %r14 # imm = 0x500000000000
-; CHECK-NEXT: jne .LBB0_7
-; CHECK-NEXT: .LBB0_6: # %if.end69
+; CHECK-NEXT: jne .LBB0_6
+; CHECK-NEXT: .LBB0_5: # %if.end69
; CHECK-NEXT: movl %r13d, 0
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: xorl %esi, %esi
@@ -91,7 +91,7 @@ define i32 @decode_sb(ptr %t, i32 %bl, i32 %_msprop1966, i32 %sub.i, i64 %idxpro
; CHECK-NEXT: movslq %r12d, %rax
; CHECK-NEXT: movzbl (%r15), %ecx
; CHECK-NEXT: movb %cl, 544(%rax)
-; CHECK-NEXT: .LBB0_7: # %land.lhs.true56
+; CHECK-NEXT: .LBB0_6: # %land.lhs.true56
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: addq $8, %rsp
; CHECK-NEXT: popq %rbx
@@ -102,7 +102,9 @@ define i32 @decode_sb(ptr %t, i32 %bl, i32 %_msprop1966, i32 %sub.i, i64 %idxpro
; CHECK-NEXT: popq %rbp
; CHECK-NEXT: .cfi_def_cfa %rsp, 8
; CHECK-NEXT: retq
-; CHECK-NEXT: .LBB0_4: # %bb
+; CHECK-NEXT: .LBB0_7: # %bb
+; CHECK-NEXT: .cfi_def_cfa %rbp, 16
+; CHECK-NEXT: ud2
entry:
%i = load i32, ptr null, align 8
br i1 %cmp54, label %if.end69, label %if.else
diff --git a/llvm/test/CodeGen/X86/jump_sign.ll b/llvm/test/CodeGen/X86/jump_sign.ll
index 9eaa65442a727f..22c331c17620fa 100644
--- a/llvm/test/CodeGen/X86/jump_sign.ll
+++ b/llvm/test/CodeGen/X86/jump_sign.ll
@@ -217,36 +217,33 @@ define void @func_o() nounwind uwtable {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al
-; CHECK-NEXT: je .LBB12_1
-; CHECK-NEXT: # %bb.2: # %if.end.i
+; CHECK-NEXT: je .LBB12_5
+; CHECK-NEXT: # %bb.1: # %if.end.i
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al
-; CHECK-NEXT: jne .LBB12_5
-; CHECK-NEXT: # %bb.3: # %sw.bb
+; CHECK-NEXT: jne .LBB12_4
+; CHECK-NEXT: # %bb.2: # %sw.bb
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al
-; CHECK-NEXT: jne .LBB12_8
-; CHECK-NEXT: # %bb.4: # %if.end29
+; CHECK-NEXT: jne .LBB12_6
+; CHECK-NEXT: # %bb.3: # %if.end29
; CHECK-NEXT: movzwl (%eax), %eax
; CHECK-NEXT: imull $-13107, %eax, %eax # imm = 0xCCCD
; CHECK-NEXT: rorw %ax
; CHECK-NEXT: movzwl %ax, %eax
; CHECK-NEXT: cmpl $6554, %eax # imm = 0x199A
-; CHECK-NEXT: jae .LBB12_5
-; CHECK-NEXT: .LBB12_8: # %if.then44
+; CHECK-NEXT: jae .LBB12_4
+; CHECK-NEXT: .LBB12_6: # %if.then44
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al
-; CHECK-NEXT: je .LBB12_9
-; CHECK-NEXT: # %bb.10: # %if.else.i104
+; CHECK-NEXT: je .LBB12_5
+; CHECK-NEXT: # %bb.7: # %if.else.i104
; CHECK-NEXT: retl
-; CHECK-NEXT: .LBB12_5: # %sw.default
+; CHECK-NEXT: .LBB12_4: # %sw.default
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al
-; CHECK-NEXT: jne .LBB12_7
-; CHECK-NEXT: # %bb.6: # %if.then.i96
-; CHECK-NEXT: .LBB12_1: # %if.then.i
-; CHECK-NEXT: .LBB12_9: # %if.then.i103
-; CHECK-NEXT: .LBB12_7: # %if.else.i97
+; CHECK-NEXT: .LBB12_5: # %if.then.i
+; CHECK-NEXT: ud2
entry:
%0 = load i16, ptr undef, align 2
br i1 undef, label %if.then.i, label %if.end.i
diff --git a/llvm/test/CodeGen/X86/machine-cse.ll b/llvm/test/CodeGen/X86/machine-cse.ll
index 431031136e4a42..e6126318414d0b 100644
--- a/llvm/test/CodeGen/X86/machine-cse.ll
+++ b/llvm/test/CodeGen/X86/machine-cse.ll
@@ -20,8 +20,10 @@ define fastcc ptr @t(i32 %base) nounwind {
; CHECK-NEXT: jne .LBB0_2
; CHECK-NEXT: # %bb.1: # %bb1
; CHECK-NEXT: callq bar at PLT
+; CHECK-NEXT: ud2
; CHECK-NEXT: .LBB0_2: # %bb2
; CHECK-NEXT: callq foo at PLT
+; CHECK-NEXT: ud2
entry:
%0 = zext i32 %base to i64
%1 = getelementptr inbounds %struct.s2, ptr null, i64 %0
diff --git a/llvm/test/CodeGen/X86/nomerge.ll b/llvm/test/CodeGen/X86/nomerge.ll
index f0aedcb90c4ada..0b697cb710369a 100644
--- a/llvm/test/CodeGen/X86/nomerge.ll
+++ b/llvm/test/CodeGen/X86/nomerge.ll
@@ -99,10 +99,13 @@ define void @nomerge_debugtrap(i32 %i) {
; CHECK: # %bb.1: # %entry
; CHECK: # %bb.2: # %if.then
; CHECK-NEXT: int3
+; CHECK-NEXT: ud2
; CHECK-NEXT: LBB{{.*}}: # %if.then2
; CHECK-NEXT: int3
+; CHECK-NEXT: ud2
; CHECK-NEXT: .LBB{{.*}}: # %if.end3
; CHECK-NEXT: int3
+; CHECK-NEXT: ud2
entry:
switch i32 %i, label %if.end3 [
i32 5, label %if.then
@@ -128,10 +131,13 @@ define void @nomerge_named_debugtrap(i32 %i) {
; CHECK: # %bb.1: # %entry
; CHECK: # %bb.2: # %if.then
; CHECK-NEXT: callq trap_func at PLT
+; CHECK-NEXT: ud2
; CHECK-NEXT: LBB{{.*}}: # %if.then2
; CHECK-NEXT: callq trap_func at PLT
+; CHECK-NEXT: ud2
; CHECK-NEXT: .LBB{{.*}}: # %if.end3
; CHECK-NEXT: callq trap_func at PLT
+; CHECK-NEXT: ud2
entry:
switch i32 %i, label %if.end3 [
i32 5, label %if.then
diff --git a/llvm/test/CodeGen/X86/noreturn-call-win64.ll b/llvm/test/CodeGen/X86/noreturn-call-win64.ll
index 57aa022e89e293..b98aced49cbd21 100644
--- a/llvm/test/CodeGen/X86/noreturn-call-win64.ll
+++ b/llvm/test/CodeGen/X86/noreturn-call-win64.ll
@@ -109,5 +109,5 @@ declare dso_local void @"??1MakeCleanup@@QEAA at XZ"(ptr)
; CHECK: callq _CxxThrowException
; CHECK-NOT: {{(addq|subq) .*, %rsp}}
; CHECK: # %unreachable
-; CHECK: int3
+; CHECK: ud2
; CHECK: .seh_handlerdata
diff --git a/llvm/test/CodeGen/X86/noreturn-call.ll b/llvm/test/CodeGen/X86/noreturn-call.ll
index 2e4c2a26c57937..204841b3ea1901 100644
--- a/llvm/test/CodeGen/X86/noreturn-call.ll
+++ b/llvm/test/CodeGen/X86/noreturn-call.ll
@@ -39,7 +39,8 @@ if.then:
; Even though _crash2 is not marked noreturn, it is in practice because
; of the "unreachable" right after it. This happens e.g. when falling off
; a non-void function after a call.
-; CHECK-NOT: add
+; CHECK-NEXT: add
+; CHECK-NEXT: ud2
; CHECK-NOT: pop
}
diff --git a/llvm/test/CodeGen/X86/overflowing-iv-codegen.ll b/llvm/test/CodeGen/X86/overflowing-iv-codegen.ll
index 3e4539d333474f..6419c7b5356f5f 100644
--- a/llvm/test/CodeGen/X86/overflowing-iv-codegen.ll
+++ b/llvm/test/CodeGen/X86/overflowing-iv-codegen.ll
@@ -17,6 +17,7 @@ define i32 @test_01(ptr %p, i64 %len, i32 %x) {
; CHECK-NEXT: leaq 4(%rdi), %rdi
; CHECK-NEXT: jne .LBB0_1
; CHECK-NEXT: # %bb.3: # %failure
+; CHECK-NEXT: ud2
; CHECK-NEXT: .LBB0_4: # %exit
; CHECK-NEXT: movl $-1, %eax
; CHECK-NEXT: retq
@@ -58,7 +59,8 @@ define i32 @test_02(ptr %p, i64 %len, i32 %x) {
; CHECK-NEXT: cmpl %edx, (%rdi)
; CHECK-NEXT: leaq 4(%rdi), %rdi
; CHECK-NEXT: jne .LBB1_1
-; CHECK-NEXT: # %bb.3: # %failure
+; CHECK-NEXT: # %bb.3: # %
+; CHECK-NEXT: ud2
; CHECK-NEXT: .LBB1_4: # %exit
; CHECK-NEXT: movl $-1, %eax
; CHECK-NEXT: retq
@@ -101,6 +103,7 @@ define i32 @test_02_nopoison(ptr %p, i64 %len, i32 %x) {
; CHECK-NEXT: leaq 4(%rdi), %rdi
; CHECK-NEXT: jne .LBB2_1
; CHECK-NEXT: # %bb.3: # %failure
+; CHECK-NEXT: ud2
; CHECK-NEXT: .LBB2_4: # %exit
; CHECK-NEXT: movl $-1, %eax
; CHECK-NEXT: retq
@@ -145,6 +148,7 @@ define i32 @test_03(ptr %p, i64 %len, i32 %x) {
; CHECK-NEXT: leaq 4(%rdi), %rdi
; CHECK-NEXT: jne .LBB3_1
; CHECK-NEXT: # %bb.3: # %failure
+; CHECK-NEXT: ud2
; CHECK-NEXT: .LBB3_4: # %exit
; CHECK-NEXT: movl $-1, %eax
; CHECK-NEXT: retq
@@ -187,6 +191,7 @@ define i32 @test_03_nopoison(ptr %p, i64 %len, i32 %x) {
; CHECK-NEXT: leaq 4(%rdi), %rdi
; CHECK-NEXT: jne .LBB4_1
; CHECK-NEXT: # %bb.3: # %failure
+; CHECK-NEXT: ud2
; CHECK-NEXT: .LBB4_4: # %exit
; CHECK-NEXT: movl $-1, %eax
; CHECK-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/patchable-prologue.ll b/llvm/test/CodeGen/X86/patchable-prologue.ll
index aec76a359d267e..8272daf4c29060 100644
--- a/llvm/test/CodeGen/X86/patchable-prologue.ll
+++ b/llvm/test/CodeGen/X86/patchable-prologue.ll
@@ -1,10 +1,10 @@
; RUN: llc -verify-machineinstrs -filetype=obj -o - -mtriple=x86_64-apple-macosx < %s | llvm-objdump --no-print-imm-hex --triple=x86_64-apple-macosx -d - | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=x86_64-apple-macosx < %s | FileCheck %s --check-prefix=CHECK-ALIGN
-; RUN: llc -verify-machineinstrs -show-mc-encoding -mtriple=i386 < %s | FileCheck %s --check-prefixes=X86,X86CFI,XCHG
-; RUN: llc -verify-machineinstrs -show-mc-encoding -mtriple=i386-windows-msvc < %s | FileCheck %s --check-prefixes=X86,MOV
-; RUN: llc -verify-machineinstrs -show-mc-encoding -mtriple=i386-windows-msvc -mcpu=pentium3 < %s | FileCheck %s --check-prefixes=X86,MOV
-; RUN: llc -verify-machineinstrs -show-mc-encoding -mtriple=i386-windows-msvc -mcpu=pentium4 < %s | FileCheck %s --check-prefixes=X86,XCHG
-; RUN: llc -verify-machineinstrs -show-mc-encoding -mtriple=x86_64-windows-msvc < %s | FileCheck %s --check-prefix=X64
+; RUN: llc -trap-unreachable=false -verify-machineinstrs -show-mc-encoding -mtriple=i386 < %s | FileCheck %s --check-prefixes=X86,X86CFI,XCHG
+; RUN: llc -trap-unreachable=false -verify-machineinstrs -show-mc-encoding -mtriple=i386-windows-msvc < %s | FileCheck %s --check-prefixes=X86,MOV
+; RUN: llc -trap-unreachable=false -verify-machineinstrs -show-mc-encoding -mtriple=i386-windows-msvc -mcpu=pentium3 < %s | FileCheck %s --check-prefixes=X86,MOV
+; RUN: llc -trap-unreachable=false -verify-machineinstrs -show-mc-encoding -mtriple=i386-windows-msvc -mcpu=pentium4 < %s | FileCheck %s --check-prefixes=X86,XCHG
+; RUN: llc -trap-unreachable=false -verify-machineinstrs -show-mc-encoding -mtriple=x86_64-windows-msvc < %s | FileCheck %s --check-prefix=X64
declare void @callee(ptr)
@@ -135,7 +135,7 @@ bb21:
}
; This testcase produces an empty function (not even a ret on some targets).
-; This scenario can happen with undefined behavior.
+; This scenario can happen with undefined behavior when trap-unreachable is set to false.
; Ensure that the "patchable-function" pass supports this case.
; CHECK-LABEL: _emptyfunc
; CHECK-NEXT: 0f 0b ud2
diff --git a/llvm/test/CodeGen/X86/pr24374.ll b/llvm/test/CodeGen/X86/pr24374.ll
index 06281b5f7f53e8..a4f7d1b7cd126c 100644
--- a/llvm/test/CodeGen/X86/pr24374.ll
+++ b/llvm/test/CodeGen/X86/pr24374.ll
@@ -31,6 +31,6 @@ define void @g() {
unreachable
}
; CHECK-LABEL: g:
-; CHECK: nop
+; CHECK: ud2
attributes #0 = { nounwind }
diff --git a/llvm/test/CodeGen/X86/pr32484.ll b/llvm/test/CodeGen/X86/pr32484.ll
index 790211f95d058d..875de256bb91a1 100644
--- a/llvm/test/CodeGen/X86/pr32484.ll
+++ b/llvm/test/CodeGen/X86/pr32484.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -O0 -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
+; Set trap-unreachable to false as otherwise otherwise part of the test will be optimized away.
+; RUN: llc -O0 -mtriple=x86_64-unknown-linux-gnu -trap-unreachable=false < %s | FileCheck %s
define void @foo() {
; CHECK-LABEL: foo:
diff --git a/llvm/test/CodeGen/X86/pr3366.ll b/llvm/test/CodeGen/X86/pr3366.ll
index 22129839eb2a42..49d141a41b3cc0 100644
--- a/llvm/test/CodeGen/X86/pr3366.ll
+++ b/llvm/test/CodeGen/X86/pr3366.ll
@@ -9,7 +9,6 @@ define void @_ada_c34002a() nounwind {
; CHECK-NEXT: movzbl %al, %eax
; CHECK-NEXT: idivb 0
; CHECK-NEXT: cmpb $3, %al
-; CHECK-NEXT: # %bb.1: # %bb457
entry:
%0 = load i8, ptr null, align 1
%1 = sdiv i8 90, %0
@@ -25,5 +24,5 @@ bb451:
br label %bb457
bb457:
- unreachable
+ ret void
}
diff --git a/llvm/test/CodeGen/X86/pr49451.ll b/llvm/test/CodeGen/X86/pr49451.ll
index cc4607c5c55f3c..c8003d8d042243 100644
--- a/llvm/test/CodeGen/X86/pr49451.ll
+++ b/llvm/test/CodeGen/X86/pr49451.ll
@@ -19,8 +19,8 @@ define void @func_6(i8 %uc_8, i64 %uli_10) nounwind {
; X86-NEXT: .LBB0_1: # %for.body612
; X86-NEXT: # =>This Inner Loop Header: Depth=1
; X86-NEXT: testb %dl, %dl
-; X86-NEXT: je .LBB0_2
-; X86-NEXT: # %bb.3: # %if.end1401
+; X86-NEXT: je .LBB0_3
+; X86-NEXT: # %bb.2: # %if.end1401
; X86-NEXT: # in Loop: Header=BB0_1 Depth=1
; X86-NEXT: addl %eax, %esi
; X86-NEXT: movw %si, s_2
@@ -29,8 +29,8 @@ define void @func_6(i8 %uc_8, i64 %uli_10) nounwind {
; X86-NEXT: incl %ebx
; X86-NEXT: cmpw $73, %cx
; X86-NEXT: jl .LBB0_1
-; X86-NEXT: # %bb.4: # %for.body1703
-; X86-NEXT: .LBB0_2: # %if.then671
+; X86-NEXT: .LBB0_3: # %if.then671
+; X86-NEXT: ud2
;
; X64-LABEL: func_6:
; X64: # %bb.0: # %entry
@@ -41,8 +41,8 @@ define void @func_6(i8 %uc_8, i64 %uli_10) nounwind {
; X64-NEXT: .LBB0_1: # %for.body612
; X64-NEXT: # =>This Inner Loop Header: Depth=1
; X64-NEXT: testb %cl, %cl
-; X64-NEXT: je .LBB0_2
-; X64-NEXT: # %bb.3: # %if.end1401
+; X64-NEXT: je .LBB0_3
+; X64-NEXT: # %bb.2: # %if.end1401
; X64-NEXT: # in Loop: Header=BB0_1 Depth=1
; X64-NEXT: addl %esi, %edx
; X64-NEXT: movw %dx, s_2(%rip)
@@ -52,8 +52,8 @@ define void @func_6(i8 %uc_8, i64 %uli_10) nounwind {
; X64-NEXT: leal -23091(%rax), %edi
; X64-NEXT: cmpw $73, %di
; X64-NEXT: jl .LBB0_1
-; X64-NEXT: # %bb.4: # %for.body1703
-; X64-NEXT: .LBB0_2: # %if.then671
+; X64-NEXT: .LBB0_3: # %if.then671
+; X64-NEXT: ud2
entry:
%conv649 = zext i8 %uc_8 to i64
%xor650 = xor i64 %conv649, 296357731680175678
diff --git a/llvm/test/CodeGen/X86/pr56103.ll b/llvm/test/CodeGen/X86/pr56103.ll
index 3a0941e82ed785..0f6ed2f9b5edbc 100644
--- a/llvm/test/CodeGen/X86/pr56103.ll
+++ b/llvm/test/CodeGen/X86/pr56103.ll
@@ -28,13 +28,14 @@ define dso_local i32 @main() nounwind {
; CHECK-NEXT: notl %ecx
; CHECK-NEXT: andl %eax, %ecx
; CHECK-NEXT: testq %rcx, %rcx
-; CHECK-NEXT: jle .LBB0_2
-; CHECK-NEXT: # %bb.1: # %if.end
+; CHECK-NEXT: jle .LBB0_1
+; CHECK-NEXT: # %bb.2: # %if.end
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: retq
-; CHECK-NEXT: .LBB0_2: # %if.then
+; CHECK-NEXT: .LBB0_1: # %if.then
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: callq abort at PLT
+; CHECK-NEXT: ud2
entry:
store i16 1, ptr @e, align 2
store i64 1, ptr @b, align 8
diff --git a/llvm/test/CodeGen/X86/shift-combine.ll b/llvm/test/CodeGen/X86/shift-combine.ll
index c9edd3f3e9048c..2ed53106cb2a0e 100644
--- a/llvm/test/CodeGen/X86/shift-combine.ll
+++ b/llvm/test/CodeGen/X86/shift-combine.ll
@@ -387,14 +387,18 @@ define dso_local i32 @ashr_add_shl_i32_i8_extra_use3(i32 %r, ptr %p1, ptr %p2) n
%"class.QPainterPath" = type { double, double, i32 }
-define dso_local void @PR42880(i32 %t0) {
+define dso_local i32 @PR42880(i32 %t0) {
; X86-LABEL: PR42880:
; X86: # %bb.0:
; X86-NEXT: xorl %eax, %eax
; X86-NEXT: testb %al, %al
; X86-NEXT: je .LBB16_1
; X86-NEXT: # %bb.2: # %if
+; X86-NEXT: xorl %eax, %eax
+; X86-NEXT: retl
; X86-NEXT: .LBB16_1: # %then
+; X86-NEXT: movl $4, %eax
+; X86-NEXT: retl
;
; X64-LABEL: PR42880:
; X64: # %bb.0:
@@ -402,7 +406,11 @@ define dso_local void @PR42880(i32 %t0) {
; X64-NEXT: testb %al, %al
; X64-NEXT: je .LBB16_1
; X64-NEXT: # %bb.2: # %if
+; X64-NEXT: xorl %eax, %eax
+; X64-NEXT: retq
; X64-NEXT: .LBB16_1: # %then
+; X64-NEXT: movl $4, %eax
+; X64-NEXT: retq
%sub = add nsw i32 %t0, -1
%add.ptr.i94 = getelementptr inbounds %"class.QPainterPath", ptr null, i32 %sub
%x = ptrtoint ptr %add.ptr.i94 to i32
@@ -412,10 +420,10 @@ define dso_local void @PR42880(i32 %t0) {
then:
%t1 = xor i32 %div, -1
- unreachable
+ ret i32 4
if:
- unreachable
+ ret i32 0
}
; The mul here is the equivalent of (neg (shl X, 32)).
diff --git a/llvm/test/CodeGen/X86/stack-coloring-wineh.ll b/llvm/test/CodeGen/X86/stack-coloring-wineh.ll
index 79057e0ea78d39..8d1635df99e9ea 100644
--- a/llvm/test/CodeGen/X86/stack-coloring-wineh.ll
+++ b/llvm/test/CodeGen/X86/stack-coloring-wineh.ll
@@ -24,6 +24,7 @@ define void @pr66984(ptr %arg) personality ptr @__CxxFrameHandler3 {
; I686-NEXT: movl $1, -16(%ebp)
; I686-NEXT: calll _throw
; I686-NEXT: # %bb.1: # %bb14
+; I686-NEXT: ud2
; I686-NEXT: LBB0_3: # Block address taken
; I686-NEXT: # %bb17
; I686-NEXT: addl $12, %ebp
@@ -86,10 +87,10 @@ define void @pr66984(ptr %arg) personality ptr @__CxxFrameHandler3 {
; X86_64-NEXT: callq throw
; X86_64-NEXT: .Ltmp1:
; X86_64-NEXT: # %bb.1: # %bb14
+; X86_64-NEXT: ud2
; X86_64-NEXT: .LBB0_3: # Block address taken
; X86_64-NEXT: # %exit
; X86_64-NEXT: $ehgcr_0_3:
-; X86_64-NEXT: nop
; X86_64-NEXT: addq $64, %rsp
; X86_64-NEXT: popq %rbp
; X86_64-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/stack-protector-no-return.ll b/llvm/test/CodeGen/X86/stack-protector-no-return.ll
index cfebf0080a6d6e..bc021d3757c346 100644
--- a/llvm/test/CodeGen/X86/stack-protector-no-return.ll
+++ b/llvm/test/CodeGen/X86/stack-protector-no-return.ll
@@ -28,6 +28,7 @@ define void @_Z7catchesv() #0 personality ptr null {
; CHECK-NEXT: callq *%rax
; CHECK-NEXT: .Ltmp3:
; CHECK-NEXT: # %bb.3: # %invoke.cont2
+; CHECK-NEXT: ud2
; CHECK-NEXT: .LBB0_4: # %lpad1
; CHECK-NEXT: .Ltmp4:
; CHECK-NEXT: movq %fs:40, %rax
@@ -61,6 +62,7 @@ define void @_Z7catchesv() #0 personality ptr null {
; DISNOTET-NEXT: callq *%rax
; DISNOTET-NEXT: .Ltmp3:
; DISNOTET-NEXT: # %bb.2: # %invoke.cont2
+; DISNOTET-NEXT: ud2
; DISNOTET-NEXT: .LBB0_3: # %lpad1
; DISNOTET-NEXT: .Ltmp4:
; DISNOTET-NEXT: movq %fs:40, %rax
diff --git a/llvm/test/CodeGen/X86/statepoint-vreg-invoke.ll b/llvm/test/CodeGen/X86/statepoint-vreg-invoke.ll
index ef542e5b1427ae..5cb1948f258dc8 100644
--- a/llvm/test/CodeGen/X86/statepoint-vreg-invoke.ll
+++ b/llvm/test/CodeGen/X86/statepoint-vreg-invoke.ll
@@ -196,6 +196,7 @@ define void @test_duplicate_ir_values() gc "statepoint-example" personality ptr
; CHECK-NEXT: $edi = MOV32ri 10
; CHECK-NEXT: dead renamable $rbx = STATEPOINT 2882400000, 0, 1, target-flags(x86-plt) @__llvm_deoptimize, killed $edi, 2, 0, 2, 2, 2, 2, killed renamable $rbx, renamable $rbx, 2, 1, renamable $rbx(tied-def 0), 2, 0, 2, 1, 0, 0, csr_64, implicit-def $rsp, implicit-def $ssp
; CHECK-NEXT: ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
+ ; CHECK-NEXT: TRAP
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.exceptional_return (landing-pad):
; CHECK-NEXT: liveins: $rax, $rdx
diff --git a/llvm/test/CodeGen/X86/switch-bt.ll b/llvm/test/CodeGen/X86/switch-bt.ll
index 2bf7c46e67e189..34fe2432e4564f 100644
--- a/llvm/test/CodeGen/X86/switch-bt.ll
+++ b/llvm/test/CodeGen/X86/switch-bt.ll
@@ -235,12 +235,15 @@ define void @test5(i32 %x) {
; CHECK-NEXT: # %bb.4: # %bb1
; CHECK-NEXT: movl $1, %edi
; CHECK-NEXT: callq g at PLT
+; CHECK-NEXT: ud2
; CHECK-NEXT: .LBB4_3: # %bb0
; CHECK-NEXT: xorl %edi, %edi
; CHECK-NEXT: callq g at PLT
+; CHECK-NEXT: ud2
; CHECK-NEXT: .LBB4_2: # %bb2
; CHECK-NEXT: movl $2, %edi
; CHECK-NEXT: callq g at PLT
+; CHECK-NEXT: ud2
entry:
switch i32 %x, label %return [
diff --git a/llvm/test/CodeGen/X86/switch.ll b/llvm/test/CodeGen/X86/switch.ll
index b00044a1e4f795..e5595f2f3cd972 100644
--- a/llvm/test/CodeGen/X86/switch.ll
+++ b/llvm/test/CodeGen/X86/switch.ll
@@ -2507,20 +2507,18 @@ define i32 @pr27135(i32 %i) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al
-; CHECK-NEXT: jne .LBB24_5
+; CHECK-NEXT: jne .LBB24_3
; CHECK-NEXT: # %bb.1: # %sw
; CHECK-NEXT: movl $1, %eax
; CHECK-NEXT: addl $-96, %edi
; CHECK-NEXT: cmpl $5, %edi
; CHECK-NEXT: jbe .LBB24_2
-; CHECK-NEXT: .LBB24_5: # %end
+; CHECK-NEXT: .LBB24_3: # %end
; CHECK-NEXT: retq
; CHECK-NEXT: .LBB24_2: # %sw
; CHECK-NEXT: movl $19, %eax
; CHECK-NEXT: btl %edi, %eax
-; CHECK-NEXT: jae .LBB24_3
-; CHECK-NEXT: # %bb.4: # %sw.bb2
-; CHECK-NEXT: .LBB24_3: # %sw.bb
+; CHECK-NEXT: ud2
;
; NOOPT-LABEL: pr27135:
; NOOPT: # %bb.0: # %entry
@@ -2558,7 +2556,9 @@ define i32 @pr27135(i32 %i) {
; NOOPT-NEXT: jne .LBB24_4
; NOOPT-NEXT: jmp .LBB24_2
; NOOPT-NEXT: .LBB24_2: # %sw.bb
+; NOOPT-NEXT: ud2
; NOOPT-NEXT: .LBB24_3: # %sw.bb2
+; NOOPT-NEXT: ud2
; NOOPT-NEXT: .LBB24_4: # %end
; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload
; NOOPT-NEXT: retq
@@ -2619,6 +2619,7 @@ define void @range_with_unreachable_fallthrough(i32 %i) {
; NOOPT-NEXT: jmp .LBB25_4
; NOOPT-NEXT: # %bb.3: # %default
; NOOPT-NEXT: .cfi_def_cfa_offset 8
+; NOOPT-NEXT: ud2
; NOOPT-NEXT: .LBB25_4: # %return
; NOOPT-NEXT: .cfi_def_cfa_offset 16
; NOOPT-NEXT: popq %rax
diff --git a/llvm/test/CodeGen/X86/tail-dup-merge-loop-headers.ll b/llvm/test/CodeGen/X86/tail-dup-merge-loop-headers.ll
index 8d84e887d3f279..b1a1750b55f84b 100644
--- a/llvm/test/CodeGen/X86/tail-dup-merge-loop-headers.ll
+++ b/llvm/test/CodeGen/X86/tail-dup-merge-loop-headers.ll
@@ -113,7 +113,7 @@ define i32 @loop_shared_header(ptr %exe, i32 %exesz, i32 %headsize, i32 %min, i3
; CHECK-NEXT: movq %r15, %rdx
; CHECK-NEXT: callq memcpy at PLT
; CHECK-NEXT: cmpl $4, %ebp
-; CHECK-NEXT: jb .LBB1_19
+; CHECK-NEXT: jb .LBB1_7
; CHECK-NEXT: # %bb.3: # %shared_preheader
; CHECK-NEXT: movb $32, %cl
; CHECK-NEXT: xorl %eax, %eax
@@ -132,7 +132,7 @@ define i32 @loop_shared_header(ptr %exe, i32 %exesz, i32 %headsize, i32 %min, i3
; CHECK-NEXT: # Parent Loop BB1_4 Depth=1
; CHECK-NEXT: # => This Inner Loop Header: Depth=2
; CHECK-NEXT: testq %r14, %r14
-; CHECK-NEXT: jne .LBB1_18
+; CHECK-NEXT: jne .LBB1_7
; CHECK-NEXT: # %bb.9: # %inner_loop_body
; CHECK-NEXT: # in Loop: Header=BB1_8 Depth=2
; CHECK-NEXT: testb %al, %al
@@ -167,6 +167,7 @@ define i32 @loop_shared_header(ptr %exe, i32 %exesz, i32 %headsize, i32 %min, i3
; CHECK-NEXT: decb %cl
; CHECK-NEXT: jne .LBB1_12
; CHECK-NEXT: .LBB1_7: # %if.end41.us1436.i
+; CHECK-NEXT: ud2
; CHECK-NEXT: .LBB1_11: # %if.then99.i
; CHECK-NEXT: movq .str.6 at GOTPCREL(%rip), %rdi
; CHECK-NEXT: xorl %ebx, %ebx
@@ -180,8 +181,6 @@ define i32 @loop_shared_header(ptr %exe, i32 %exesz, i32 %headsize, i32 %min, i3
; CHECK-NEXT: popq %r15
; CHECK-NEXT: popq %rbp
; CHECK-NEXT: retq
-; CHECK-NEXT: .LBB1_18: # %wunpsect.exit.thread.loopexit389
-; CHECK-NEXT: .LBB1_19: # %wunpsect.exit.thread.loopexit391
entry:
%0 = load i32, ptr undef, align 4
%mul = shl nsw i32 %0, 2
diff --git a/llvm/test/CodeGen/X86/tail-merge-unreachable.ll b/llvm/test/CodeGen/X86/tail-merge-unreachable.ll
index ce5613f5230955..94e442cfb29c67 100644
--- a/llvm/test/CodeGen/X86/tail-merge-unreachable.ll
+++ b/llvm/test/CodeGen/X86/tail-merge-unreachable.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=x86_64-linux-gnu %s -o - -verify-machineinstrs | FileCheck %s
+; RUN: llc -trap-unreachable=false -mtriple=x86_64-linux-gnu %s -o - -verify-machineinstrs | FileCheck %s
define i32 @tail_merge_unreachable(i32 %i) {
entry:
diff --git a/llvm/test/CodeGen/X86/tail-opts.ll b/llvm/test/CodeGen/X86/tail-opts.ll
index d9ab2f7d1f5fb6..8bb818edd5d452 100644
--- a/llvm/test/CodeGen/X86/tail-opts.ll
+++ b/llvm/test/CodeGen/X86/tail-opts.ll
@@ -277,6 +277,7 @@ define fastcc void @c_expand_expr_stmt(ptr %expr) nounwind {
; CHECK-NEXT: .LBB3_8: # %bb1
; CHECK-NEXT: cmpb $23, %bl
; CHECK-NEXT: .LBB3_9: # %bb3
+; CHECK-NEXT: ud2
; CHECK-NEXT: .LBB3_15:
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: jmp .LBB3_16
@@ -300,6 +301,7 @@ define fastcc void @c_expand_expr_stmt(ptr %expr) nounwind {
; CHECK-NEXT: cmpl $23, %ecx
; CHECK-NEXT: jne .LBB3_9
; CHECK-NEXT: .LBB3_16: # %lvalue_p.exit4
+; CHECK-NEXT: ud2
; CHECK-NEXT: testb %bl, %bl
; CHECK-NEXT: sete %cl
; CHECK-NEXT: orb %al, %cl
@@ -527,6 +529,7 @@ define dso_local void @two() nounwind optsize {
; CHECK-NEXT: .LBB7_1: # %bb7
; CHECK-NEXT: movl $0, XYZ(%rip)
; CHECK-NEXT: movl $1, XYZ(%rip)
+; CHECK-NEXT: ud2
entry:
%0 = icmp eq i32 undef, 0
br i1 %0, label %bbx, label %bby
@@ -568,6 +571,7 @@ define dso_local void @two_pgso() nounwind !prof !14 {
; CHECK-NEXT: .LBB8_1: # %bb7
; CHECK-NEXT: movl $0, XYZ(%rip)
; CHECK-NEXT: movl $1, XYZ(%rip)
+; CHECK-NEXT: ud2
entry:
%0 = icmp eq i32 undef, 0
br i1 %0, label %bbx, label %bby
@@ -611,6 +615,7 @@ define dso_local void @two_minsize() nounwind minsize {
; CHECK-NEXT: .LBB9_1: # %bb7
; CHECK-NEXT: movl $0, XYZ(%rip)
; CHECK-NEXT: movl $1, XYZ(%rip)
+; CHECK-NEXT: ud2
entry:
%0 = icmp eq i32 undef, 0
br i1 %0, label %bbx, label %bby
@@ -752,6 +757,7 @@ define dso_local void @merge_aborts() {
; CHECK-NEXT: .LBB12_5: # %abort1
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq abort
+; CHECK-NEXT: ud2
entry:
%c1 = call i1 @qux()
br i1 %c1, label %cont1, label %abort1
@@ -812,8 +818,10 @@ define dso_local void @merge_alternating_aborts() {
; CHECK-NEXT: .LBB13_5: # %abort1
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq abort
+; CHECK-NEXT: ud2
; CHECK-NEXT: .LBB13_6: # %abort2
; CHECK-NEXT: callq alt_abort
+; CHECK-NEXT: ud2
entry:
%c1 = call i1 @qux()
br i1 %c1, label %cont1, label %abort1
diff --git a/llvm/test/CodeGen/X86/trap.ll b/llvm/test/CodeGen/X86/trap.ll
index 3d9a858beda851..5a41090dcf470f 100644
--- a/llvm/test/CodeGen/X86/trap.ll
+++ b/llvm/test/CodeGen/X86/trap.ll
@@ -18,7 +18,7 @@ entry:
; LINUX: int3
; PS4: int $65
; WIN64: int3
-; WIN64-NOT: ud2
+; CHECK-NEXT: ud2
define i32 @test1() noreturn nounwind {
entry:
tail call void @llvm.debugtrap( )
diff --git a/llvm/test/CodeGen/X86/unreachable-trap.ll b/llvm/test/CodeGen/X86/unreachable-trap.ll
index d2704bf7b46205..755adc9d1987ec 100644
--- a/llvm/test/CodeGen/X86/unreachable-trap.ll
+++ b/llvm/test/CodeGen/X86/unreachable-trap.ll
@@ -1,10 +1,13 @@
-; RUN: llc -o - %s -mtriple=x86_64-linux-gnu | FileCheck %s --check-prefixes=CHECK
-; RUN: llc -o - %s -mtriple=x86_64-windows-msvc | FileCheck %s --check-prefixes=CHECK
-; RUN: llc -o - %s -mtriple=x86_64-scei-ps4 | FileCheck %s --check-prefixes=CHECK,TRAP_AFTER_NORETURN
+; RUN: llc -o - %s -mtriple=x86_64-linux-gnu | FileCheck %s --check-prefixes=CHECK,NO_TRAP_AFTER_NORETURN
+; RUN: llc -o - %s -mtriple=x86_64-windows-msvc | FileCheck %s --check-prefixes=CHECK,NO_TRAP_AFTER_NORETURN
; RUN: llc -o - %s -mtriple=x86_64-apple-darwin | FileCheck %s --check-prefixes=CHECK,NO_TRAP_AFTER_NORETURN
-; RUN: llc --trap-unreachable -o - %s -mtriple=x86_64-linux-gnu | FileCheck %s --check-prefixes=CHECK,TRAP_AFTER_NORETURN
-; RUN: llc --trap-unreachable -global-isel -o - %s -mtriple=x86_64-linux-gnu | FileCheck %s --check-prefixes=CHECK,TRAP_AFTER_NORETURN
-; RUN: llc --trap-unreachable -fast-isel -o - %s -mtriple=x86_64-linux-gnu | FileCheck %s --check-prefixes=CHECK,TRAP_AFTER_NORETURN
+; RUN: llc -o - %s -mtriple=x86_64-scei-ps4 | FileCheck %s --check-prefixes=CHECK,TRAP_AFTER_NORETURN
+; RUN: llc --trap-unreachable --no-trap-after-noreturn -o - %s -mtriple=x86_64-linux-gnu | FileCheck %s --check-prefixes=CHECK,NO_TRAP_AFTER_NORETURN
+; RUN: llc --trap-unreachable --no-trap-after-noreturn -global-isel -o - %s -mtriple=x86_64-linux-gnu | FileCheck %s --check-prefixes=CHECK,NO_TRAP_AFTER_NORETURN
+; RUN: llc --trap-unreachable --no-trap-after-noreturn -fast-isel -o - %s -mtriple=x86_64-linux-gnu | FileCheck %s --check-prefixes=CHECK,NO_TRAP_AFTER_NORETURN
+; RUN: llc --trap-unreachable --no-trap-after-noreturn=false -o - %s -mtriple=x86_64-linux-gnu | FileCheck %s --check-prefixes=CHECK,TRAP_AFTER_NORETURN
+; RUN: llc --trap-unreachable --no-trap-after-noreturn=false -global-isel -o - %s -mtriple=x86_64-linux-gnu | FileCheck %s --check-prefixes=CHECK,TRAP_AFTER_NORETURN
+; RUN: llc --trap-unreachable --no-trap-after-noreturn=false -fast-isel -o - %s -mtriple=x86_64-linux-gnu | FileCheck %s --check-prefixes=CHECK,TRAP_AFTER_NORETURN
; CHECK-LABEL: call_exit:
; CHECK: callq {{_?}}exit
diff --git a/llvm/test/CodeGen/X86/unreachable-ubsantrap.ll b/llvm/test/CodeGen/X86/unreachable-ubsantrap.ll
index d02a12b6c3af9e..0a8ea3bc3e53f3 100644
--- a/llvm/test/CodeGen/X86/unreachable-ubsantrap.ll
+++ b/llvm/test/CodeGen/X86/unreachable-ubsantrap.ll
@@ -1,9 +1,14 @@
-; RUN: llc -o - %s -mtriple=x86_64-linux-gnu | FileCheck %s --check-prefixes=CHECK
-; RUN: llc -global-isel -o - %s -mtriple=x86_64-linux-gnu | FileCheck %s --check-prefixes=CHECK
-; RUN: llc -fast-isel -o - %s -mtriple=x86_64-linux-gnu | FileCheck %s --check-prefixes=CHECK
-; RUN: llc --trap-unreachable -o - %s -mtriple=x86_64-linux-gnu | FileCheck %s --check-prefixes=CHECK,TRAP_UNREACHABLE
-; RUN: llc --trap-unreachable -global-isel -o - %s -mtriple=x86_64-linux-gnu | FileCheck %s --check-prefixes=CHECK,TRAP_UNREACHABLE
-; RUN: llc --trap-unreachable -fast-isel -o - %s -mtriple=x86_64-linux-gnu | FileCheck %s --check-prefixes=CHECK,TRAP_UNREACHABLE
+; RUN: llc --trap-unreachable -o - %s -mtriple=x86_64-linux-gnu | FileCheck %s --check-prefixes=CHECK,NO_TRAP_AFTER_NORET
+; RUN: llc --trap-unreachable -global-isel -o - %s -mtriple=x86_64-linux-gnu | FileCheck %s --check-prefixes=CHECK,NO_TRAP_AFTER_NORET
+; RUN: llc --trap-unreachable -fast-isel -o - %s -mtriple=x86_64-linux-gnu | FileCheck %s --check-prefixes=CHECK,NO_TRAP_AFTER_NORET
+
+; RUN: llc --trap-unreachable=false -o - %s -mtriple=x86_64-linux-gnu | FileCheck %s --check-prefixes=CHECK,NO_TRAP_AFTER_NORET
+; RUN: llc --trap-unreachable=false -global-isel -o - %s -mtriple=x86_64-linux-gnu | FileCheck %s --check-prefixes=CHECK,NO_TRAP_AFTER_NORET
+; RUN: llc --trap-unreachable=false -fast-isel -o - %s -mtriple=x86_64-linux-gnu | FileCheck %s --check-prefixes=CHECK,NO_TRAP_AFTER_NORET
+
+; RUN: llc --trap-unreachable --no-trap-after-noreturn=false -o - %s -mtriple=x86_64-linux-gnu | FileCheck %s --check-prefixes=CHECK,TRAP_AFTER_NORET
+; RUN: llc --trap-unreachable --no-trap-after-noreturn=false -global-isel -o - %s -mtriple=x86_64-linux-gnu | FileCheck %s --check-prefixes=CHECK,TRAP_AFTER_NORET
+; RUN: llc --trap-unreachable --no-trap-after-noreturn=false -fast-isel -o - %s -mtriple=x86_64-linux-gnu | FileCheck %s --check-prefixes=CHECK,TRAP_AFTER_NORET
; CHECK-LABEL: ubsantrap:
; CHECK: ud1l 12(%eax), %eax
@@ -15,8 +20,8 @@ define i32 @ubsantrap() noreturn nounwind {
; CHECK-LABEL: ubsantrap_fn_attr:
; CHECK: callq {{_?}}ubsantrap_func
-; TRAP_UNREACHABLE: ud2
-; CHECK-NOT: ud2
+; TRAP_AFTER_NORET: ud2
+; NO_TRAP_AFTER_NORET-NOT: ud2
define i32 @ubsantrap_fn_attr() noreturn nounwind {
call void @llvm.ubsantrap(i8 12) "trap-func-name"="ubsantrap_func"
unreachable
diff --git a/llvm/test/CodeGen/X86/win64-eh-empty-block.ll b/llvm/test/CodeGen/X86/win64-eh-empty-block.ll
index 117e3e9c11a5a5..3171e35a5b8478 100644
--- a/llvm/test/CodeGen/X86/win64-eh-empty-block.ll
+++ b/llvm/test/CodeGen/X86/win64-eh-empty-block.ll
@@ -21,7 +21,7 @@
; CHECK: # %eh.resume
; CHECK: callq _Unwind_Resume
; CHECK-NEXT: # %unreachable
-; CHECK-NEXT: int3
+; CHECK-NEXT: ud2
; CHECK-NEXT: .Lfunc_end0:
%struct.as = type { ptr }
diff --git a/llvm/test/CodeGen/X86/win64-eh-trailing-statepoint.ll b/llvm/test/CodeGen/X86/win64-eh-trailing-statepoint.ll
index fa49cb80e09807..d52b4b535a754b 100644
--- a/llvm/test/CodeGen/X86/win64-eh-trailing-statepoint.ll
+++ b/llvm/test/CodeGen/X86/win64-eh-trailing-statepoint.ll
@@ -9,7 +9,7 @@ define void @foo() gc "statepoint-example" personality ptr @__gxx_personality_se
; CHECK-NEXT: .seh_endprologue
; CHECK-NEXT: callq raise
; CHECK-NEXT: .Ltmp0:
-; CHECK-NEXT: int3
+; CHECK-NEXT: ud2
; CHECK-NEXT: .seh_endproc
%statepoint_token = call token (i64, i32, ptr, i32, i32, ...) @llvm.experimental.gc.statepoint.p0(i64 2882400000, i32 0, ptr elementtype(void ()) @raise, i32 0, i32 0, i32 0, i32 0)
unreachable
diff --git a/llvm/test/CodeGen/X86/wineh-coreclr.ll b/llvm/test/CodeGen/X86/wineh-coreclr.ll
index d30f14e272fcb8..ea8ba14efb6b0b 100644
--- a/llvm/test/CodeGen/X86/wineh-coreclr.ll
+++ b/llvm/test/CodeGen/X86/wineh-coreclr.ll
@@ -321,7 +321,7 @@ unreachable:
; CHECK-NEXT: movl $2, %ecx
; CHECK-NEXT: callq f
; CHECK-NEXT: [[test2_after_f2:.+]]:
-; CHECK: int3
+; CHECK: ud2
; CHECK: [[test2_end:.*func_end.*]]:
@@ -513,7 +513,7 @@ unreachable:
; CHECK-NEXT: movl $4, %ecx
; CHECK-NEXT: callq f
; CHECK-NEXT: [[test3_after_f4:.+]]:
-; CHECK: int3
+; CHECK: ud2
; CHECK: .seh_proc [[test3_fault2:[^ ]+]]
; CHECK: # %fault2
; CHECK: .seh_endprologue
@@ -521,7 +521,7 @@ unreachable:
; CHECK-NEXT: movl $3, %ecx
; CHECK-NEXT: callq f
; CHECK-NEXT: [[test3_after_f3:.+]]:
-; CHECK: int3
+; CHECK: ud2
; CHECK: .seh_proc [[test3_fault1:[^ ]+]]
; CHECK: # %fault1
; CHECK: .seh_endprologue
@@ -529,7 +529,7 @@ unreachable:
; CHECK-NEXT: movl $2, %ecx
; CHECK-NEXT: callq f
; CHECK-NEXT: [[test3_after_f2:.+]]:
-; CHECK: int3
+; CHECK: ud2
; CHECK: [[test3_end:.*func_end.*]]:
}
diff --git a/llvm/test/CodeGen/X86/x86-shrink-wrap-unwind.ll b/llvm/test/CodeGen/X86/x86-shrink-wrap-unwind.ll
index 3349d31cad4b97..2be332b3b369d0 100644
--- a/llvm/test/CodeGen/X86/x86-shrink-wrap-unwind.ll
+++ b/llvm/test/CodeGen/X86/x86-shrink-wrap-unwind.ll
@@ -344,6 +344,7 @@ define void @with_nounwind(i1 %cond) nounwind personality ptr @my_personality {
; NOCOMPACTUNWIND-NEXT: callq throw_exception at PLT
; NOCOMPACTUNWIND-NEXT: .Ltmp1:
; NOCOMPACTUNWIND-NEXT: # %bb.2: # %unreachable
+; NOCOMPACTUNWIND-NEXT: ud2
; NOCOMPACTUNWIND-NEXT: .LBB4_3: # %landing
; NOCOMPACTUNWIND-NEXT: .Ltmp2:
; NOCOMPACTUNWIND-NEXT: popq %rax
diff --git a/llvm/test/DebugInfo/Mips/eh_frame.ll b/llvm/test/DebugInfo/Mips/eh_frame.ll
index d53bc156ef29ff..9227b0f16a684b 100644
--- a/llvm/test/DebugInfo/Mips/eh_frame.ll
+++ b/llvm/test/DebugInfo/Mips/eh_frame.ll
@@ -26,9 +26,9 @@
; CHECK-READELF-PIC-NEXT: R_MIPS_PC32
; CHECK-READELF-NEXT: .gcc_except_table
-; EXCEPT-TABLE-STATIC: 0000 ff9b1501 0c001400 00140e22 01221e00 ..........."."..
+; EXCEPT-TABLE-STATIC: 0000 ff9b1501 0c001400 00140e26 01222200 ...........&."".
; EXCEPT-TABLE-STATIC: 0010 00010000 00000000
-; EXCEPT-TABLE-PIC: 0000 ff9b1501 0c002c00 002c123e 013e2a00 ......,..,.>.>*.
+; EXCEPT-TABLE-PIC: 0000 ff9b1501 0c002c00 002c1242 013e2e00 ......,..,.B.>..
; EXCEPT-TABLE-PIC: 0010 00010000 00000000 ........
@_ZTIi = external constant ptr
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